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h8s/2237 series, h8s/2237, h8s/2235, h8s/2233 h8s/2227 series h8s/2227, h8s/2225, h8s/2223 hardware manual ade-602-154a rev. 2.0 12/15/98 hitachi ltd.
preface the h8s/2237 series and h8s/2227 series are series of high-performance microcontrollers with a 32-bit h8s/2000 cpu core, and a set of on-chip supporting functions required for system configuration. the h8s/2000 cpu can execute basic instructions in one state, and is provided with sixteen 16-bit general registers with a 32-bit internal configuration, and a concise and optimized instruction set. the cpu can handle a 16-mbyte linear address space (architecturally 4 gbytes). programs based on the high-level language c can also be run efficiently. the address space is divided into eight areas. the data bus width and access states can be selected for each of these areas, and various kinds of memory can be connected fast and easily. prom (ztata*) and mask rom versions are available, providing a quick and flexible response to conditions from ramp-up through full-scale volume production, even for applications with frequently changing specifications. on-chip supporting functions include a 16-bit timer pulse unit (tpu), 8-bit timer unit (tmr), watchdog timer (wdt), serial communication interface (sci), a/d converter, d/a converter (h8s/2237 series only), and i/o ports. in addition, an on-chip data transfer controller (dtc) is provided, enabling high-speed data transfer without cpu intervention. use of the h8s/2237 series or h8s/2227 series enables compact, high-performance systems to be implemented easily. this manual describes the hardware of the h8s/2237 series and h8s/2227 series. refer to the h8s/2600 series and h8s/2000 series programming manual for a detailed description of the instruction set. note: * ztat is a registered trademark of hitachi, ltd.
on-chip peripheral functions series h8s/2237 series h8s/2227 series product names h8s/2237, h8s/2235, h8s/2233 h8s/2227, h8s/2225, h8s/2223 bus controller (bsc) (16 bits) (16 bits) data transfer controller (dtc) available available 16-bit timer pulse unit (tpu) 6 3 8-bit timer unit (tmr) 2 2 watchdog timer (wdt) 2 2 serial communication interface (sci) 4 3 a/d converter 8 8 d/a converter 2 pc break controller 2 2
i contents section 1 overview ........................................................................................................... 1 1.1 overview.................................................................................................................... ........ 1 1.2 internal block diagrams .................................................................................................... 6 1.3 pin description............................................................................................................. ...... 8 1.3.1 pin arrangements ................................................................................................. 8 1.3.2 pin functions in each operating mode................................................................ 12 1.3.3 pin functions ........................................................................................................ 20 section 2 cpu ..................................................................................................................... 25 2.1 overview.................................................................................................................... ........ 25 2.1.1 features................................................................................................................. 2 5 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu................................... 26 2.1.3 differences from h8/300 cpu............................................................................. 27 2.1.4 differences from h8/300h cpu .......................................................................... 27 2.2 cpu operating modes....................................................................................................... 28 2.3 address space............................................................................................................... ..... 33 2.4 register configuration...................................................................................................... .34 2.4.1 overview............................................................................................................... 34 2.4.2 general registers.................................................................................................. 35 2.4.3 control registers .................................................................................................. 36 2.4.4 initial register values .......................................................................................... 38 2.5 data formats................................................................................................................ ...... 39 2.5.1 general register data formats............................................................................. 39 2.5.2 memory data formats.......................................................................................... 41 2.6 instruction set ............................................................................................................. ....... 42 2.6.1 overview............................................................................................................... 42 2.6.2 instructions and addressing modes ..................................................................... 43 2.6.3 table of instructions classified by function....................................................... 45 2.6.4 basic instruction formats..................................................................................... 55 2.6.5 notes on use of bit-manipulation instructions.................................................... 56 2.7 addressing modes and effective address calculation ..................................................... 56 2.7.1 addressing mode.................................................................................................. 56 2.7.2 effective address calculation .............................................................................. 59 2.8 processing states ........................................................................................................... .... 63 2.8.1 overview............................................................................................................... 63 2.8.2 reset state ............................................................................................................ 64 2.8.3 exception-handling state..................................................................................... 65 2.8.4 program execution state ...................................................................................... 68 2.8.5 bus-released state ............................................................................................... 68
ii 2.8.6 power-down state ................................................................................................ 68 2.9 basic timing................................................................................................................ ...... 69 2.9.1 overview............................................................................................................... 69 2.9.2 on-chip memory (rom, ram) ......................................................................... 69 2.9.3 on-chip supporting module access timing....................................................... 71 2.9.4 external address space access timing............................................................... 72 section 3 mcu operating modes ................................................................................. 73 3.1 overview.................................................................................................................... ........ 73 3.1.1 operating mode selection .................................................................................... 73 3.1.2 register configuration ......................................................................................... 74 3.2 register descriptions....................................................................................................... .. 74 3.2.1 mode control register (mdcr) .......................................................................... 74 3.2.2 system control register (syscr)....................................................................... 75 3.3 operating mode descriptions ............................................................................................ 77 3.3.1 mode 4 .................................................................................................................. 77 3.3.2 mode 5 ................................................................................................................. 77 3.3.3 mode 6 .................................................................................................................. 78 3.3.4 mode 7 .................................................................................................................. 78 3.4 pin functions in each operating mode............................................................................. 79 3.5 address map in each operating mode ............................................................................. 79 section 4 exception handling ........................................................................................ 83 4.1 overview.................................................................................................................... ........ 83 4.1.1 exception handling types and priority ............................................................... 83 4.1.2 exception handling operation ............................................................................. 84 4.1.3 exception sources and vector table ................................................................... 84 4.2 reset....................................................................................................................... ............ 86 4.2.1 overview............................................................................................................... 86 4.2.2 reset types........................................................................................................... 86 4.2.3 reset sequence..................................................................................................... 87 4.2.4 interrupts after reset............................................................................................. 89 4.2.5 state of on-chip supporting modules after reset release ................................. 89 4.3 traces...................................................................................................................... ........... 90 4.4 interrupts .................................................................................................................. .......... 91 4.5 trap instruction ............................................................................................................ ..... 92 4.6 stack status after exception handling .............................................................................. 93 4.7 notes on use of the stack.................................................................................................. 9 4 section 5 interrupt controller ......................................................................................... 95 5.1 overview.................................................................................................................... ........ 95 5.1.1 features................................................................................................................. 9 5 5.1.2 block diagram...................................................................................................... 96
iii 5.1.3 pin configuration ................................................................................................. 97 5.1.4 register configuration ......................................................................................... 97 5.2 register descriptions....................................................................................................... .. 98 5.2.1 system control register (syscr)....................................................................... 98 5.2.2 interrupt priority registers a to k, o (ipra to iprk, irpo) ............................ 99 5.2.3 irq enable register (ier)................................................................................... 100 5.2.4 irq sense control registers h and l (iscrh, iscrl)..................................... 101 5.2.5 irq status register (isr) .................................................................................... 102 5.3 interrupt sources........................................................................................................... ..... 103 5.3.1 external interrupts ................................................................................................ 103 5.3.2 internal interrupts ................................................................................................. 104 5.3.3 interrupt exception handling vector table ......................................................... 104 5.4 interrupt operation......................................................................................................... .... 108 5.4.1 interrupt control modes and interrupt operation................................................. 108 5.4.2 interrupt control mode 0...................................................................................... 111 5.4.3 interrupt control mode 2...................................................................................... 113 5.4.4 interrupt exception handling sequence............................................................... 115 5.4.5 interrupt response times..................................................................................... 116 5.5 usage notes ................................................................................................................. ...... 117 5.5.1 contention between interrupt generation and disabling..................................... 117 5.5.2 instructions that disable interrupts....................................................................... 118 5.5.3 times when interrupts are disabled .................................................................... 118 5.5.4 interrupts during execution of eepmov instruction .......................................... 118 5.6 dtc activation by interrupt ............................................................................................. 119 5.6.1 overview............................................................................................................... 119 5.6.2 block diagram...................................................................................................... 119 5.6.3 operation .............................................................................................................. 120 section 6 pc break controller (pbc) ......................................................................... 123 6.1 overview.................................................................................................................... ........ 123 6.1.1 features................................................................................................................. 1 23 6.1.2 block diagram...................................................................................................... 124 6.1.3 register configuration ......................................................................................... 125 6.2 register descriptions....................................................................................................... .. 125 6.2.1 break address register a (bara) ..................................................................... 125 6.2.2 break address register b (barb) ...................................................................... 126 6.2.3 break control register a (bcra)....................................................................... 126 6.2.4 break control register b (bcrb) ....................................................................... 128 6.2.5 module stop control register c (mstpcrc) .................................................... 128 6.3 operation ................................................................................................................... ........ 129 6.3.1 pc break interrupt due to instruction fetch........................................................ 129 6.3.2 pc break interrupt due to data access ............................................................... 129 6.3.3 notes on pc break interrupt handling................................................................. 130
iv 6.3.4 operation in transitions to power-down modes................................................. 130 6.3.5 pc break operation in continuous data transfer ............................................... 131 6.3.6 when instruction execution is delayed by one state ......................................... 132 6.3.7 additional notes................................................................................................... 133 section 7 bus controller .................................................................................................. 135 7.1 overview.................................................................................................................... ........ 135 7.1.1 features................................................................................................................. 1 35 7.1.2 block diagram...................................................................................................... 136 7.1.3 pin configuration ................................................................................................. 137 7.1.4 register configuration ......................................................................................... 138 7.2 register descriptions....................................................................................................... .. 139 7.2.1 bus width control register (abwcr) ............................................................... 139 7.2.2 access state control register (astcr).............................................................. 140 7.2.3 wait control registers h and l (wcrh, wcrl) .............................................. 141 7.2.4 bus control register h (bcrh) .......................................................................... 145 7.2.5 bus control register l (bcrl)........................................................................... 147 7.2.6 pin function control register (pfcr)................................................................. 148 7.3 overview of bus control................................................................................................... 15 0 7.3.1 area partitioning................................................................................................... 150 7.3.2 bus specifications ................................................................................................ 151 7.3.3 memory interfaces................................................................................................ 152 7.3.4 interface specifications for each area................................................................. 153 7.3.5 chip select signals............................................................................................... 154 7.4 basic bus interface ......................................................................................................... ... 155 7.4.1 overview............................................................................................................... 155 7.4.2 data size and data alignment ............................................................................. 155 7.4.3 valid strobes ....................................................................................................... 157 7.4.4 basic timing......................................................................................................... 158 7.4.5 wait control ......................................................................................................... 166 7.5 burst rom interface ......................................................................................................... 168 7.5.1 overview............................................................................................................... 168 7.5.2 basic timing......................................................................................................... 168 7.5.3 wait control ......................................................................................................... 170 7.6 idle cycle.................................................................................................................. ......... 171 7.6.1 operation .............................................................................................................. 171 7.6.2 pin states in idle cycle......................................................................................... 174 7.7 bus release................................................................................................................. ....... 175 7.7.1 overview............................................................................................................... 175 7.7.2 operation .............................................................................................................. 175 7.7.3 pin states in external bus released state ............................................................ 176 7.7.4 transition timing................................................................................................. 177 7.7.5 usage note ........................................................................................................... 178
v 7.8 bus arbitration............................................................................................................. ...... 178 7.8.1 overview............................................................................................................... 178 7.8.2 operation .............................................................................................................. 178 7.8.3 bus transfer timing............................................................................................. 179 7.8.4 external bus release usage note ........................................................................ 179 7.9 resets and the bus controller............................................................................................ 179 section 8 data transfer controller (dtc) ................................................................. 181 8.1 overview.................................................................................................................... ........ 181 8.1.1 features................................................................................................................. 1 81 8.1.2 block diagram...................................................................................................... 182 8.1.3 register configuration ......................................................................................... 183 8.2 register descriptions....................................................................................................... .. 184 8.2.1 dtc mode register a (mra)............................................................................. 184 8.2.2 dtc mode register b (mrb) ............................................................................. 186 8.2.3 dtc source address register (sar) .................................................................. 187 8.2.4 dtc destination address register (dar) .......................................................... 187 8.2.5 dtc transfer count register a (cra)............................................................... 187 8.2.6 dtc transfer count register b (crb) ............................................................... 188 8.2.7 dtc enable registers (dtcer) ......................................................................... 188 8.2.8 dtc vector register (dtvecr) ........................................................................ 189 8.2.9 module stop control register a (mstpcra).................................................... 190 8.3 operation ................................................................................................................... ........ 191 8.3.1 overview............................................................................................................... 191 8.3.2 activation sources................................................................................................ 193 8.3.3 dtc vector table ................................................................................................ 194 8.3.4 location of register information in address space............................................. 197 8.3.5 normal mode........................................................................................................ 198 8.3.6 repeat mode......................................................................................................... 199 8.3.7 block transfer mode............................................................................................ 200 8.3.8 chain transfer ...................................................................................................... 202 8.3.9 operation timing ................................................................................................. 203 8.3.10 number of dtc execution states ........................................................................ 204 8.3.11 procedures for using dtc ................................................................................... 206 8.3.12 examples of use of the dtc................................................................................ 207 8.4 interrupts .................................................................................................................. .......... 209 8.5 usage notes ................................................................................................................. ...... 209 section 9 i/o ports ............................................................................................................. 211 9.1 overview.................................................................................................................... ........ 211 9.2 port 1...................................................................................................................... ............ 216 9.2.1 overview............................................................................................................... 216 9.2.2 register configuration ......................................................................................... 217
vi 9.2.3 pin functions ........................................................................................................ 219 9.3 port 3...................................................................................................................... ............ 227 9.3.1 overview............................................................................................................... 227 9.3.2 register configuration ......................................................................................... 227 9.3.3 pin functions ........................................................................................................ 230 9.4 port 4...................................................................................................................... ............ 232 9.4.1 overview............................................................................................................... 232 9.4.2 register configuration ......................................................................................... 232 9.4.3 pin functions ........................................................................................................ 233 9.5 port 7...................................................................................................................... ............ 234 9.5.1 overview............................................................................................................... 234 9.5.2 register configuration ......................................................................................... 235 9.5.3 pin functions ........................................................................................................ 237 9.6 port 9...................................................................................................................... ............ 239 9.6.1 overview............................................................................................................... 239 9.6.2 register configuration ......................................................................................... 239 9.6.3 pin functions ........................................................................................................ 240 9.7 port a...................................................................................................................... ........... 240 9.7.1 overview............................................................................................................... 240 9.7.2 register configuration ......................................................................................... 241 9.7.3 pin functions ........................................................................................................ 243 9.7.4 mos input pull-up function ............................................................................... 246 9.8 port b ...................................................................................................................... ........... 247 9.8.1 overview............................................................................................................... 247 9.8.2 register configuration ......................................................................................... 248 9.8.3 pin functions ........................................................................................................ 250 9.8.4 mos input pull-up function ............................................................................... 259 9.9 port c ...................................................................................................................... ........... 260 9.9.1 overview............................................................................................................... 260 9.9.2 register configuration ......................................................................................... 261 9.9.3 pin functions in each mode................................................................................. 263 9.9.4 mos input pull-up function ............................................................................... 265 9.10 port d..................................................................................................................... ............ 266 9.10.1 overview............................................................................................................... 26 6 9.10.2 register configuration ......................................................................................... 267 9.10.3 pin functions in each mode................................................................................. 269 9.10.4 mos input pull-up function ............................................................................... 270 9.11 port e ..................................................................................................................... ............ 271 9.11.1 overview............................................................................................................... 27 1 9.11.2 register configuration ......................................................................................... 272 9.11.3 pin functions in each mode................................................................................. 274 9.11.4 mos input pull-up function ............................................................................... 275 9.12 port f ..................................................................................................................... ............ 277
vii 9.12.1 overview............................................................................................................... 27 7 9.12.2 register configuration ......................................................................................... 278 9.12.3 pin functions ........................................................................................................ 279 9.13 port g..................................................................................................................... ............ 282 9.13.1 overview............................................................................................................... 28 2 9.13.2 register configuration ......................................................................................... 283 9.13.3 pin functions ........................................................................................................ 285 section 10 16-bit timer pulse unit (tpu) .................................................................. 287 10.1 overview................................................................................................................... ......... 287 10.1.1 features................................................................................................................. 287 10.1.2 block diagram...................................................................................................... 291 10.1.3 pin configuration ................................................................................................. 293 10.1.4 register configuration ......................................................................................... 295 10.2 register descriptions...................................................................................................... ... 297 10.2.1 timer control register (tcr) ............................................................................. 297 10.2.2 timer mode register (tmdr)............................................................................. 302 10.2.3 timer i/o control register (tior) ..................................................................... 304 10.2.4 timer interrupt enable register (tier)............................................................... 317 10.2.5 timer status register (tsr) ................................................................................ 320 10.2.6 timer counter (tcnt)......................................................................................... 323 10.2.7 timer general register (tgr)............................................................................. 324 10.2.8 timer start register (tstr) ................................................................................ 325 10.2.9 timer synchro register (tsyr) .......................................................................... 326 10.2.10 module stop control register a (mstpcra).................................................... 327 10.3 interface to bus master.................................................................................................... .. 328 10.3.1 16-bit registers .................................................................................................... 328 10.3.2 8-bit registers ...................................................................................................... 328 10.4 operation .................................................................................................................. ......... 330 10.4.1 overview............................................................................................................... 33 0 10.4.2 basic functions..................................................................................................... 331 10.4.3 synchronous operation ........................................................................................ 337 10.4.4 buffer operation................................................................................................... 339 10.4.5 cascaded operation (h8s/2237 series only) ....................................................... 343 10.4.6 pwm modes......................................................................................................... 345 10.4.7 phase counting mode........................................................................................... 350 10.5 interrupts ................................................................................................................. ........... 356 10.5.1 interrupt sources and priorities ............................................................................ 356 10.5.2 dtc activation .................................................................................................... 358 10.5.3 a/d converter activation..................................................................................... 358 10.6 operation timing........................................................................................................... .... 359 10.6.1 input/output timing............................................................................................. 359 10.6.2 interrupt signal timing ........................................................................................ 363
viii 10.7 usage notes ................................................................................................................ ....... 367 section 11 8-bit timers (tmr) ....................................................................................... 377 11.1 overview................................................................................................................... ......... 377 11.1.1 features................................................................................................................. 377 11.1.2 block diagram...................................................................................................... 378 11.1.3 pin configuration ................................................................................................. 379 11.1.4 register configuration ......................................................................................... 379 11.2 register descriptions...................................................................................................... ... 380 11.2.1 timer counters 0 and 1 (tcnt0, tcnt1).......................................................... 380 11.2.2 time constant registers a0 and a1 (tcora0, tcora1) ............................... 380 11.2.3 time constant registers b0 and b1 (tcorb0, tcorb1) ................................ 381 11.2.4 time control registers 0 and 1 (tcr0, tcr1)................................................... 381 11.2.5 timer control/status registers 0 and 1 (tcsr0, tcsr1) .................................. 384 11.2.6 module stop control register a (mstpcra).................................................... 387 11.3 operation .................................................................................................................. ......... 388 11.3.1 tcnt incrementation timing.............................................................................. 388 11.3.2 compare match timing ....................................................................................... 389 11.3.3 timing of external reset on tcnt .................................................................. 391 11.3.4 timing of overflow flag (ovf) setting.............................................................. 391 11.3.5 operation with cascaded connection .................................................................. 392 11.4 interrupts ................................................................................................................. ........... 393 11.4.1 interrupt sources and dtc activation................................................................. 393 11.4.2 a/d converter activation..................................................................................... 393 11.5 sample application ......................................................................................................... .. 394 11.6 usage notes ................................................................................................................ ....... 395 11.6.1 contention between tcnt write and clear ........................................................ 395 11.6.2 contention between tcnt write and increment................................................. 396 11.6.3 contention between tcor write and compare match....................................... 397 11.6.4 contention between compare matches a and b ................................................. 398 11.6.5 switching of internal clocks and tcnt operation ............................................ 398 11.6.6 interrupts and module stop mode........................................................................ 400 section 12 watchdog timer (wdt) .............................................................................. 401 12.1 overview................................................................................................................... ......... 401 12.1.1 features................................................................................................................. 401 12.1.2 block diagram...................................................................................................... 402 12.1.3 pin configuration ................................................................................................. 403 12.1.4 register configuration ......................................................................................... 404 12.2 register descriptions...................................................................................................... ... 405 12.2.1 timer counter (tcnt)......................................................................................... 405 12.2.2 timer control/status register (tcsr) ................................................................ 405 12.2.3 reset control/status register (rstcsr) (wdt0 only)..................................... 410
ix 12.2.4 pin function control register (pfcr)................................................................. 412 12.2.5 notes on register access ..................................................................................... 413 12.3 operation .................................................................................................................. ......... 415 12.3.1 watchdog timer operation .................................................................................. 415 12.3.2 interval timer operation ...................................................................................... 417 12.3.3 timing of setting of overflow flag (ovf) ......................................................... 418 12.3.4 timing of setting of watchdog timer overflow flag (wovf) ......................... 418 12.4 interrupts ................................................................................................................. ........... 419 12.5 usage notes ................................................................................................................ ....... 420 12.5.1 contention between timer counter (tcnt) write and increment ..................... 420 12.5.2 changing value of pss and cks2 to cks0........................................................ 420 12.5.3 switching between watchdog timer mode and interval timer mode................ 420 12.5.4 internal reset in watchdog timer mode ............................................................. 421 section 13 serial communication interface (sci) ..................................................... 423 13.1 overview................................................................................................................... ......... 423 13.1.1 features................................................................................................................. 423 13.1.2 block diagram...................................................................................................... 425 13.1.3 pin configuration ................................................................................................. 426 13.1.4 register configuration ......................................................................................... 427 13.2 register descriptions...................................................................................................... ... 429 13.2.1 receive shift register (rsr)............................................................................... 429 13.2.2 receive data register (rdr)............................................................................... 429 13.2.3 transmit shift register (tsr).............................................................................. 430 13.2.4 transmit data register (tdr) ............................................................................. 430 13.2.5 serial mode register (smr) ................................................................................ 431 13.2.6 serial control register (scr) .............................................................................. 434 13.2.7 serial status register (ssr)................................................................................. 438 13.2.8 bit rate register (brr)....................................................................................... 442 13.2.9 smart card mode register (scmr)..................................................................... 449 13.2.10 module stop control registers b and c (mstpcrb, mstpcrc).................... 450 13.3 operation .................................................................................................................. ......... 452 13.3.1 overview............................................................................................................... 45 2 13.3.2 operation in asynchronous mode........................................................................ 454 13.3.3 multiprocessor communication function ............................................................ 465 13.3.4 operation in clocked synchronous mode ........................................................... 473 13.4 sci interrupts............................................................................................................. ........ 481 13.5 usage notes ................................................................................................................ ....... 483 section 14 smart card interface ...................................................................................... 493 14.1 overview................................................................................................................... ......... 493 14.1.1 features................................................................................................................. 493 14.1.2 block diagram...................................................................................................... 494
x 14.1.3 pin configuration ................................................................................................. 495 14.1.4 register configuration ......................................................................................... 496 14.2 register descriptions...................................................................................................... ... 498 14.2.1 smart card mode register (scmr)..................................................................... 498 14.2.2 serial status register (ssr)................................................................................. 499 14.2.3 serial mode register (smr) ................................................................................ 501 14.2.4 serial control register (scr) .............................................................................. 503 14.3 operation .................................................................................................................. ......... 504 14.3.1 overview............................................................................................................... 50 4 14.3.2 pin connections .................................................................................................... 504 14.3.3 data format .......................................................................................................... 506 14.3.4 register settings................................................................................................... 508 14.3.5 clock.................................................................................................................... . 510 14.3.6 data transfer operations ..................................................................................... 512 14.3.7 operation in gsm mode ...................................................................................... 519 14.3.8 operation in block transfer mode....................................................................... 520 14.4 usage notes ................................................................................................................ ....... 521 section 15 a/d converter ................................................................................................. 525 15.1 overview................................................................................................................... ......... 525 15.1.1 features................................................................................................................. 525 15.1.2 block diagram...................................................................................................... 526 15.1.3 pin configuration ................................................................................................. 527 15.1.4 register configuration ......................................................................................... 528 15.2 register descriptions...................................................................................................... ... 529 15.2.1 a/d data registers a to d (addra to addrd).............................................. 529 15.2.2 a/d control/status register (adcsr) ................................................................ 530 15.2.3 a/d control register (adcr)............................................................................. 532 15.2.4 module stop control register a (mstpcra).................................................... 533 15.3 interface to bus master.................................................................................................... .. 534 15.4 operation .................................................................................................................. ......... 535 15.4.1 single mode (scan = 0) ..................................................................................... 535 15.4.2 scan mode (scan = 1) ....................................................................................... 537 15.4.3 input sampling and a/d conversion time .......................................................... 539 15.4.4 external trigger input timing ............................................................................. 540 15.5 interrupts ................................................................................................................. ........... 541 15.6 usage notes ................................................................................................................ ....... 541 section 16 d/a converter ................................................................................................. 547 16.1 overview................................................................................................................... ......... 547 16.1.1 features................................................................................................................. 547 16.1.2 block diagram...................................................................................................... 548 16.1.3 pin configuration ................................................................................................. 549
xi 16.1.4 register configuration ......................................................................................... 549 16.2 register descriptions...................................................................................................... ... 549 16.2.1 d/a data registers 0 and 1 (dadr0, dadr1).................................................. 549 16.2.2 d/a control register (dacr)............................................................................. 550 16.2.3 module stop control register a (mstpcra).................................................... 551 16.3 operation .................................................................................................................. ......... 552 section 17 ram ................................................................................................................... 555 17.1 overview................................................................................................................... ......... 555 17.1.1 block diagram...................................................................................................... 555 17.1.2 register configuration ......................................................................................... 556 17.2 register descriptions...................................................................................................... ... 556 17.2.1 system control register (syscr)....................................................................... 556 17.3 operation .................................................................................................................. ......... 557 17.4 usage note................................................................................................................. ........ 557 section 18 rom ................................................................................................................... 559 18.1 overview................................................................................................................... ......... 559 18.1.1 block diagram...................................................................................................... 559 18.2 operation .................................................................................................................. ......... 560 18.3 prom mode.................................................................................................................. .... 561 18.3.1 prom mode setting ............................................................................................ 561 18.3.2 socket adapter and memory map ....................................................................... 561 18.4 programming ................................................................................................................ ..... 565 18.4.1 overview............................................................................................................... 56 5 18.4.2 programming and verification ............................................................................. 565 18.4.3 programming precautions..................................................................................... 570 18.4.4 reliability of programmed data........................................................................... 571 section 19 clock pulse generator ................................................................................... 573 19.1 overview................................................................................................................... ......... 573 19.1.1 block diagram...................................................................................................... 573 19.1.2 register configuration ......................................................................................... 574 19.2 register descriptions...................................................................................................... ... 574 19.2.1 system clock control register (sckcr)............................................................ 574 19.2.2 low-power control register (lpwrcr)............................................................ 575 19.3 system clock oscillator .................................................................................................... 579 19.3.1 connecting a crystal resonator ........................................................................... 579 19.3.2 external clock input............................................................................................. 581 19.4 duty adjustment circuit.................................................................................................... 585 19.5 medium-speed clock divider........................................................................................... 585 19.6 bus master clock selection circuit................................................................................... 585 19.7 subclock oscillator........................................................................................................ .... 585
xii 19.8 subclock wavefrom shaping circuit ................................................................................ 587 19.9 notes on crystal resonator ............................................................................................... 58 7 section 20 power-down modes ...................................................................................... 589 20.1 overview................................................................................................................... ......... 589 20.1.1 register configuration ......................................................................................... 593 20.2 register descriptions...................................................................................................... ... 593 20.2.1 standby control register (sbycr)..................................................................... 593 20.2.2 system clock control register (sckcr) ........................................................... 595 20.2.3 low-power control register (lpwrcr)............................................................ 596 20.2.4 timer control/status register (tcsr) ................................................................ 598 20.2.5 module stop control register (mstpcr)........................................................... 599 20.3 medium-speed mode......................................................................................................... 6 00 20.4 sleep mode ................................................................................................................. ....... 601 20.4.1 sleep mode........................................................................................................... 601 20.4.2 clearing sleep mode ............................................................................................ 601 20.5 module stop mode ........................................................................................................... . 602 20.5.1 module stop mode ............................................................................................... 602 20.5.2 usage note ........................................................................................................... 603 20.6 software standby mode..................................................................................................... 6 04 20.6.1 software standby mode ....................................................................................... 604 20.6.2 clearing software standby mode......................................................................... 604 20.6.3 setting oscillation stabilization time after clearing software standby mode... 605 20.6.4 software standby mode application example .................................................... 605 20.6.5 usage notes .......................................................................................................... 606 20.7 hardware standby mode ................................................................................................... 606 20.7.1 hardware standby mode ...................................................................................... 606 20.7.2 hardware standby mode timing ......................................................................... 607 20.8 watch mode................................................................................................................. ...... 608 20.8.1 watch mode ......................................................................................................... 608 20.8.2 clearing watch mode........................................................................................... 608 20.8.3 usage notes .......................................................................................................... 609 20.9 subsleep mode.............................................................................................................. ..... 609 20.9.1 subsleep mode ..................................................................................................... 609 20.9.2 clearing subsleep mode....................................................................................... 609 20.10 subactive mode ............................................................................................................ ..... 610 20.10.1 subactive mode .................................................................................................... 610 20.10.2 clearing subactive mode ..................................................................................... 610 20.11 direct transition ......................................................................................................... ....... 611 20.11.1 overview of direct transition.............................................................................. 611 20.12 ? clock output disabling function................................................................................... 611
xiii section 21 electrical characteristics .............................................................................. 613 21.1 absolute maximum ratings .............................................................................................. 613 21.2 power supply voltage and operating frequency range .................................................. 614 21.3 dc characteristics ......................................................................................................... .... 615 21.4 ac characteristics ......................................................................................................... .... 621 21.4.1 clock timing ........................................................................................................ 622 21.4.2 control signal timing .......................................................................................... 624 21.4.3 bus timing ........................................................................................................... 626 21.4.4 timing of on-chip supporting modules ............................................................. 634 21.5 a/d conversion characteristics ........................................................................................ 640 21.6 d/a convervion characteristics ........................................................................................ 641 21.7 usage note................................................................................................................. ........ 641 appendix a instruction set ................................................................................................ 643 a.1 instruction list............................................................................................................ ....... 643 a.2 instruction codes ........................................................................................................... .... 667 a.3 operation code map.......................................................................................................... 681 a.4 number of states required for instruction execution....................................................... 685 a.5 bus states during instruction execution........................................................................... 699 a.6 condition code modification ............................................................................................ 713 appendix b internal i/o register .................................................................................... 719 b.1 addresses................................................................................................................... ........ 719 b.2 functions................................................................................................................... ......... 726 appendix c i/o port block diagrams ............................................................................ 844 c.1 port 1 block diagrams....................................................................................................... 844 c.2 port 3 block diagrams....................................................................................................... 848 c.3 port 4 block diagram ........................................................................................................ 852 c.4 port 7 block diagrams....................................................................................................... 853 c.5 port 9 block diagram ........................................................................................................ 860 c.6 port a block diagrams...................................................................................................... 8 61 c.7 port b block diagram ....................................................................................................... 8 65 c.8 port c block diagram ....................................................................................................... 8 66 c.9 port d block diagram ....................................................................................................... 8 67 c.10 port e block diagram....................................................................................................... . 868 c.11 port f block diagrams...................................................................................................... . 869 c.12 port g block diagrams...................................................................................................... 875 appendix d pin states ......................................................................................................... 879 d.1 port states in each processing state.................................................................................. 879
xiv appendix e timing of transition to and recovery from hardware standby mode ................................................................................................ 882 appendix f product code lineup ................................................................................... 883 appendix g package dimensions .................................................................................... 884
1 section 1 overview 1.1 overview the h8s/2237 series and h8s/2227 series are series of microcomputers (mcus: microcomputer units), built around the h8s/2000 cpu, employing hitachi's proprietary architecture, and equipped with the on-chip peripheral functions necessary for system configuration. the h8s/2000 cpu has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-mbyte linear address space. the instruction set is upward-compatible with h8/300 and h8/300h cpu instructions at the object-code level, facilitating migration from the h8/300, h8/300l, or h8/300h series. on-chip peripheral functions required for system configuration include data transfer controller (dtc) bus masters, rom and ram memory, a16-bit timer-pulse unit (tpu), 8-bit timer (tmr), watchdog timer (wdt), serial communication interface (sci), a/d converter, d/a converter (h8s/2237 series only), and i/o ports. the on-chip rom is either prom (ztat*) or mask rom, with a capacity of 128 or 64 kbytes. rom is connected to the cpu via a 16-bit data bus, enabling both byte and word data to be accessed in one state. instruction fetching has been speeded up, and processing speed increased. four operating modes, modes 4 to 7, are provided, and there is a choice of single-chip mode or external expansion mode. the features of the h8s/2237 series and h8s/2227 series are shown in table 1-1. note: * ztat is a trademark of hitachi, ltd.
2 table 1-1 overview item specification cpu general-register machine ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) high-speed operation suitable for realtime control ? maximum clock rate 10 mhz: ztat version 13 mhz: mask rom version ? high-speed arithmetic operations (at 10 mhz operation) 8/16/32-bit register-register add/subtract : 100 ns 16 16-bit register-register multiply : 2000 ns 32 ? 16-bit register-register divide : 2000 ns instruction set suitable for high-speed operation ? sixty-five basic instructions ? 8/16/32-bit move/arithmetic and logic instructions ? unsigned/signed multiply and divide instructions ? powerful bit-manipulation instructions two cpu operating modes ? normal mode : 64-kbyte address space (not available in the h8s/2237 series and h8s/2227 series) ? advanced mode : 16-mbyte address space bus controller address space divided into 8 areas, with bus specifications settable independently for each area chip select output possible for each area choice of 8-bit or 16-bit access space for each area 2-state or 3-state access space can be designated for each area number of program wait states can be set for each area burst rom directly connectable external bus release function data transfer controller (dtc) can be activated by internal interrupt or software multiple transfers or multiple types of transfer possible for one activation source transfer possible in repeat mode, block transfer mode, etc. request can be sent to cpu for interrupt that activated dtc
3 table 1-1 overview (cont) item specification 16-bit timer-pulse unit (tpu) 6-channel 16-bit timer on-chip h8s/2237 series: 6 channels h8s/2227 series: 3 channels pulse i/o processing capability for up to 16 pins' h8s/2237 series: max. 16 pins h8s/2227 series: max. 8 pins automatic 2-phase encoder count capability 8-bit timer (tmr) 2 channels 8-bit up-counter (external event count capability) two time constant registers two-channel connection possible watchdog timer (wdt) 2 channels watchdog timer or interval timer selectable can operate on subclock (1 channel only) serial communication interface (sci) h8s/2237 series: 4 channels (sci0?ci3) h8s/2227 series: 3 channels (sci0, sci1, sci3) asynchronous mode or synchronous mode selectable multiprocessor communication function smart card interface function a/d converter resolution: 10 bits input: 8 channels 13.4 m s minimum conversion time (at 10 mhz operation) single or scan mode selectable sample and hold circuit a/d conversion can be activated by external trigger or timer trigger d/a converter (h8s/2237 series only) resolution: 8 bits output: 2 channels i/o ports 72 i/o pins, 10 input-only pins
4 table 1-1 overview (cont) item specification memory prom or mask rom high-speed static ram product name rom ram h8s/2237, h8s/2227 128 kbytes 16 kbytes h8s/2235, h8s/2225 128 kbytes 4 kbytes h8s/2233, h8s/2223 64 bytes 4 kbytes interrupt controller nine external interrupt pins (nmi, irq0 to irq7 ) 53 internal interrupt sources eight priority levels settable pc break controller supports debugging functions by means of pc break interrupts two break channels power-down state medium-speed mode sleep mode module stop mode software standby mode hardware standby mode subclock operation (subactive mode, subsleep mode, watch mode) operating modes four mcu operating modes external data bus mode description on-chip rom initial value maximum value 4 advanced on-chip rom disabled expansion mode disabled 16 bits 16 bits 5 on-chip rom disabled expansion mode disabled 8 bits 16 bits 6 on-chip rom enabled expansion mode enabled 8 bits 16 bits 7 single-chip mode enabled cpu operating mode
5 table 1-1 overview (cont) item specification clock pulse generator two on chip clock pulse generators system clock pulse generator: 2 to 10 mhz (ztat version) 2 to 13 mhz (mask rom version) built-in duty correction circuit subclock pulse generator: 32.768 khz packages 100-pin plastic tqfp (tfp-100b, tfp-100g) 100-pin plastic qfp (fp-100a, fp-100b) product lineup model name mask rom version ztat version rom/ram (bytes) packages hd6432237 hd6432235 hd6432233 hd6472237 128 k/16 k 128 k/4 k 64 k/4 k tfp-100b tfp-100g fp-100a fp-100b hd6432227 128k/16 k hd6432225 128 k/4 k hd6432223 64 k/4 k
6 1.2 internal block diagrams figures 1-1 and 1-2 show internal block diagrams of the h8s/2237 series and h8s/2227 series. pe7/d7 pe6/d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0/d0 internal data bus peripheral data bus peripheral address bus pd7 / d15 pd6 / d14 pd5 / d13 pd4 / d12 pd3 / d11 pd2 / d10 pd1/d9 pd0/d8 port d vcc vcc vss vss pa3 / a19/sck2 pa2 / a18/rxd2 pa1 / a17/txd2 pa0 / a16 pb7 / a15/tiocb5 pb6 / a14/tioca5 pb5 / a13/tiocb4 pb4 / a12/tioca4 pb3 / a11/tiocd3 pb2/a10/tiocc3 pb1 / a9/tiocb3 pb0 / a8/tioca3 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 p36 p35 / sck1/irq5 p34 / rxd1 p33 / txd1 p32 / sck0/irq4 p31 / rxd0 p30 / txd0 p97 / da1 p96 /da0 p47 / an7 p46 / an6 p45 / an5 p44 / an4 p43 / an3 p42 / an2 p41 / an1 p40 / an0 vref avcc avss p10 / tioca0 /a20 p11 / tiocb0 /a21 p12 / tiocc0 / tclka/a22 p13 / tiocd0 / tclkb/a23 p14 / tioca1/irq0 p15 / tiocb1 / tclkc p16 / tioca2/irq1 p17 / tiocb2/ tclkd p70/tmri01/ tmci01/cs4 p71 / cs5 p72 / tmo0/ cs6 p73 / tmo1/ cs7 p74 / mres p75 / sck3 p76 / rxd3 p77 / txd3 pg4 / cs0 pg3 / cs1 pg2 / cs2 pg1 / cs3/irq7 pg0 / irq6 pf7/ pf6/as pf5/rd pf4 / hwr pf3 / lwr/adtrg/irq3 pf2 / wait pf1 / back/buzz pf0 / breq/irq2 pc break controller (2 channels) rom ram tpu (6 channels) sci (4 channels) d/a converter (2 channels) 8-bit timer (2 channels) a/d converter (8 channels) md2 md1 md0 extal xtal osc1 osc2 stby res nmi fwe h8s/2000 cpu dtc wdt0 wdt1 (subclock operation) interrupt controller port e port 4 port 1 port 7 internal address bus subclock clock pulse generator system clock pulse generator port a port b bus controller port c port 3 port 9 port g port f figure 1-1 h8s/2237 series internal block diagram
7 pe7/d7 pe6/d6 pe5/d5 pe4/d4 pe3/d3 pe2/d2 pe1/d1 pe0/d0 internal data bus peripheral data bus peripheral address bus pd7 / d15 pd6 / d14 pd5 / d13 pd4 / d12 pd3 / d11 pd2 / d10 pd1/d9 pd0/d8 port d vcc vcc vss vss pa3 / a19 pa2 / a18 pa1 / a17 pa0 / a16 pb7 / a15 pb6 / a14 pb5 / a13 pb4 / a12 pb3 / a11 pb2/a10 pb1/a9 pb0/a8 pc7/a7 pc6/a6 pc5/a5 pc4/a4 pc3/a3 pc2/a2 pc1/a1 pc0/a0 p36 p35 / sck1/ irq5 p34 / rxd1 p33 / txd1 p32 / sck0/ irq4 p31 / rxd0 p30 / txd0 p97 p96 p47 / an7 p46 / an6 p45 / an5 p44 / an4 p43 / an3 p42 / an2 p41 / an1 p40 / an0 vref avcc avss p10 / tioca0 /a20 p11 / tiocb0 /a21 p12 / tiocc0 / tclka/a22 p13 / tiocd0 / tclkb/a23 p14 / tioca1/ irq0 p15 / tiocb1 / tclkc p16 / tioca2/ irq1 p17 / tiocb2/ tclkd p70/tmri01/ tmci01/ cs4 p71 / cs5 p72 / tmo0/ cs6 p73 / tmo1/ cs7 p74 / mres p75 / sck3 p76 / rxd3 p77 / txd3 pg4 / cs0 pg3 / cs1 pg2 / cs2 pg1 / cs3 / irq7 pg0 / irq6 pf7/? pf6 / as pf5 / rd pf4 / hwr pf3 / lwr / adtrg / irq3 pf2 / wait pf1 / back /buzz pf0 / breq / irq2 pc break controller (2 channels) rom ram tpu (3 channels) sci (3 channels) 8-bit timer (2 channels) a/d converter (8 channels) md2 md1 md0 extal xtal osc1 osc2 stby res nmi fwe h8s/2000 cpu dtc wdt0 wdt1 (subclock operation) interrupt controller port e internal address bus port a port b port c port 3 port 9 port 4 port 1 port 7 port g port f subclock clock pulse generator system clock pulse generator bus controller figure 1-2 h8s/2227 series internal block diagram
8 1.3 pin description 1.3.1 pin arrangements (1) h8s/2237 series pin arrangements figures 1-3 and 1-4 show the pin arrangements of the h8s/2237 series. p30/txd0 p31/rxd0 p32/sck0/ irq4 p33/txd1 p34/rxd1 p35/sck1/ irq5 p36 p77/txd3 p76/rxd3 p75/sck3 p74/ mres p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci01/ cs4 pg0/ irq6 pg1/ cs3 / irq7 pg2/ cs2 pg3/ cs1 pg4/ cs0 pe0/d0 pe1/d1 pe2/d2 pe3/d3 pe4/d4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 pf0/ breq / irq2 pf1/ back /buzz pf2/ wait pf3/ lwr / adtrg / irq3 pf4/ hwr pf5/ rd pf6/ as pf7/? md2 fwe extal vss xtal vcc stby nmi res osc1 osc2 md1 md0 avcc vref p40/an0 p41/an1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p42/an2 p43/an3 p44/an4 p45/an5 p46/an6 p47/an7 p96/da0 p97/da1 p17/tiocb2/tclkd p16/tioca2/ irq1 p14/tioca1/ irq0 p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 p10/tioca0/a20 pa3/a19/sck2 pa2/a18/rxd2 pa1/a17/txd2 pa0/a16 pb7/a15/tiocb5 pb6/a14/tioca5 pb5/a13/tiocb4 pb4/a12/tioca4 avss p15/tiocb1/tclkc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 pe5/d5 pe6/d6 pe7/d7 pd0/d8 pd1/d9 pd2/d10 pd3/d11 pd4/d12 pd5/d13 pd6/d14 pd7/d15 pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pc6/a6 pc7/a7 pb0/a8/tioca3 pb2/a10/tiocc3 pb3/a11/tiocd3 vcc pc0/a0 vss pb1/a9/tiocb3 tfp-100b tfp-100g fp-100b (top view) figure 1-3 h8s/2237 series pin arrangement (tfp-100b, tfp-100g, fp-100b: top view)
9 p32/sck0/ irq4 p33/txd1 p34/rxd1 p35/sck1/ irq5 p36 p77/txd3 p76/rxd3 p75/sck3 p74/ mres p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci01/ cs4 pg0/ irq6 pg1/ cs3 / irq7 pg2/ cs2 pg3/ cs1 pg4/ cs0 pe0/d0 pe1/d1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 pf3/ lwr / adtrg / irq 3 pf2/ wait pf1/ back /buzz pf0/ breq / irq2 p30/txd0 p31/rxd0 pf4/ hwr pf5/ rd pf6/ as pf7/? md2 fwe extal vss xtal vcc stby nmi res osc1 osc2 md1 md0 avcc vref p40/an0 p41/an1 p42/an2 p43/an3 p44/an4 75 74 76 77 78 79 80 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p45/an5 p46/an6 p47/an7 p97/da1 avss p16/tioca2/ irq1 p15/tiocb1/tclkc p14/tioca1/ irq0 p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 p10/tioca0/a20 pa3/a19/sck2 pa2/a18/rxd2 pa1/a17/txd2 pa0/a16 pb7/a15/tiocb5 pb6/a14/tioca5 p96/da0 p17/tiocb2/tclkd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pe2/d2 pe3/d3 pe4/d4 pe5/d5 pe6/d6 pe7/d7 pd0/d8 pd1/d9 pd2/d10 pd3/d11 pd4/d12 vcc pc0/a0 vss pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pb1/a9/tiocb3 pb2/a10/tiocc3 pb3/a11/tiocd3 pb4/a12/tioca4 pb5/a13/tiocb4 pc7/a7 pb0/a8/tioca3 pd5/d13 pd6/d14 pd7/d15 pc6/a6 fp-100a (top view) figure 1-4 h8s/2237 series pin arrangement (fp-100a: top view)
10 (2) h8s/2227 series pin arrangements figures 1-5 and 1-6 show the pin arrangements of the h8s/2227 series. p30/txd0 p31/rxd0 p32/sck0/ irq4 p33/txd1 p34/rxd1 p35/sck1/ irq5 p36 p77/txd3 p76/rxd3 p75/sck3 p74/ mres p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci01/ cs4 pg0/ irq6 pg1/ cs3 / irq7 pg2/ cs2 pg3/ cs1 pg4/ cs0 pe0/d0 pe1/d1 pe2/d2 pe3/d3 pe4/d4 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 pf0/ breq / irq2 pf1/ back /buzz pf2/ wait pf3/ lwr / adtrg / irq3 pf4/ hwr pf5/ rd pf6/ as pf7/? md2 fwe extal vss xtal vcc stby nmi res osc1 osc2 md1 md0 avcc vref p40/an0 p41/an1 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p42/an2 p43/an3 p44/an4 p45/an5 p46/an6 p47/an7 p96 p97 p17/tiocb2/tclkd p16/tioca2/ irq1 p14/tioca1/ irq0 p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 p10/tioca0/a20 pa3/a19 pa2/a18 pa1/a17 pa0/a16 pb7/a15 pb6/a14 pb5/a13 pb4/a12 avss p15/tiocb1/tclkc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 pe5/d5 pe6/d6 pe7/d7 pd0/d8 pd1/d9 pd2/d10 pd3/d11 pd4/d12 pd5/d13 pd6/d14 pd7/d15 pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pc6/a6 pc7/a7 pb0/a8 pb2/a10 pb3/a11 vcc pc0/a0 vss pb1/a9 tfp-100b tfp-100g fp-100b (top view) figure 1-5 h8s/2227 series pin arrangement (tfp-100b, tfp-100g, fp-100b: top view)
11 p32/sck0/ irq4 p33/txd1 p34/rxd1 p35/sck1/ irq5 p36 p77/txd3 p76/rxd3 p75/sck3 p74/ mres p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci01/ cs4 pg0/ irq6 pg1/ cs3 / irq7 pg2/ cs2 pg3/ cs1 pg4/ cs0 pe0/d0 pe1/d1 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 pf3/ lwr / adtrg / irq 3 pf2/ wait pf1/ back /buzz pf0/ breq / irq2 p30/txd0 p31/rxd0 pf4/ hwr pf5/ rd pf6/ as pf7/? md2 fwe extal vss xtal vcc stby nmi res osc1 osc2 md1 md0 avcc vref p40/an0 p41/an1 p42/an2 p43/an3 p44/an4 75 74 76 77 78 79 80 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 p45/an5 p46/an6 p47/an7 p97 avss p16/tioca2/ irq1 p15/tiocb1/tclkc p14/tioca1/ irq0 p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 p10/tioca0/a20 pa3/a19 pa2/a18 pa1/a17 pa0/a16 pb7/a15 pb6/a14 p96 p17/tiocb2/tclkd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 pe2/d2 pe3/d3 pe4/d4 pe5/d5 pe6/d6 pe7/d7 pd0/d8 pd1/d9 pd2/d10 pd3/d11 pd4/d12 vcc pc0/a0 vss pc1/a1 pc2/a2 pc3/a3 pc4/a4 pc5/a5 pb1/a9 pb2/a10 pb3/a11 pb4/a12 pb5/a13 pc7/a7 pb0/a8 pd5/d13 pd6/d14 pd7/d15 pc6/a6 fp-100a (top view) figure 1-6 h8s/2227 series pin arrangement (fp-100a: top view)
12 1.3.2 pin functions in each operating mode table 1-2 shows the pin functions of the h8s/2237 series in each of the operating modes. table 1-2 pin functions in each operating mode pin no. pin name tfp-100b tfp-100g fp-100b fp-100a mode 4 mode 5 mode 6 mode 7 prom mode 1 4 pe5/d5 pe5/d5 pe5/d5 pe5 nc 2 5 pe6/d6 pe6/d6 pe6/d6 pe6 nc 3 6 pe7/d7 pe7/d7 pe7/d7 pe7 nc 4 7 d8 d8 d8 pd0 d0 5 8 d9 d9 d9 pd1 d1 6 9 d10 d10 d10 pd2 d2 7 10 d11 d11 d11 pd3 d3 8 11 d12 d12 d12 pd4 d4 9 12 d13 d13 d13 pd5 d5 10 13 d14 d14 d14 pd6 d6 11 14 d15 d15 d15 pd7 d7 12 15 vcc vcc vcc vcc vcc 13 16 a0 a0 pc0/a0 pc0 a0 14 17 vss vss vss vss vss 15 18 a1 a1 pc1/a1 pc1 a1 16 19 a2 a2 pc2/a2 pc2 a2 17 20 a3 a3 pc3/a3 pc3 a3 18 21 a4 a4 pc4/a4 pc4 a4 19 22 a5 a5 pc5/a5 pc5 a5 20 23 a6 a6 pc6/a6 pc6 a6 21 24 a7 a7 pc7/a7 pc7 a7 22 25 pb0/a8/tioca3 pb0/a8/tioca3 pb0/a8/tioca3 pb0/tioca3 a8 23 26 pb1/a9/tiocb3 pb1/a9/tiocb3 pb1/a9/tiocb3 pb1/tiocb3 oe 24 27 pb2/a10/tiocc3 pb2/a10/tiocc3 pb2/a10/tiocc3 pb2/tiocc3 a10 25 28 pb3/a11/tiocd3 pb3/a11/tiocd3 pb3/a11/tiocd3 pb3/tiocd3 a11 26 29 pb4/a12/tioca4 pb4/a12/tioca4 pb4/a12/tioca4 pb4/tioca4 a12 27 30 pb5/a13/tiocb4 pb5/a13/tiocb4 pb5/a13/tiocb4 pb5/tiocb4 a13 28 31 pb6/a14/tioca5 pb6/a14/tioca5 pb6/a14/tioca5 pb6/tioca5 a14
13 table 1-2 pin functions in each operating mode (cont) pin no. pin name tfp-100b tfp-100g fp-100b fp-100a mode 4 mode 5 mode 6 mode 7 prom mode 29 32 pb7/a15/tiocb5 pb7/a15/tiocb5 pb7/a15/tiocb5 pb7/tiocb5 a15 30 33 pa0/a16 pa0/a16 pa0/a16 pa0 a16 31 34 pa1/a17/txd2 pa1/a17/txd2 pa1/a17/txd2 pa1/txd2 vcc 32 35 pa2/a18/rxd2 pa2/a18/rxd2 pa2/a18/rxd2 pa2/rxd2 vcc 33 36 pa3/a19/sck2 pa3/a19/sck2 pa3/a19/sck2 pa3/sck2 nc 34 37 p10/tioca0/a20 p10/tioca0/a20 p10/tioca0/a20 p10/tioca0 nc 35 38 p11/tiocb0/a21 p11/tiocb0/a21 p11/tiocb0/a21 p11/tiocb0 nc 36 39 p12/tiocc0/ tclka/a22 p12/tiocc0/ tclka/a22 p12/tiocc0/ tclka/a22 p12/tiocc0/ tclka nc 37 40 p13/tiocd0/ tclkb/a23 p13/tiocd0/ tclkb/a23 p13/tiocd0/ tclkb/a23 p13/tiocd0/ tclkb nc 38 41 p14/tioca1/ irq0 p14/tioca1/ irq0 p14/tioca1/ irq0 p14/tioca1/ irq0 nc 39 42 p15/tiocb1/ tclkc p15/tiocb1/ tclkc p15/tiocb1/ tclkc p15/tiocb1/ tclkc nc 40 43 p16/tioca2/ irq1 p16/tioca2/ irq1 p16/tioca2/ irq1 p16/tioca2/ irq1 nc 41 44 p17/tiocb2/ tclkd p17/tiocb2/ tclkd p17/tiocb2/ tclkd p17/tiocb2/ tclkd nc 42 45 avss avss avss avss vss 43 46 p97/da1 p97/da1 p97/da1 p97/da1 nc 44 47 p96/da0 p96/da0 p96/da0 p96/da0 nc 45 48 p47/an7 p47/an7 p47/an7 p47/an7 nc 46 49 p46/an6 p46/an6 p46/an6 p46/an6 nc 47 50 p45/an5 p45/an5 p45/an5 p45/an5 nc 48 51 p44/an4 p44/an4 p44/an4 p44/an4 nc 49 52 p43/an3 p43/an3 p43/an3 p43/an3 nc 50 53 p42/an2 p42/an2 p42/an2 p42/an2 nc 51 54 p41/an1 p41/an1 p41/an1 p41/an1 nc 52 55 p40/an0 p40/an0 p40/an0 p40/an0 nc 53 56 vref vref vref vref vcc 54 57 avcc avcc avcc avcc vcc
14 table 1-2 pin functions in each operating mode (cont) pin no. pin name tfp-100b tfp-100g fp-100b fp-100a mode 4 mode 5 mode 6 mode 7 prom mode 55 58 md0 md0 md0 md0 vss 56 59 md1 md1 md1 md1 vss 57 60 osc2 osc2 osc2 osc2 nc 58 61 osc1 osc1 osc1 osc1 nc 59 62 res res res res vpp 60 63 nmi nmi nmi nmi a9 61 64 stby stby stby stby vss 62 65 vcc vcc vcc vcc vcc 63 66 xtal xtal xtal xtal nc 64 67 vss vss vss vss vss 65 68 extal extal extal extal nc 66 69 fwe fwe fwe fwe nc 67 70 md2 md2 md2 md2 vss 68 71 pf7/ pf7/ pf7/ pf7/ nc 69 72 as as as pf6 nc 70 73 rd rd rd pf5 nc 71 74 hwr hwr hwr pf4 nc 72 75 pf3/ lwr / adtrg / irq3 pf3/ lwr / adtrg / irq3 pf3/ lwr / adtrg / irq3 pf3/ adtrg / irq3 nc 73 76 pf2/ wait pf2/ wait pf2/ wait pf2 ce 74 77 pf1/ back /buzz pf1/ back /buzz pf1/ back /buzz pf1/buzz pgm 75 78 pf0/ breq / irq2 pf0/ breq / irq2 pf0/ breq / irq2 pf0/ irq2 nc 76 79 p30/txd0 p30/txd0 p30/txd0 p30/txd0 nc 77 80 p31/rxd1 p31/rxd1 p31/rxd1 p31/rxd1 nc 78 81 p32/sck0/ irq4 p32/sck0/ irq4 p32/sck0/ irq4 p32/sck0/ irq4 nc 79 82 p33/txd1 p33/txd1 p33/txd1 p33/txd1 nc 80 83 p34/rxd1 p34/rxd1 p34/rxd1 p34/rxd1 nc 81 84 p35/sck1/ irq5 p35/sck1/ irq5 p35/sck1/ irq5 p35/sck1/ irq5 nc 82 85 p36 p36 p36 p36 nc 83 86 p77/txd3 p77/txd3 p77/txd3 p77/txd3 nc 84 87 p76/rxd3 p76/rxd3 p76/rxd3 p76/rxd3 nc
15 table 1-2 pin functions in each operating mode (cont) pin no. pin name tfp-100b tfp-100g fp-100b fp-100a mode 4 mode 5 mode 6 mode 7 prom mode 85 88 p75/sck3 p75/sck3 p75/sck3 p75/sck3 nc 86 89 p74/ mres p74/ mres p74/ mres p74/ mres nc 87 90 p73/tmo1/ cs7 p73/tmo1/ cs7 p73/tmo1/ cs7 p73/tmo1 nc 88 91 p72/tmo0/ cs6 p72/tmo0/ cs6 p72/tmo0/ cs6 p72/tmo0 nc 89 92 p71/ cs5 p71/ cs5 p71/ cs5 p71 nc 90 93 p70/tmri01/ tmci01/ cs4 p70/tmri01/ tmci01/ cs4 p70/tmri01/ tmci01/ cs4 p70/tmri01/ tmci01 nc 91 94 pg0/ irq6 pg0/ irq6 pg0/ irq6 pg0/ irq6 nc 92 95 pg1/ cs3 / irq7 pg1/ cs3 / irq7 pg1/ cs3 / irq7 pg1/ irq7 nc 93 96 pg2/ cs2 pg2/ cs2 pg2/ cs2 pg2 nc 94 97 pg3/ cs1 pg3/ cs1 pg3/ cs1 pg3 nc 95 98 pg4/ cs0 pg4/ cs0 pg4/ cs0 pg4 nc 96 99 pe0/d0 pe0/d0 pe0/d0 pe0 nc 97 100 pe1/d1 pe1/d1 pe1/d1 pe1 nc 98 101 pe2/d2 pe2/d2 pe2/d2 pe2 nc 99 102 pe3/d3 pe3/d3 pe3/d3 pe3 nc 100 103 pe4/d4 pe4/d4 pe4/d4 pe4 nc
16 table 1-3 shows the pin functions of the h8s/2227 series in each of the operating modes. table 1-3 pin functions in each operating mode pin no. pin name tfp-100b tfp-100g fp-100b fp-100a mode 4 mode 5 mode 6 mode 7 prom mode 1 4 pe5/d5 pe5/d5 pe5/d5 pe5 nc 2 5 pe6/d6 pe6/d6 pe6/d6 pe6 nc 3 6 pe7/d7 pe7/d7 pe7/d7 pe7 nc 4 7 d8 d8 d8 pd0 d0 5 8 d9 d9 d9 pd1 d1 6 9 d10 d10 d10 pd2 d2 7 10 d11 d11 d11 pd3 d3 8 11 d12 d12 d12 pd4 d4 9 12 d13 d13 d13 pd5 d5 10 13 d14 d14 d14 pd6 d6 11 14 d15 d15 d15 pd7 d7 12 15 vcc vcc vcc vcc vcc 13 16 a0 a0 pc0/a0 pc0 a0 14 17 vss vss vss vss vss 15 18 a1 a1 pc1/a1 pc1 a1 16 19 a2 a2 pc2/a2 pc2 a2 17 20 a3 a3 pc3/a3 pc3 a3 18 21 a4 a4 pc4/a4 pc4 a4 19 22 a5 a5 pc5/a5 pc5 a5 20 23 a6 a6 pc6/a6 pc6 a6 21 24 a7 a7 pc7/a7 pc7 a7 22 25 pb0/a8 pb0/a8 pb0/a8 pb0 a8 23 26 pb1/a9 pb1/a9 pb1/a9 pb1 oe 24 27 pb2/a10 pb2/a10 pb2/a10 pb2 a10 25 28 pb3/a11 pb3/a11 pb3/a11 pb3 a11 26 29 pb4/a12 pb4/a12 pb4/a12 pb4 a12 27 30 pb5/a13 pb5/a13 pb5/a13 pb5 a13 28 31 pb6/a14 pb6/a14 pb6/a14 pb6 a14 29 32 pb7/a15 pb7/a15 pb7/a15 pb7 a15
17 table 1-3 pin functions in each operating mode (cont) pin no. pin name tfp-100b tfp-100g fp-100b fp-100a mode 4 mode 5 mode 6 mode 7 prom mode 30 33 pa0/a16 pa0/a16 pa0/a16 pa0 a16 31 34 pa1/a17 pa1/a17 pa1/a17 pa1 vcc 32 35 pa2/a18 pa2/a18 pa2/a18 pa2 vcc 33 36 pa3/a19 pa3/a19 pa3/a19 pa3 nc 34 37 p10/tioca0/a20 p10/tioca0/a20 p10/tioca0/a20 p10/tioca0 nc 35 38 p11/tiocb0/a21 p11/tiocb0/a21 p11/tiocb0/a21 p11/tiocb0 nc 36 39 p12/tiocc0/ tclka/a22 p12/tiocc0/ tclka/a22 p12/tiocc0/ tclka/a22 p12/tiocc0/ tclka nc 37 40 p13/tiocd0/ tclkb/a23 p13/tiocd0/ tclkb/a23 p13/tiocd0/ tclkb/a23 p13/tiocd0/ tclkb nc 38 41 p14/tioca1/ irq0 p14/tioca1/ irq0 p14/tioca1/ irq0 p14/tioca1/ irq0 nc 39 42 p15/tiocb1/ tclkc p15/tiocb1/ tclkc p15/tiocb1/ tclkc p15/tiocb1/ tclkc nc 40 43 p16/tioca2/ irq1 p16/tioca2/ irq1 p16/tioca2/ irq1 p16/tioca2/ irq1 nc 41 44 p17/tiocb2/ tclkd p17/tiocb2/ tclkd p17/tiocb2/ tclkd p17/tiocb2/ tclkd nc 42 45 avss avss avss avss vss 43 46 p97 p97 p97 p97 nc 44 47 p96 p96 p96 p96 nc 45 48 p47/an7 p47/an7 p47/an7 p47/an7 nc 46 49 p46/an6 p46/an6 p46/an6 p46/an6 nc 47 50 p45/an5 p45/an5 p45/an5 p45/an5 nc 48 51 p44/an4 p44/an4 p44/an4 p44/an4 nc 49 52 p43/an3 p43/an3 p43/an3 p43/an3 nc 50 53 p42/an2 p42/an2 p42/an2 p42/an2 nc 51 54 p41/an1 p41/an1 p41/an1 p41/an1 nc 52 55 p40/an0 p40/an0 p40/an0 p40/an0 nc 53 56 vref vref vref vref vcc 54 57 avcc avcc avcc avcc vcc 55 58 md0 md0 md0 md0 vss
18 table 1-3 pin functions in each operating mode (cont) pin no. pin name tfp-100b tfp-100g fp-100b fp-100a mode 4 mode 5 mode 6 mode 7 prom mode 56 59 md1 md1 md1 md1 vss 57 60 osc2 osc2 osc2 osc2 nc 58 61 osc1 osc1 osc1 osc1 nc 59 62 res res res res vpp 60 63 nmi nmi nmi nmi a9 61 64 stby stby stby stby vss 62 65 vcc vcc vcc vcc vcc 63 66 xtal xtal xtal xtal nc 64 67 vss vss vss vss vss 65 68 extal extal extal extal nc 66 69 fwe fwe fwe fwe nc 67 70 md2 md2 md2 md2 vss 68 71 pf7/ pf7/ pf7/ pf7/ nc 69 72 as as as pf6 nc 70 73 rd rd rd pf5 nc 71 74 hwr hwr hwr pf4 nc 72 75 pf3/ lwr / adtrg / irq3 pf3/ lwr / adtrg / irq3 pf3/ lwr / adtrg / irq3 pf3/ adtrg / irq3 nc 73 76 pf2/ wait pf2/ wait pf2/ wait pf2 ce 74 77 pf1/ back /buzz pf1/ back /buzz pf1/ back /buzz pf1/buzz pgm 75 78 pf0/ breq / irq2 pf0/ breq / irq2 pf0/ breq / irq2 pf0/ irq2 nc 76 79 p30/txd0 p30/txd0 p30/txd0 p30/txd0 nc 77 80 p31/rxd1 p31/rxd1 p31/rxd1 p31/rxd1 nc 78 81 p32/sck0/ irq4 p32/sck0/ irq4 p32/sck0/ irq4 p32/sck0/ irq4 nc 79 82 p33/txd1 p33/txd1 p33/txd1 p33/txd1 nc 80 83 p34/rxd1 p34/rxd1 p34/rxd1 p34/rxd1 nc 81 84 p35/sck1/ irq5 p35/sck1/ irq5 p35/sck1/ irq5 p35/sck1/ irq5 nc 82 85 p36 p36 p36 p36 nc 83 86 p77/txd3 p77/txd3 p77/txd3 p77/txd3 nc 84 87 p76/rxd3 p76/rxd3 p76/rxd3 p76/rxd3 nc 85 88 p75/sck3 p75/sck3 p75/sck3 p75/sck3 nc
19 table 1-3 pin functions in each operating mode (cont) pin no. pin name tfp-100b tfp-100g fp-100b fp-100a mode 4 mode 5 mode 6 mode 7 prom mode 86 89 p74/ mres p74/ mres p74/ mres p74/ mres nc 87 90 p73/tmo1/ cs7 p73/tmo1/ cs7 p73/tmo1/ cs7 p73/tmo1 nc 88 91 p72/tmo0/ cs6 p72/tmo0/ cs6 p72/tmo0/ cs6 p72/tmo0 nc 89 92 p71/ cs5 p71/ cs5 p71/ cs5 p71 nc 90 93 p70/tmri01/ tmci01/ cs4 p70/tmri01/ tmci01/ cs4 p70/tmri01/ tmci01/ cs4 p70/tmri01/ tmci01 nc 91 94 pg0/ irq6 pg0/ irq6 pg0/ irq6 pg0/ irq6 nc 92 95 pg1/ cs3 / irq7 pg1/ cs3 / irq7 pg1/ cs3 / irq7 pg1/ irq7 nc 93 96 pg2/ cs2 pg2/ cs2 pg2/ cs2 pg2 nc 94 97 pg3/ cs1 pg3/ cs1 pg3/ cs1 pg3 nc 95 98 pg4/ cs0 pg4/ cs0 pg4/ cs0 pg4 nc 96 99 pe0/d0 pe0/d0 pe0/d0 pe0 nc 97 100 pe1/d1 pe1/d1 pe1/d1 pe1 nc 98 101 pe2/d2 pe2/d2 pe2/d2 pe2 nc 99 102 pe3/d3 pe3/d3 pe3/d3 pe3 nc 100 103 pe4/d4 pe4/d4 pe4/d4 pe4 nc
20 1.3.3 pin functions table 1-4 outlines the pin functions of the h8s/2237 series and h8s/2227 series. table 1-4 pin functions type symbol i/o name and function power vcc input power supply: for connection to the power supply. all v cc pins should be connected to the system power supply. vss input ground: for connection to ground (0 v). all v ss pins should be connected to the system power supply (0 v). clock xtal input crystal: connects to a crystal oscillator. see section 19, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input. extal input external clock: connects to a crystal oscillator. the extal pin can also input an external clock. see section 19, clock pulse generator, for typical connection diagrams for a crystal oscillator and external clock input. osc1 input subclock: connects to a 32.768 khz crystal oscillator. see section 19, clock pulse generator, for typical connection diagrams for a crystal oscillator. osc2 input subclock: connects to a 32.768 khz crystal oscillator. see section 19, clock pulse generator, for typical connection diagrams for a crystal oscillator. output system clock: supplies the system clock to an external device.
21 table 1-4 pin functions (cont) type symbol i/o name and function operating mode control md2 to md0 input mode pins: these pins set the operating mode. the relation between the settings of pins md2 to md0 and the operating mode is shown below. these pins should not be changed while the h8s/2237 series and h8s/2227 series is operating. md2 md1 md0 operating mode 000 1 10 1 1 0 0 mode 4 1 mode 5 1 0 mode 6 1 mode 7 system control res input reset input: when this pin is driven low, the chip enters the power-on reset state. mres input manual reset: when this pin is driven low, the chip enters the manual reset state. stby input standby: when this pin is driven low, a transition is made to hardware standby mode. breq input bus request: used by an external bus master to issue a bus request to the h8s/2237 series and h8s/2227 series. back output bus request acknowledge: indicates that the bus has been released to an external bus master. fwe input flash write enable: pin for use by flash memory (in planning stage) interrupts nmi input nonmaskable interrupt: requests a nonmaskable interrupt. when this pin is not used, it should be fixed high. irq7 to irq0 input interrupt request 7 to 0: these pins request a maskable interrupt. address bus a23 to a0 output address bus: these pins output an address. data bus d15 to d0 i/o data bus: these pins constitute a bidirectional data bus.
22 table 1-4 pin functions (cont) type symbol i/o name and function bus control cs7 to cs0 output chip select: signals for selecting areas 7 to 0. as output address strobe: when this pin is low, it indicates that address output on the address bus is enabled. rd output read: when this pin is low, it indicates that the external address space can be read. hwr output high write: a strobe signal that writes to external space and indicates that the upper half (d15 to d8) of the data bus is enabled. lwr output low write: a strobe signal that writes to external space and indicates that the lower half (d7 to d0) of the data bus is enabled. wait input wait: requests insertion of a wait state in the bus cycle when accessing external 3-state address space. 16-bit timer- pulse unit (tpu) tclkd to tclka input clock input d to a: these pins input an external clock. tioca0, tiocb0, tiocc0, tiocd0 i/o input capture/ output compare match a0 to d0: the tgr0a to tgr0d input capture input or output compare output, or pwm output pins. tioca1, tiocb1 i/o input capture/ output compare match a1 and b1: the tgr1a and tgr1b input capture input or output compare output, or pwm output pins. tioca2, tiocb2 i/o input capture/ output compare match a2 and b2: the tgr2a and tgr2b input capture input or output compare output, or pwm output pins. tioca3, tiocb3, tiocc3, tiocd3 i/o input capture/ output compare match a3 to d3: the tgr3a to tgr3d input capture input or output compare output, or pwm output pins (h8s/2237 series only). tioca4, tiocb4 i/o input capture/ output compare match a4 and b4: the tgr4a and tgr4b input capture input or output compare output, or pwm output pins (h8s/2237 series only). tioca5, tiocb5 i/o input capture/ output compare match a5 and b5: the tgr5a and tgr5b input capture input or output compare output, or pwm output pins (h8s/2237 series only).
23 table 1-4 pin functions (cont) type symbol i/o name and function 8-bit timer tmo0, tmo1 output compare match output: the compare match output pins. tmci01 input counter external clock input: input pins for the external clock input to the counter. tmri01 input counter external reset input: the counter reset input pins. watchdog timer (wdt) buzz output buzz output: outputs pulses scaled by the watchdog timer. serial communication interface (sci) smart card txd3, txd2, txd1, txd0 output transmit data: data output pins. (txd2 is provided only in the h8s/2237 series) interface rxd3, rxd2, rxd1, rxd0 input receive data: data input pins. (rxd2 is provided only in the h8s/2237 series) sck3, sck2, sck1 sck0 i/o serial clock: clock i/o pins. (sck2 is provided only in the h8s/2237 series) a/d converter an7 to an0 input analog 7 to 0: analog input pins. adtrg input a/d conversion external trigger input: pin for input of an external trigger to start a/d conversion. d/a converter da1, da0 output analog output: d/a converter analog output pins. (h8s/2237 series only) a/d converter and d/a converters av cc input this is the power supply pin for the a/d converter and d/a converter. when the a/d converter and d/a converter are not used, this pin should be connected to the system power supply (+3 v). av ss input this is the ground pin for the a/d converter and d/a converter. this pin should be connected to the system power supply (0 v). v ref input this is the reference voltage input pin for the a/d converter and d/a converter. when the a/d converter and d/a converter are not used, this pin should be connected to the system power supply (+3 v).
24 table 1-4 pin functions (cont) type symbol i/o name and function i/o ports p17 to p10 i/o port 1: an 8-bit i/o port. input or output can be designated for each bit by means of the port 1 data direction register (p1ddr). p36 to p30 i/o port 3: a 7-bit i/o port. input or output can be designated for each bit by means of the port 3 data direction register (p3ddr). p47 to p40 input port 4: an 8-bit input port. p77 to p70 i/o port 7: an 8-bit i/o port. input or output can be designated for each bit by means of the port 7 data direction register (p7ddr). p97, p96 input port 9: a 2-bit input port. pa3 to pa0 i/o port a: a 4-bit i/o port. input or output can be designated for each bit by means of the port a data direction register (paddr). pb7 to pb0 i/o port b: an 8-bit i/o port. input or output can be designated for each bit by means of the port b data direction register (pbddr). pc7 to pc0 i/o port c: an 8-bit i/o port. input or output can be designated for each bit by means of the port c data direction register (pcddr). pd7 to pd0 i/o port d: an 8-bit i/o port. input or output can be designated for each bit by means of the port d data direction register (pdddr). pe7 to pe0 i/o port e: an 8-bit i/o port. input or output can be designated for each bit by means of the port e data direction register (peddr). pf7 to pf0 i/o port f: an 8-bit i/o port. input or output can be designated for each bit by means of the port f data direction register (pfddr). pg4 to pg0 i/o port g: a 5-bit i/o port. input or output can be designated for each bit by means of the port g data direction register (pgddr).
25 section 2 cpu 2.1 overview the h8s/2000 cpu is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the h8/300 and h8/300h cpus. the h8s/2000 cpu has sixteen 16-bit general registers, can address a 16-mbyte (architecturally 4-gbyte) linear address space, and is ideal for realtime control. 2.1.1 features the h8s/2000 cpu has the following features. upward-compatible with h8/300 and h8/300h cpus ? can execute h8/300 and h8/300h object programs general-register architecture ? sixteen 16-bit general registers (also usable as sixteen 8-bit registers or eight 32-bit registers) sixty-five basic instructions ? 8/16/32-bit arithmetic and logic instructions ? multiply and divide instructions ? powerful bit-manipulation instructions eight addressing modes ? register direct [rn] ? register indirect [@ern] ? register indirect with displacement [@(d:16,ern) or @(d:32,ern)] ? register indirect with post-increment or pre-decrement [@ern+ or @eern] ? absolute address [@aa:8, @aa:16, @aa:24, or @aa:32] ? immediate [#xx:8, #xx:16, or #xx:32] ? program-counter relative [@(d:8,pc) or @(d:16,pc)] ? memory indirect [@@aa:8] 16-mbyte address space ? program: 16 mbytes ? data: 16 mbytes (4 gbytes architecturally)
26 high-speed operation ? all frequently-used instructions execute in one or two states ? maximum clock rate : 10 mhz (ztat version) 13 mhz (mask rom version) ? 8/16/32-bit register-register add/subtract : 100 ns (at 10 mhz operation) ? 8 8-bit register-register multiply : 1200 ns (at 10 mhz operation) ? 16 ? 8-bit register-register divide : 1200 ns (at 10 mhz operation) ? 16 16-bit register-register multiply : 2000 ns (at 10 mhz operation) ? 32 ? 16-bit register-register divide : 2000 ns (at 10 mhz operation) two cpu operating modes ? normal mode* ? advanced mode note: * not available in the h8s/2237 series and h8s/2227 series. power-down state ? transition to power-down state by sleep instruction ? cpu clock speed selection 2.1.2 differences between h8s/2600 cpu and h8s/2000 cpu the differences between the h8s/2600 cpu and the h8s/2000 cpu are as shown below. register configuration the mac register is supported only by the h8s/2600 cpu. basic instructions the four instructions mac, clrmac, ldmac, and stmac are supported only by the h8s/2600 cpu. number of execution states the number of exection states of the mulxu and mulxs instructions. internal operation instruction mnemonic h8s/2600 h8s/2000 mulxu mulxu.b rs, rd 3 12 mulxu.w rs, erd 4 20 mulxs mulxs.b rs, rd 4 13 mulxs.w rs, erd 5 21
27 there are also differences in the address space, ccr and exr register functions, power-down state, etc., depending on the product. 2.1.3 differences from h8/300 cpu in comparison to the h8/300 cpu, the h8s/2000 cpu has the following enhancements. more general registers and control registers ? eight 16-bit expanded registers, plus one 8-bit and two 32-bit control registers, have been added. expanded address space ? normal mode* supports the same 64-kbyte address space as the h8/300 cpu. ? advanced mode supports a maximum 16-mbyte address space. note: * not available in the h8s/2237 series and h8s/2227 series. enhanced addressing ? the addressing modes have been enhanced to make effective use of the 16-mbyte address space. enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? signed multiply and divide instructions have been added. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added. higher speed ? basic instructions execute twice as fast. 2.1.4 differences from h8/300h cpu in comparison to the h8/300h cpu, the h8s/2000 cpu has the following enhancements. additional control register ? one 8-bit and two 32-bit control registers have been added. enhanced instructions ? addressing modes of bit-manipulation instructions have been enhanced. ? two-bit shift instructions have been added. ? instructions for saving and restoring multiple registers have been added. ? a test and set instruction has been added.
28 higher speed ? basic instructions execute twice as fast. 2.2 cpu operating modes the h8s/2000 cpu has two operating modes: normal* and advanced. normal mode supports a maximum 64-kbyte address space. advanced mode supports a maximum 16-mbyte total address space (architecturally a maximum 16-mbyte program area and a maximum of 4 gbytes for program and data areas combined). the mode is selected by the mode pins of the microcontroller. note: * not available in the h8s/2237 series and h8s/2227 series. cpu operating modes normal mode * note: * not available in the h8s/2237 series and h8s/2227 series. advanced mode maximum 64 kbytes, program and data areas combined maximum 16-mbytes for program and data areas combined figure 2-1 cpu operating modes (1) normal mode (not available in the h8s/2237 series and h8s/2227 series) the exception vector table and stack have the same structure as in the h8/300 cpu. address space: a maximum address space of 64 kbytes can be accessed. extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers. when en is used as a 16-bit register it can contain any value, even when the corresponding general register (rn) is used as an address register. if the general register is referenced in the register indirect addressing mode with pre-decrement (@ern) or post-increment (@rn+) and a carry or borrow occurs, however, the value in the corresponding extended register (en) will be affected. instruction set: all instructions and addressing modes can be used. only the lower 16 bits of effective addresses (ea) are valid.
29 exception vector table and memory indirect branch addresses: in normal mode the top area starting at h'0000 is allocated to the exception vector table. one branch address is stored per 16 bits. the configuration of the exception vector table in normal mode is shown in figure 2-2. for details of the exception vector table, see section 4, exception handling. h'0000 h'0001 h'0002 h'0003 h'0004 h'0005 h'0006 h'0007 h'0008 h'0009 h'000a h'000b power-on reset exception vector manual reset exception vector exception vector 1 exception vector 2 exception vector table (reserved for system use) figure 2-2 exception vector table (normal mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in normal mode the operand is a 16-bit word operand, providing a 16- bit branch address. branch addresses can be stored in the top area from h'0000 to h'00ff. note that this area is also used for the exception vector table.
30 stack structure: when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2-3. when exr is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. (a) subroutine branch (b) exception handling pc (16 bits) exr * 1 reserved * 1, * 3 ccr ccr * 3 pc (16 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored when returning. (sp ) * 2 figure 2-3 stack structure in normal mode (2) advanced mode address space: linear access is provided to a 16-mbyte maximum address space (architecturally a maximum 16-mbyte program area and a maximum 4-gbyte data area, with a maximum of 4 gbytes for program and data areas combined). extended registers (en): the extended registers (e0 to e7) can be used as 16-bit registers, or as the upper 16-bit segments of 32-bit registers or address registers. instruction set: all instructions and addressing modes can be used.
31 exception vector table and memory indirect branch addresses: in advanced mode the top area starting at h'00000000 is allocated to the exception vector table in units of 32 bits. in each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2-4). for details of the exception vector table, see section 4, exception handling. h'00000000 h'00000003 h'00000004 h'0000000b h'0000000c exception vector table reserved power-on reset exception vector (reserved for system use) reserved exception vector 1 reserved manual reset exception vector h'00000010 h'00000008 h'00000007 figure 2-4 exception vector table (advanced mode) the memory indirect addressing mode (@@aa:8) employed in the jmp and jsr instructions uses an 8-bit absolute address included in the instruction code to specify a memory operand that contains a branch address. in advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch address. the upper 8 bits of these 32 bits are a reserved area that is regarded as h'00. branch addresses can be stored in the area from h'00000000 to h'000000ff. note that the first part of this range is also the exception vector table.
32 stack structure: in advanced mode, when the program counter (pc) is pushed onto the stack in a subroutine call, and the pc, condition-code register (ccr), and extended control register (exr) are pushed onto the stack in exception handling, they are stored as shown in figure 2-5. when exr is invalid, it is not pushed onto the stack. for details, see section 4, exception handling. (a) subroutine branch (b) exception handling pc (24 bits) exr * 1 reserved * 1, * 3 ccr pc (24 bits) sp sp notes: 1. 2. 3. when exr is not used it is not stored on the stack. sp when exr is not used. ignored when returning. (sp ) * 2 reserved figure 2-5 stack structure in advanced mode
33 2.3 address space figure 2-6 shows a memory map of the h8s/2000 cpu. the h8s/2000 cpu provides linear access to a maximum 64-kbyte address space in normal mode, and a maximum 16-mbyte (architecturally 4-gbyte) address space in advanced mode. (b) advanced mode h'0000 h'ffff h'00000000 h'ffffffff h'00ffffff (a) normal mode * data area program area cannot be used by the h8s/2237 series, h8/2227 series note: * not available in the h8s/2237 series and h8s/2227 series. figure 2-6 memory map
34 2.4 register configuration 2.4.1 overview the cpu has the internal registers shown in figure 2-7. there are two types of registers: general registers and control registers. t i2 i1 i0 exr 76543210 pc 23 0 15 07 07 0 e0 e1 e2 e3 e4 e5 e6 e7 r0h r1h r2h r3h r4h r5h r6h r7h r0l r1l r2l r3l r4l r5l r6l r7l general registers (rn) and extended registers (en) control registers (cr) legend stack pointer program counter extended control register trace bit interrupt mask bits condition-code register interrupt mask bit user bit or interrupt mask bit * sp: pc: exr: t: i2 to i0: ccr: i: ui: note: * in the h8s/2237 series and h8s/2227 series, this bit cannot be used as an interrupt mask. er0 er1 er2 er3 er4 er5 er6 er7 (sp) i ui hunzvc ccr 76543210 half-carry flag user bit negative flag zero flag overflow flag carry flag h: u: n: z: v: c: figure 2-7 cpu registers
35 2.4.2 general registers the cpu has eight 32-bit general registers. these general registers are all functionally alike and can be used as both address registers and data registers. when a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. when the general registers are used as 32-bit registers or address registers, they are designated by the letters er (er0 to er7). the er registers divide into 16-bit general registers designated by the letters e (e0 to e7) and r (r0 to r7). these registers are functionally equivalent, providing a maximum sixteen 16-bit registers. the e registers (e0 to e7) are also referred to as extended registers. the r registers divide into 8-bit general registers designated by the letters rh (r0h to r7h) and rl (r0l to r7l). these registers are functionally equivalent, providing a maximum sixteen 8-bit registers. figure 2-8 illustrates the usage of the general registers. the usage of each register can be selected independently. ? address registers ? 32-bit registers ? 16-bit registers ? 8-bit registers er registers (er0 to er7) e registers (extended registers) (e0 to e7) r registers (r0 to r7) rh registers (r0h to r7h) rl registers (r0l to r7l) figure 2-8 usage of general registers
36 general register er7 has the function of stack pointer (sp) in addition to its general-register function, and is used implicitly in exception handling and subroutine calls. figure 2-9 shows the stack. free area stack area sp (er7) figure 2-9 stack 2.4.3 control registers the control registers are the 24-bit program counter (pc), 8-bit extended control register (exr), and 8-bit condition-code register (ccr). (1) program counter (pc): this 24-bit counter indicates the address of the next instruction the cpu will execute. the length of all cpu instructions is 2 bytes (one word), so the least significant pc bit is ignored. (when an instruction is fetched, the least significant pc bit is regarded as 0.) (2) extended control register (exr): this 8-bit register contains the trace bit (t) and interrupt mask bit. bit 7?race bit (t): selects trace mode. when this bit is cleared to 0, instructions are executed in sequence. when this bit is set to 1, a trace exception is generated each time an instruction is executed. bits 6 to 3?eserved: these bits are reserved. they are always read as 1.
37 bits 2 to 0?nterrupt mask bits (i2 to i0): these bits designate the interrupt mask level (0 to 7). for details, refer to section 5, interrupt controller. operations can be performed on the exr bits by the ldc, stc, andc, orc, and xorc instructions. all interrupts, including nmi, are disabled for three states after one of these instructions is executed, except for stc. (3) condition-code register (ccr): this 8-bit register contains internal cpu status information, including an interrupt mask bit (i) and half-carry (h), negative (n), zero (z), overflow (v), and carry (c) flags. bit 7?nterrupt mask bit (i): masks interrupts other than nmi when set to 1. (nmi is accepted regardless of the i bit setting.) the i bit is set to 1 by hardware at the start of an exception- handling sequence. for details, refer to section 5, interrupt controller. bit 6?ser bit or interrupt mask bit (ui): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. with the h8s/2237 series and h8s/2227 series, this bit cannot be used as an interrupt mask bit. bit 5?alf-carry flag (h): when the add.b, addx.b, sub.b, subx.b, cmp.b, or neg.b instruction is executed, this flag is set to 1 if there is a carry or borrow at bit 3, and cleared to 0 otherwise. when the add.w, sub.w, cmp.w, or neg.w instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 11, and cleared to 0 otherwise. when the add.l, sub.l, cmp.l, or neg.l instruction is executed, the h flag is set to 1 if there is a carry or borrow at bit 27, and cleared to 0 otherwise. bit 4?ser bit (u): can be written and read by software using the ldc, stc, andc, orc, and xorc instructions. bit 3?egative flag (n): stores the value of the most significant bit (sign bit) of data. bit 2?ero flag (z): set to 1 to indicate zero data, and cleared to 0 to indicate non-zero data. bit 1?verflow flag (v): set to 1 when an arithmetic overflow occurs, and cleared to 0 at other times. bit 0?arry flag (c): set to 1 when a carry occurs, and cleared to 0 otherwise. used by: add instructions, to indicate a carry subtract instructions, to indicate a borrow shift and rotate instructions, to indicate a carry the carry flag is also used as a bit accumulator by bit manipulation instructions.
38 some instructions leave some or all of the flag bits unchanged. for the action of each instruction on the flag bits, refer to appendix a.1, list of instructions. operations can be performed on the ccr bits by the ldc, stc, andc, orc, and xorc instructions. the n, z, v, and c flags are used as branching conditions for conditional branch (bcc) instructions. 2.4.4 initial register values reset exception handling loads the cpu? program counter (pc) from the vector table, clears the trace bit in exr to 0, and sets the interrupt mask bits in ccr and exr to 1. the other ccr bits and the general registers are not initialized. in particular, the stack pointer (er7) is not initialized. the stack pointer should therefore be initialized by an mov.l instruction executed immediately after a reset.
39 2.5 data formats the cpu can process 1-bit, 4-bit (bcd), 8-bit (byte), 16-bit (word), and 32-bit (longword) data. bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2, ? 7) of byte operand data. the daa and das decimal-adjust instructions treat byte data as two digits of 4-bit bcd data. 2.5.1 general register data formats figure 2-10 shows the data formats in general registers. 76543210 don? care 70 don? care 76543210 43 70 70 don? care upper lower lsb msb lsb data type register number data format 1-bit data 1-bit data 4-bit bcd data 4-bit bcd data byte data byte data rnh rnl rnh rnl rnh rnl msb don? care upper lower 43 70 don? care 70 don? care 70 figure 2-10 general register data formats
40 0 msb lsb 15 word data word data rn en 0 lsb 15 16 msb 31 en rn general register er general register e general register r general register rh general register rl most significant bit least significant bit legend ern: en: rn: rnh: rnl: msb: lsb: 0 msb lsb 15 longword data ern data type register number data format figure 2-10 general register data formats (cont)
41 2.5.2 memory data formats figure 2-11 shows the data formats in memory. the cpu can access word data and longword data in memory, but word or longword data must begin at an even address. if an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. this also applies to instruction fetches. 76543210 70 msb lsb msb lsb msb lsb data type data format 1-bit data byte data word data longword data address address l address l address 2m address 2m + 1 address 2n address 2n + 1 address 2n + 2 address 2n + 3 figure 2-11 memory data formats when er7 is used as an address register to access the stack, the operand size should be word size or longword size.
42 2.6 instruction set 2.6.1 overview the h8s/2000 cpu has 65 types of instructions. the instructions are classified by function in table 2-1. table 2-1 instruction classification function instructions size types data transfer mov bwl 5 pop * 1 , push * 1 wl ldm, stm l movfpe, movtpe * 3 b arithmetic add, sub, cmp, neg bwl 19 operations addx, subx, daa, das b inc, dec bwl adds, subs l mulxu, divxu, mulxs, divxs bw extu, exts wl tas b logic operations and, or, xor, not bwl 4 shift shal, shar, shll, shlr, rotl, rotr, rotxl, rotxr bwl 8 bit manipulation bset, bclr, bnot, btst, bld, bild, bst, bist, band, biand, bor, bior, bxor, bixor b14 branch bcc * 2 , jmp, bsr, jsr, rts 5 system control trapa, rte, sleep, ldc, stc, andc, orc, xorc, nop 9 block data transfer eepmov 1 total: 65 notes: b-byte size; w-word size; l-longword size. 1. pop.w rn and push.w rn are identical to mov.w @sp+, rn and mov.w rn, @- sp. pop.l ern and push.l ern are identical to mov.l @sp+, ern and mov.l ern, @-sp. 2. bcc is the general name for conditional branch instructions. 3. cannot be used in the h8s/2237 series and h8s/2227 series.
43 2.6.2 instructions and addressing modes table 2-2 indicates the combinations of instructions and addressing modes that the h8s/2600 cpu can use. table 2-2 combinations of instructions and addressing modes addressing modes function data transfer arithmetic operations instruction mov bwl bwl bwl bwl bwl bwl b bwl bwl pop, push ?l ldm, stm ? add, cmp bwl bwl sub wlbwl addx, subx b b adds, subs l inc, dec bwl daa, das b neg ?wl extu, exts wl tas b note: * cannot be used in the h8s/2237 series and h8s/2227 series. movfpe, * b movtpe * mulxu, bw divxu mulxs, bw divxs #xx rn @ern @(d:16,ern) @(d:32,ern) @?rn/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8
44 table 2-2 combinations of instructions and addressing modes (cont) addressing modes function logic operations system control block data transfer shift bit manipulation branch instruction and, or, bwl bwl xor andc, b orc, xorc bcc, bsr jmp, jsr rts trapa rte sleep ldc b b wwww w w stc b wwww w w not ?wl ?wl ? b bb b nop ?w legend b: byte w: word l: longword #xx rn @ern @(d:16,ern) @(d:32,ern) @?rn/@ern+ @aa:8 @aa:16 @aa:24 @aa:32 @(d:8,pc) @(d:16,pc) @@aa:8
45 2.6.3 table of instructions classified by function table 2-3 summarizes the instructions in each functional category. the notation used in table 2-3 is defined below. operation notation rd general register (destination) * rs general register (source) * rn general register * ern general register (32-bit register) (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + addition subtraction multiplication ? division logical and logical or ? logical exclusive or ? move not (logical complement) :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length note: * general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7).
46 table 2-3 instructions classified by function type instruction size * function data transfer mov b/w/l (eas) ? rd, rs ? (ead) moves data between two general registers or between a general register and memory, or moves immediate data to a general register. movfpe b cannot be used in the h8s/2237 series and h8s/2227 series. movtpe b cannot be used in the h8s/2237 series and h8s/2227 series. pop w/l @sp+ ? rn pops a register from the stack. pop.w rn is identical to mov.w @sp+, rn. pop.l ern is identical to mov.l @sp+, ern. push w/l rn ? @?p pushes a register onto the stack. push.w rn is identical to mov.w rn, @?p. push.l ern is identical to mov.l ern, @?p. ldm l @sp+ ? rn (register list) pops two or more general registers from the stack. stm l rn (register list) ? @?p pushes two or more general registers onto the stack. note: * size refers to the operand size. b: byte w: word l: longword
47 table 2-3 instructions classified by function (cont) type instruction size * function arithmetic operations add sub b/w/l rd rs ? rd, rd #imm ? rd performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (immediate byte data cannot be subtracted from byte data in a general register. use the subx or add instruction.) addx subx b rd rs c ? rd, rd #imm c ? rd performs addition or subtraction with carry or borrow on byte data in two general registers, or on immediate data and data in a general register. inc dec b/w/l rd 1 ? rd, rd 2 ? rd increments or decrements a general register by 1 or 2. (byte operands can be incremented or decremented by 1 only.) adds subs l rd 1 ? rd, rd 2 ? rd, rd 4 ? rd adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register. daa das b rd decimal adjust ? rd decimal-adjusts an addition or subtraction result in a general register by referring to the ccr to produce 4-bit bcd data. mulxu b/w rd rs ? rd performs unsigned multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. mulxs b/w rd rs ? rd performs signed multiplication on data in two general registers: either 8 bits 8 bits ? 16 bits or 16 bits 16 bits ? 32 bits. divxu b/w rd ? rs ? rd performs unsigned division on data in two general registers: either 16 bits ? 8 bits ? 8-bit quotient and 8-bit remainder or 32 bits ? 16 bits ? 16-bit quotient and 16- bit remainder. note: * size refers to the operand size. b: byte w: word l: longword
48 table 2-3 instructions classified by function (cont) type instruction size * function arithmetic operations divxs b/w rd ? rs ? rd performs signed division on data in two general registers: either 16 bits ? 8 bits ? 8-bit quotient and 8-bit remainder or 32 bits ? 16 bits ? 16-bit quotient and 16- bit remainder. cmp b/w/l rd ?rs, rd ?#imm compares data in a general register with data in another general register or with immediate data, and sets ccr bits according to the result. neg b/w/l 0 ?rd ? rd takes the two? complement (arithmetic complement) of data in a general register. extu w/l rd (zero extension) ? rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by padding with zeros on the left. exts w/l rd (sign extension) ? rd extends the lower 8 bits of a 16-bit register to word size, or the lower 16 bits of a 32-bit register to longword size, by extending the sign bit. tas b @erd ?0, 1 ? ( of @erd) tests memory contents, and sets the most significant bit (bit 7) to 1. note: * size refers to the operand size. b: byte w: word l: longword
49 table 2-3 instructions classified by function (cont) type instruction size * function logic operations and b/w/l rd rs ? rd, rd #imm ? rd performs a logical and operation on a general register and another general register or immediate data. or b/w/l rd rs ? rd, rd #imm ? rd performs a logical or operation on a general register and another general register or immediate data. xor b/w/l rd ? rs ? rd, rd ? #imm ? rd performs a logical exclusive or operation on a general register and another general register or immediate data. not b/w/l ?(rd) ? (rd) takes the one? complement of general register contents. shift operations shal shar b/w/l rd (shift) ? rd performs an arithmetic shift on general register contents. 1-bit or 2-bit shift is possible. shll shlr b/w/l rd (shift) ? rd performs a logical shift on general register contents. 1-bit or 2-bit shift is possible. rotl rotr b/w/l rd (rotate) ? rd rotates general register contents. 1-bit or 2-bit rotation is possible. rotxl rotxr b/w/l rd (rotate) ? rd rotates general register contents through the carry flag. 1-bit or 2-bit rotation is possible. note: * size refers to the operand size. b: byte w: word l: longword
50 table 2-3 instructions classified by function (cont) type instruction size * function bit- manipulation instructions bset b 1 ? ( of ) sets a specified bit in a general register or memory operand to 1. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bclr b 0 ? ( of ) clears a specified bit in a general register or memory operand to 0. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. bnot b ( of ) ? ( of ) inverts a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. btst b ( of ) ? z tests a specified bit in a general register or memory operand and sets or clears the z flag accordingly. the bit number is specified by 3-bit immediate data or the lower three bits of a general register. band biand b b c ( of ) ? c ands the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ?( of ) ? c ands the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bor bior b b c ( of ) ? c ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ?( of ) ? c ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. note: * size refers to the operand size. b: byte
51 table 2-3 instructions classified by function (cont) type instruction size * function bit- manipulation instructions bxor bixor b b c ? ( of ) ? c exclusive-ors the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. c ? ?( of ) ? c exclusive-ors the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. the bit number is specified by 3-bit immediate data. bld bild b b ( of ) ? c transfers a specified bit in a general register or memory operand to the carry flag. ?( of ) ? c transfers the inverse of a specified bit in a general register or memory operand to the carry flag. the bit number is specified by 3-bit immediate data. bst bist b b c ? ( of ) transfers the carry flag value to a specified bit in a general register or memory operand. ?c ? ( of ) transfers the inverse of the carry flag value to a specified bit in a general register or memory operand. the bit number is specified by 3-bit immediate data. note: * size refers to the operand size. b: byte
52 table 2-3 instructions classified by function (cont) type instruction size * function branch instructions bcc branches to a specified address if a specified condition is true. the branching conditions are listed below. mnemonic description condition bra(bt) always (true) always brn(bf) never (false) never bhi high c z = 0 bls low or same c z = 1 bcc(bhs) carry clear c = 0 (high or same) bcs(blo) carry set (low) c = 1 bne not equal z = 0 beq equal z = 1 bvc overflow clear v = 0 bvs overflow set v = 1 bpl plus n = 0 bmi minus n = 1 bge greater or equal n ? v = 0 blt less than n ? v = 1 bgt greater than z (n ? v) = 0 ble less or equal z (n ? v) = 1 jmp branches unconditionally to a specified address. bsr branches to a subroutine at a specified address. jsr branches to a subroutine at a specified address. rts returns from a subroutine
53 table 2-3 instructions classified by function (cont) type instruction size * function system control trapa starts trap-instruction exception handling. instructions rte returns from an exception-handling routine. sleep causes a transition to a power-down state. ldc b/w (eas) ? ccr, (eas) ? exr moves the source operand contents or immediate data to ccr or exr. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. stc b/w ccr ? (ead), exr ? (ead) transfers ccr or exr contents to a general register or memory. although ccr and exr are 8-bit registers, word-size transfers are performed between them and memory. the upper 8 bits are valid. andc b ccr #imm ? ccr, exr #imm ? exr logically ands the ccr or exr contents with immediate data. orc b ccr #imm ? ccr, exr #imm ? exr logically ors the ccr or exr contents with immediate data. xorc b ccr ? #imm ? ccr, exr ? #imm ? exr logically exclusive-ors the ccr or exr contents with immediate data. nop pc + 2 ? pc only increments the program counter. note: * size refers to the operand size. b: byte w: word
54 table 2-3 instructions classified by function (cont) type instruction size * function block data transfer instruction eepmov.b eepmov.w if r4l 1 0 then repeat @er5+ ? @er6+ r4l? ? r4l until r4l = 0 else next; if r4 1 0 then repeat @er5+ ? @er6+ r4? ? r4 until r4 = 0 else next; transfers a data block according to parameters set in general registers r4l or r4, er5, and er6. r4l or r4: size of block (bytes) er5: starting source address er6: starting destination address execution of the next instruction begins as soon as the transfer is completed.
55 2.6.4 basic instruction formats the cpu instructions consist of 2-byte (1-word) units. an instruction consists of an operation field (op field), a register field (r field), an effective address extension (ea field), and a condition field (cc field). figure 2-12 shows examples of instruction formats. op op rn rm nop, rts, etc. add.b rn, rm, etc. mov.b @(d:16, rn), rm, etc. (1) operation field only (2) operation field and register fields (3) operation field, register fields, and effective address extension rn rm op ea (disp) (4) operation field, effective address extension, and condition field op cc ea (disp) bra d:16, etc figure 2-12 instruction formats (examples) (1) operation field: indicates the function of the instruction, the addressing mode, and the operation to be carried out on the operand. the operation field always includes the first four bits of the instruction. some instructions have two operation fields. (2) register field: specifies a general register. address registers are specified by 3 bits, data registers by 3 bits or 4 bits. some instructions have two register fields. some have no register field. (3) effective address extension: eight, 16, or 32 bits specifying immediate data, an absolute address, or a displacement. (4) condition field: specifies the branching condition of bcc instructions.
56 2.6.5 notes on use of bit-manipulation instructions the bset, bclr, bnot, bst, and bist instructions read a byte of data, carry out bit manipulation, then write back the byte of data. caution is therefore required when using these instructions on a register containing write-only bits, or a port. the bclr instruction can be used to clear internal i/o register flags to 0. in this case, the relevant flag need not be read beforehand if it is clear that it has been set to 1 in an interrupt handling routine, etc. 2.7 addressing modes and effective address calculation 2.7.1 addressing mode the cpu supports the eight addressing modes listed in table 2-4. each instruction uses a subset of these addressing modes. arithmetic and logic instructions can use the register direct and immediate modes. data transfer instructions can use all addressing modes except program-counter relative and memory indirect. bit manipulation instructions use register direct, register indirect, or absolute addressing mode to specify an operand, and register direct (bset, bclr, bnot, and btst instructions) or immediate (3-bit) addressing mode to specify a bit number in the operand. table 2-4 addressing modes no. addressing mode symbol 1 register direct rn 2 register indirect @ern 3 register indirect with displacement @(d:16,ern)/@(d:32,ern) 4 register indirect with post-increment register indirect with pre-decrement @ern+ @?rn 5 absolute address @aa:8/@aa:16/@aa:24/@aa:32 6 immediate #xx:8/#xx:16/#xx:32 7 program-counter relative @(d:8,pc)/@(d:16,pc) 8 memory indirect @@aa:8 (1) register direct?n: the register field of the instruction specifies an 8-, 16-, or 32-bit general register containing the operand. r0h to r7h and r0l to r7l can be specified as 8-bit registers. r0 to r7 and e0 to e7 can be specified as 16-bit registers. er0 to er7 can be specified as 32-bit registers.
57 (2) register indirect?ern: the register field of the instruction code specifies an address register (ern) which contains the address of the operand on memory. if the address is a program instruction address, the lower 24 bits are valid and the upper 8 bits are all assumed to be 0 (h'00). (3) register indirect with displacement?(d:16, ern) or @(d:32, ern): a 16-bit or 32-bit displacement contained in the instruction is added to an address register (ern) specified by the register field of the instruction, and the sum gives the address of a memory operand. a 16-bit displacement is sign-extended when added. (4) register indirect with post-increment or pre-decrement?ern+ or @-ern: register indirect with post-increment?@ern+ the register field of the instruction code specifies an address register (ern) which contains the address of a memory operand. after the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. the value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. for word or longword transfer instruction, the register value should be even. register indirect with pre-decrement?@-ern the value 1, 2, or 4 is subtracted from an address register (ern) specified by the register field in the instruction code, and the result becomes the address of a memory operand. the result is also stored in the address register. the value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction. for word or longword transfer instruction, the register value should be even. (5) absolute address?@aa:8, @aa:16, @aa:24, or @aa:32: the instruction code contains the absolute address of a memory operand. the absolute address may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long (@aa:32). to access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits (@aa:32) long. for an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (h'ffff). for a 16-bit absolute address the upper 16 bits are a sign extension. a 32-bit absolute address can access the entire address space. a 24-bit absolute address (@aa:24) indicates the address of a program instruction. the upper 8 bits are all assumed to be 0 (h'00). table 2-5 indicates the accessible absolute address ranges.
58 table 2-5 absolute address access ranges absolute address normal mode * advanced mode data address 8 bits (@aa:8) h'ff00 to h'ffff h'ffff00 to h'ffffff 16 bits (@aa:16) h'0000 to h'ffff h'000000 to h'007fff, h'ff8000 to h'ffffff 32 bits (@aa:32) h'000000 to h'ffffff program instruction address 24 bits (@aa:24) note: * not available in the h8s/2237 series and h8s/2227 series. (6) immediate?xx:8, #xx:16, or #xx:32: the instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. the adds, subs, inc, and dec instructions contain immediate data implicitly. some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. the trapa instruction contains 2-bit immediate data in its instruction code, specifying a vector address. (7) program-counter relative?(d:8, pc) or @(d:16, pc): this mode is used in the bcc and bsr instructions. an 8-bit or 16-bit displacement contained in the instruction is sign-extended and added to the 24-bit pc contents to generate a branch address. only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to be 0 (h'00). the pc value to which the displacement is added is the address of the first byte of the next instruction, so the possible branching range is ?26 to +128 bytes (?3 to +64 words) or ?2766 to +32768 bytes (?6383 to +16384 words) from the branch instruction. the resulting value should be an even number. (8) memory indirect?@aa:8: this mode can be used by the jmp and jsr instructions. the instruction code contains an 8-bit absolute address specifying a memory operand. this memory operand contains a branch address. the upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255 (h'0000 to h'00ff* in normal mode, h'000000 to h'0000ff in advanced mode). in normal mode the memory operand is a word operand and the branch address is 16 bits long. in advanced mode the memory operand is a longword operand, the first byte of which is assumed to be all 0 (h'00). note that the first part of the address range is also the exception vector area. for further details, refer to section 4, exception handling. note: * not available in the h8s/2237 series and h8s/2227 series.
59 (a) normal mode * (b) advanced mode branch address specified by @aa:8 specified by @aa:8 reserved branch address note: * not available in the h8s/2237 series and h8s/2227 series. figure 2-13 branch address specification in memory indirect mode if an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (for further information, see section 2.5.2, memory data formats.) 2.7.2 effective address calculation table 2-6 indicates how effective addresses are calculated in each addressing mode. in normal mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
60 register indirect with post-increment or pre-decrement ? register indirect with post-increment @ern+ no. addressing mode and instruction format effective address calculation effective address (ea) 1 register direct (rn) op rm rn operand is general register contents. register indirect (@ern) 2 register indirect with displacement @(d:16, ern) or @(d:32, ern) 3 ? register indirect with pre-decrement @?rn 4 general register contents general register contents sign extension disp general register contents 1, 2, or 4 general register contents 1, 2, or 4 byte word longword 1 2 4 operand size value added 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 31 0 op r r op op r r op disp 24 23 don? care 24 23 don? care 24 23 don? care 24 23 don? care table 2-6 effective address calculation
61 5 @aa:8 absolute address @aa:16 @aa:32 6 immediate #xx:8/#xx:16/#xx:32 31 0 8 7 operand is immediate data. no. addressing mode and instruction format effective address calculation effective address (ea) @aa:24 31 0 16 15 31 0 24 23 31 0 op abs op abs abs op op abs op imm h'ffff don? care 24 23 don? care 24 23 don? care 24 23 don? care sign extension table 2-6 effective address calculation (cont)
62 31 0 0 0 7 program-counter relative @(d:8, pc)/@(d:16, pc) 8 memory indirect @@aa:8 ? normal mode * ? advanced mode note: * not available in the h8s/2237 series and h8s/2227 series. 0 no. addressing mode and instruction format effective address calculation effective address (ea) 23 23 31 8 7 0 15 0 31 8 7 0 disp h'000000 abs h'000000 31 0 24 23 31 0 16 15 31 0 24 23 op disp op abs op abs sign extension pc contents abs memory contents memory contents h'00 don? care 24 23 don? care don? care table 2-6 effective address calculation (cont)
63 2.8 processing states 2.8.1 overview the cpu has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. figure 2-14 shows a diagram of the processing states. figure 2-15 indicates the state transitions. reset state the cpu and all on-chip supporting modules have been initialized and are stopped. exception-handling state a transient state in which the cpu changes the normal processing flow in response to a reset, interrupt, or trap instruction. program execution state the cpu executes program instructions in sequence. bus-released state the external bus has been released in response to a bus request signal from a bus master other than the cpu. power-down state cpu operation is stopped to conserve power. * sleep mode software standby mode hardware standby mode processing states note: * the power-down state also includes a medium-speed mode, module stop mode, subactive mode, subsleep mode, and watch mode. figure 2-14 processing states
64 end of bus request bus request program execution state bus-released state sleep mode exception-handling state external interrupt software standby mode mres = high res = high manual reset state * 1 power-on reset state * 1 reset state hardware standby mode * 2 power-down state * 3 notes: 1. 2. 3. from any state except hardware standby mode, a transition to the power-on reset state occurs whenever res goes low. from any state except hardware standby mode and the power-on reset state, a transition to the manual reset state occurs whenever mres goes low. a transition can also be made to the reset state when the watchdog timer overflows. from any state, a transition to hardware standby mode occurs when stby goes low. there are also other modes, including watch mode, subactive mode, and subsleep mode. for details, refer to section 20, power-down state. sleep instruction with ssby = 0 sleep instruction with ssby = 1 interrupt request end of bus request bus request request for exception handling end of exception handling stby = high, res = low figure 2-15 state transitions 2.8.2 reset state when the res input goes low all current processing stops and the cpu enters the power-on reset state. when the mres input goes low, the cpu enters the manual reset state. all interrupts are disabled in the reset state. reset exception handling starts when the res or mres signal changes from low to high. the reset state can also be entered by a watchdog timer overflow. for details, refer to section 12, watchdog timer.
65 2.8.3 exception-handling state the exception-handling state is a transient state that occurs when the cpu alters the normal processing flow due to a reset, interrupt, or trap instruction. the cpu fetches a start address (vector) from the exception vector table and branches to that address. (1) types of exception handling and their priority exception handling is performed for resets, traces, interrupts, and trap instructions. table 2-7 indicates the types of exception handling and their priority. trap instruction exception handling is always accepted, in the program execution state. exception handling and the stack structure depend on the interrupt control mode set in syscr. table 2-7 exception handling types and priority priority type of exception detection timing start of exception handling high reset synchronized with clock exception handling starts immediately after a low-to-high transition at the res or mres pin, or when the watchdog timer overflows. trace end of instruction execution or end of exception-handling sequence * 1 when the trace (t) bit is set to 1, the trace starts at the end of the current instruction or current exception-handling sequence interrupt end of instruction execution or end of exception-handling sequence * 2 when an interrupt is requested, exception handling starts at the end of the current instruction or current exception-handling sequence low trap instruction when trapa instruction is executed exception handling starts when a trap (trapa) instruction is executed * 3 notes: 1. traces are enabled only in interrupt control mode 2. trace exception-handling is not executed at the end of the rte instruction. 2. interrupts are not detected at the end of the andc, orc, xorc, and ldc instructions, or immediately after reset exception handling. 3. trap instruction exception handling is always accepted, in the program execution state.
66 (2) reset exception handling after the res or mres pin has gone low and the reset state has been entered, reset exception handling starts when res or mres goes high again. the cpu enters the power-on reset state when the res pin is low, and the manual reset state when the mres pin is low. when reset exception handling starts the cpu fetches a start address (vector) from the exception vector table and starts program execution from that address. all interrupts, including nmi, are disabled during reset exception handling and after it ends. (3) traces traces are enabled only in interrupt control mode 2. trace mode is entered when the t bit of exr is set to 1. when trace mode is established, trace exception handling starts at the end of each instruction. at the end of a trace exception-handling sequence, the t bit of exr is cleared to 0 and trace mode is cleared. interrupt masks are not affected. the t bit saved on the stack retains its value of 1, and when the rte instruction is executed to return from the trace exception-handling routine, trace mode is entered again. trace exception- handling is not executed at the end of the rte instruction. trace mode is not entered in interrupt control mode 0, regardless of the state of the t bit. (4) interrupt exception handling and trap instruction exception handling when interrupt or trap-instruction exception handling begins, the cpu references the stack pointer (er7) and pushes the program counter and other control registers onto the stack. next, the cpu alters the settings of the interrupt mask bits in the control registers. then the cpu fetches a start address (vector) from the exception vector table and program execution starts from that start address. figure 2-16 shows the stack after exception handling ends.
67 (c) interrupt control mode 0 (d) interrupt control mode 2 ccr pc (24 bits) sp notes: 1. 2. ignored when returning. not available in the h8s/2237 series and h8s/2227 series. ccr pc (24 bits) sp exr reserved * 1 (a) interrupt control mode 0 (b) interrupt control mode 2 ccr ccr * 1 pc (16 bits) sp ccr ccr * 1 pc (16 bits) sp exr reserved * 1 normal mode * 2 advanced mode figure 2-16 stack structure after exception handling (examples)
68 2.8.4 program execution state in this state the cpu executes program instructions in sequence. 2.8.5 bus-released state this is a state in which the bus has been released in response to a bus request from a bus master other than the cpu. while the bus is released, the cpu halts operations. there is one other bus master in addition to the cpu: the data transfer controller (dtc). for further details, refer to section 7, bus controller. 2.8.6 power-down state the power-down state includes both modes in which the cpu stops operating and modes in which the cpu does not stop. there are five modes in which the cpu stops operating: sleep mode, software standby mode, hardware standby mode, subsleep mode, and watch mode. there are also three other power-down modes: medium-speed mode, module stop mode, and subactive mode. in medium-speed mode the cpu and other bus masters operate on a medium-speed clock. module stop mode permits halting of the operation of individual modules, other than the cpu. subactive mode, subsleep mode, and watch mode are power-down states in which subclock input is used. for details, refer to section 20, power-down state. (1) sleep mode: a transition to sleep mode is made if the sleep instruction is executed while the ssby bit in sbycr and the lson bit in lpwrcr are both cleared to 0. in sleep mode, cpu operations stop immediately after execution of the sleep instruction. the contents of cpu registers are retained. (2) software standby mode: a transition to software standby mode is made if the sleep instruction is executed while the ssby bit in sbycr is set to 1, and the lson bit in lpwrcr and the pss bit in tcsr (wdt1) are both cleared to 0. in software standby mode, the cpu and clock halt and all mcu operations stop. as long as a specified voltage is supplied, the contents of cpu registers and on-chip ram are retained. the i/o ports also remain in their existing states. (3) hardware standby mode: a transition to hardware standby mode is made when the stby pin goes low. in hardware standby mode, the cpu and clock halt and all mcu operations stop. the on-chip supporting modules are reset, but as long as a specified voltage is supplied, on-chip ram contents are retained.
69 2.9 basic timing 2.9.1 overview the cpu is driven by a system clock, denoted by the symbol ? the period from one rising edge of ?to the next is referred to as a "state." the memory cycle or bus cycle consists of one, two, or three states. different methods are used to access on-chip memory, on-chip supporting modules, and the external address space. 2.9.2 on-chip memory (rom, ram) on-chip memory is accessed in one state. the data bus is 16 bits wide, permitting both byte and word transfer instruction. figure 2-17 shows the on-chip memory access cycle. figure 2-18 shows the pin states. internal address bus internal read signal internal data bus internal write signal internal data bus bus cycle t1 address read data write data read access write access figure 2-17 on-chip memory access cycle
70 bus cycle t1 unchanged address bus as rd hwr , lwr data bus ? high high high hi g h-impedance state figure 2-18 pin states during on-chip memory access
71 2.9.3 on-chip supporting module access timing the on-chip supporting modules are accessed in two states. the data bus is either 8 bits or 16 bits wide, depending on the particular internal i/o register being accessed. figure 2-19 shows the access timing for the on-chip supporting modules. figure 2-20 shows the pin states. bus cycle t1 t2 address read data write data internal read signal internal data bus internal write signal internal data bus read access write access internal address bus figure 2-19 on-chip supporting module access cycle
72 bus cycle t1 t2 unchanged address bus as rd hwr , lwr data bus ? high high high high-impedance state figure 2-20 pin states during on-chip supporting module access 2.9.4 external address space access timing the external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. in three-state access, wait states can be inserted. for further details, refer to section 7, bus controller.
73 section 3 mcu operating modes 3.1 overview 3.1.1 operating mode selection the h8s/2237 series and h8s/2227 series has four operating modes (modes 4 to 7). these modes enable selection of the cpu operating mode, enabling/disabling of on-chip rom, and the initial bus width setting, by setting the mode pins (md2 to md0). table 3-1 lists the mcu operating modes. table 3-1 mcu operating mode selection mcu cpu external data bus operating mode md2 md1 md0 operating mode description on-chip rom initial width max. width 0 * 000 1 * 1 2 * 10 3 * 1 4 1 0 0 advanced on-chip rom disabled, expanded mode disabled 16 bits 16 bits 5 1 8 bits 16 bits 6 1 0 on-chip rom enabled, expanded mode enabled 8 bits 16 bits 7 1 single-chip mode note: * not available in the h8s/2237 series and h8s/2227 series. the cpu? architecture allows for 4 gbytes of address space, but the h8s/2237 series and h8s/2227 series actually accesses a maximum of 16 mbytes. modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. the external expansion modes allow switching between 8-bit and 16-bit bus modes. after program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting. if 16-bit access is selected for any one area, 16-bit bus mode is set; if 8-bit access is selected for all areas, 8-bit bus mode is set. note that the functions of each pin depend on the operating mode.
74 the h8s/2237 series and h8s/2227 series can be used only in modes 4 to 7. this means that the mode pins must be set to select one of these modes. do not change the inputs at the mode pins during operation. 3.1.2 register configuration the h8s/2237 series and h8s/2227 series has a mode control register (mdcr) that indicates the inputs at the mode pins (md2 to md0), and a system control register (syscr) that controls the operation of the h8s/2237 series and h8s/2227 series. table 3-2 summarizes these registers. table 3-2 mcu registers name abbreviation r/w initial value address * mode control register mdcr r undetermined h'fde7 system control register syscr r/w h'01 h'fde5 note: * lower 16 bits of the address. 3.2 register descriptions 3.2.1 mode control register (mdcr) 7 1 6 0 5 0 4 0 3 0 0 mds0 * r 2 mds2 * r 1 mds1 * r note: * determined by pins md2 to md0. bit initial value r/w : : : mdcr is an 8-bit read-only register that indicates the current operating mode of the h8s/2237 series and h8s/2227 series. bit 7?eserved: read-only bit, always read as 1. bits 6 to 3?eserved: read-only bits, always read as 0. bits 2 to 0?ode select 2 to 0 (mds2 to mds0): these bits indicate the input levels at pins md2 to md0 (the current operating mode). bits mds2 to mds0 correspond to md2 to md0. mds2 to mds0 are read-only bits-they cannot be written to. the mode pin (md2 to md0) input levels are latched into these bits when mdcr is read. these latches are canceled by a power-on reset, but are retained after a manual reset.
75 3.2.2 system control register (syscr) 7 0 r/w 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 0 bit initial value r/w : : : syscr is an 8-bit readable/writable register that selects the interrupt control mode, the detected edge for nmi, and enables or disables mres pin input and on-chip ram. syscr is initialized to h?01 by a power-on reset and in hardware standby mode. in a manual reset, the intm1, intm0, nmieg, and rame bits are initialized, but the mrese bit is not. syscr is not initialized in software standby mode. bit 7?reserved: only 0 should be written to this bit. bit 6?reserved: read-only bit, always read as 0. bits 5 and 4?interrupt control mode 1 and 0 (intm1, intm0): these bits select the control mode of the interrupt controller. for details of the interrupt control modes, see section 5.4.1, interrupt control modes and interrupt operation. bit 5 bit 4 interrupt intm1 intm0 control mode description 0 0 0 control of interrupts by i bit (initial value) 1 setting prohibited 1 0 2 control of interrupts by i2 to i0 bits and ipr 1 setting prohibited bit 3?mi edge select (nmieg): selects the valid edge of the nmi interrupt input. bit 3 nmieg description 0 an interrupt is requested at the falling edge of nmi input (initial value) 1 an interrupt is requested at the rising edge of nmi input
76 bit 2?anual reset select (mrese): enables or disables the mres pin. table 3-3 shows the relationship between the res and mres pin values and type of reset. for details of resets, see section 4.2, resets. bit 2 mrese description 0 manual reset is disabled p74/ mres pin can be used as p74 i/o pin (initial value) 1 manual reset is enabled p74/ mres pin can be used as mres input pin table 3-3 relationship between res and mres pin values and type of reset pins res mres type of reset 0 * power-on reset 1 0 manual reset 1 1 operating state * : don? care bit 1?eserved: read-only bit, always read as 0. bit 0?am enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset status is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value) note: when the dtc is used, the rame bit should not be cleared to 0.
77 3.3 operating mode descriptions 3.3.1 mode 4 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. pins p13 to p10, and ports a, b, and c function as an address bus, ports d and e function as a data bus, and part of port f carries bus control signals. pins p13 to p11 function as input ports immediately after a reset. address (a23 to a21) output can be enabled or disabled by bits ae3 to ae0 in the pin function control register (pfcr) regardless of the corresponding data direction register (ddr) values. pin 10 and ports a and b function as address (a20 to a8) outputs immediately after a reset. address output can be enabled or disabled by bits ae3 to ae0 in pfcr regardless of the corresponding ddr values. pins for which address output is disabled among pins p13 to p10 and in ports a and b become port outputs when the corresponding ddr bits are set to 1. port c always has an address (a7 to a0) output function. the initial bus mode after a reset is 16 bits, with 16-bit access to all areas. however, note that if 8-bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits. 3.3.2 mode 5 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is disabled. pins p13 to p10, and ports a, b, and c function as an address bus, ports d and e function as a data bus, and part of port f carries bus control signals. pins p13 to p11 function as input ports immediately after a reset. address (a23 to a21) output can be enabled or disabled by bits ae3 to ae0 in the pin function control register (pfcr) regardless of the corresponding data direction register (ddr) values. pin 10 and ports a and b function as address (a20 to a8) outputs immediately after a reset. address output can be enabled or disabled by bits ae3 to ae0 in pfcr regardless of the corresponding ddr values. pins for which address output is disabled among pins p13 to p10 and in ports a and b become port outputs when the corresponding ddr bits are set to 1. port c always has an address (a7 to a0) output function. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if 16- bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port e becomes a data bus.
78 3.3.3 mode 6 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled. pins p13 to p10, and ports a and b function as input ports immediately after a reset. address (a23 to a8) output can be enabled or disabled by bits ae3 to ae0 in the pin function control register (pfcr) regardless of the corresponding data direction register (ddr) values. pins for which address output is disabled among pins p13 to p10 and in ports a and b become port outputs when the corresponding ddr bits are set to 1. ports d and e function as a data bus, and part of port f carries data bus signals. port c is an input port immediately after a reset. addresses a7 to a0 are output by setting the corresponding ddr bits to 1. the initial bus mode after a reset is 8 bits, with 8-bit access to all areas. however, note that if 16- bit access is designated by the bus controller for any area, the bus mode switches to 16 bits and port e becomes a data bus. 3.3.4 mode 7 the cpu can access a 16-mbyte address space in advanced mode. the on-chip rom is enabled, but external addresses cannot be accessed. all i/o ports are available for use as input-output ports.
79 3.4 pin functions in each operating mode the pin functions of ports 1, and a to f vary depending on the operating mode. table 3-4 shows their functions in each operating mode. table 3-4 pin functions in each mode port mode 4 mode 5 mode 6 mode 7 port 1 p13 to p11 p * /a p * /a p * /a p p10 p/a * p/a * p * /a p port a pa3 to pa0 p/a * p/a * p * /a p port b p/a * p/a * p * /a p port c a a p * /a p port d dddp port e p/d * p * /d p * /d p port f pf7 p/c * p/c * p/c * p * /c pf6 to pf4 cccp pf3 p/c * p * /c p * /c pf2 to pf0 p * /c p * /c p * /c legend p: i/o port a: address bus output d: data bus i/o c: control signals, clock i/o * : after reset 3.5 memory map in each operating mode the h8s/2237, h8s/2227, h8s/2235, h8s/2225, h8s/2223, and h8s/2223 memory maps are shown in figures 3-1 to 3-3. the address space is 16 mbytes in modes 4 to 7 (advanced modes). the address space is divided into eight areas for modes 4 to 7. for details, see section 7, bus controller.
80 modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) external address space on-chip rom on-chip ram * on-chip ram * on-chip ram * on-chip ram note: internal i/o registers on-chip rom external address space external address space on-chip ram * on-chip ram internal i/o registers internal i/o registers internal i/o registers internal i/o registers external address space external address space internal i/o registers external address space h'000000 h'000000 h'000000 h'020000 h'ffb000 h'ffefc0 h'fff800 h'fff800 h'ffb000 h'ffefc0 h'01ffff h'ffb000 h'ffefbf h'ffff40 h'ffff40 h'fff800 h'ffff3f h'ffff60 h'ffff60 h'ffff60 h'ffffff h'ffffff h'ffffff h'ffffc0 h'ffffc0 h'ffffc0 external addresses can be accessed by clearing the rame bit in syscr to 0. * figure 3-1 memory map in each operating mode in the h8s/2237 and h8s/2227
81 external address space on-chip rom on-chip ram * note: internal i/o registers on-chip rom external address space external address space on-chip ram * reserved area * reserved area * on-chip ram on-chip ram * on-chip ram * on-chip ram internal i/o registers internal i/o registers internal i/o registers internal i/o registers external address space external address space internal i/o registers external address space h'000000 h'000000 h'000000 h'020000 h'ffb000 h'ffe000 h'ffe000 h'ffefc0 h'ffffc0 h'ffb000 h'ffefc0 h'ffffc0 h'ffefbf h'ffe000 h'ffffc0 h'ffffff h'ffffff h'ffffff h'ffff40 h'ffff40 h'fff800 h'ffff3f h'ffff60 h'ffff60 h'ffff60 h'fff800 h'fff800 h'01ffff external addresses can be accessed by clearing the rame bit in syscr to 0. * modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) figure 3-2 memory map in each operating mode in the h8s/2235 and h8s/2225
82 external address space on-chip rom on-chip ram * note: internal i/o registers on-chip rom external address space external address space on-chip ram * reserved area * reserved area * reserved area on-chip ram on-chip ram * on-chip ram * on-chip ram internal i/o registers internal i/o registers internal i/o registers internal i/o registers external address space external address space internal i/o registers external address space h'000000 h'000000 h'010000 h'000000 h'020000 h'ffb000 h'ffe000 h'ffe000 h'ffefc0 h'ffffc0 h'ffb000 h'ffefc0 h'ffffc0 h'ffefbf h'ffe000 h'ffffc0 h'ffffff h'ffffff h'ffffff h'ffff40 h'ffff40 h'fff800 h'ffff3f h'ffff60 h'ffff60 h'ffff60 h'fff800 h'fff800 h'00ffff external addresses can be accessed by clearing the rame bit in syscr to 0. * modes 4 and 5 (advanced expanded modes with on-chip rom disabled) mode 6 (advanced expanded mode with on-chip rom enabled) mode 7 (advanced single-chip mode) figure 3-3 memory map in each operating mode in the h8s/2233 and h8s/2223
83 section 4 exception handling 4.1 overview 4.1.1 exception handling types and priority as table 4-1 indicates, exception handling may be caused by a reset, trace, trap instruction, or interrupt. exception handling is prioritized as shown in table 4-1. if two or more exceptions occur simultaneously, they are accepted and processed in order of priority. trap instruction exceptions are accepted at all times, in the program execution state. exception handling sources, the stack structure, and the operation of the cpu vary depending on the interrupt control mode set by the intm0 and intm1 bits of syscr. table 4-1 exception handling types and priority priority exception handling type start of exception handling high reset starts immediately after a low-to-high transition at the res or mres pin, or when the watchdog timer overflows. the cpu enters the power-on reset state when the res pin is low, and the manual reset state when the mres pin is low. trace * 1 starts when execution of the current instruction or exception handling ends, if the trace (t) bit is set to 1 interrupt starts when execution of the current instruction or exception handling ends, if an interrupt request has been issued * 2 low trap instruction (trapa) * 3 started by execution of a trap instruction (trapa) notes: 1. traces are enabled only in interrupt control mode 2. trace exception handling is not executed after execution of an rte instruction. 2. interrupt detection is not performed on completion of andc, orc, xorc, or ldc instruction execution, or on completion of reset exception handling. 3. trap instruction exception handling requests are accepted at all times in program execution state.
84 4.1.2 exception handling operation exceptions originate from various sources. trap instructions and interrupts are handled as follows: 1. the program counter (pc), condition code register (ccr), and extended register (exr) are pushed onto the stack. 2. the interrupt mask bits are updated. the t bit is cleared to 0. 3. a vector address corresponding to the exception source is generated, and program execution starts from that address. for a reset exception, steps 2 and 3 above are carried out. 4.1.3 exception sources and vector table the exception sources are classified as shown in figure 4-1. different vector addresses are assigned to different exception sources. table 4-2 lists the exception sources and their vector addresses. exception sources reset trace direct transition interrupts trap instruction power-on reset manual reset external interrupts: nmi, irq7 to irq0 internal interrupts: 53 interrupt sources (h8s/2237) and 36 interrupt sources (h8s/2227) in on-chip supporting modules figure 4-1 exception sources
85 table 4-2 exception vector table vector address * 1 exception source vector number advanced mode power-on reset 0 h'0000 to h'0003 manual reset 1 h'0004 to h'0007 reserved for system use 2 h'0008 to h'000b 3 h'000c to h'000f 4 h'0010 to h'0013 trace 5 h'0014 to h'0017 direct transition * 3 6 h'0018 to h'001b external interrupt nmi 7 h'001c to h'001f trap instruction (4 sources) 8 h'0020 to h'0023 9 h'0024 to h'0027 10 h'0028 to h'002b 11 h'002c to h'002f reserved for system use 12 h'0030 to h'0033 13 h'0034 to h'0037 14 h'0038 to h'003b 15 h'003c to h'003f external interrupt irq0 16 h'0040 to h'0043 irq1 17 h'0044 to h'0047 irq2 18 h'0048 to h'004b irq3 19 h'004c to h'004f irq4 20 h'0050 to h'0053 irq5 21 h'0054 to h'0057 irq6 22 h'0058 to h'005b irq7 23 h'005c to h'005f internal interrupt * 2 24 ? 123 h'0060 to h'0063 ? h'01ec to h'01ef notes: 1. lower 16 bits of the address. 2. for details of internal interrupt vectors, see section 5.3.3, interrupt exception handling vector table. 3. for details of direct transition, see section 20.11, direct transition.
86 4.2 reset 4.2.1 overview a reset has the highest exception priority. when the res or mres pin goes low, all processing halts and the h8s/2237 series and h8s/2227 series enter the reset state. a reset initializes the internal state of the cpu and the registers of on-chip supporting modules. immediately after a reset, interrupt control mode 0 is set. reset exception handling begins when the res or mres pin changes from low to high. the levels of the res and mres pins at reset determine whether a power-on reset or a manual reset is effected. the h8s/2237 series and h8s/2227 series can also be reset by overflow of the watchdog timer. for details see section 12, watchdog timer. 4.2.2 reset types a reset can be of either of two types: a power-on reset or a manual reset. reset types are shown in table 4-3. a power-on reset should be used when powering on. the internal state of the cpu is initialized by either type of reset. a power-on reset also initializes all the registers in the on-chip supporting modules, while a manual reset initializes all the registers in the on-chip supporting modules except for the bus controller and i/o ports, which retain their previous states. with a manual reset, since the on-chip supporting modules are initialized, ports used as on-chip supporting module i/o pins are switched to i/o ports controlled by ddr and dr. table 4-3 reset types reset transition conditions internal state type mres res cpu on-chip supporting modules power-on reset * low initialized initialized manual reset low high initialized initialized, except for bus controller and i/o ports * : don? care a reset caused by the watchdog timer can also be of either of two types: a power-on reset or a manual reset.
87 when the mres pin is used, mres pin input must be enabled by setting the mrese bit to 1 in syscr. 4.2.3 reset sequence the h8s/2237 series and h8s/2227 series enter the reset state when the res or mres pin goes low. to ensure that the h8s/2237 series and h8s/2227 series are reset, hold the res or mres pin low for at least 20 ms at power-up. to reset the h8s/2237 series and h8s/2227 series during operation, hold the res or mres pin low for at least 20 states. when the res or mres pin goes high after being held low for the necessary time, the chip starts reset exception handling as follows: 1. the internal state of the cpu and the registers of the on-chip supporting modules are initialized, the t bit is cleared to 0 in exr, and the i bit is set to 1 in exr and ccr. 2. the reset exception handling vector address is read and transferred to the pc, and program execution starts from the address indicated by the pc. figures 4-2 and 4-3 show examples of the reset sequence.
88 internal address bus internal read signal internal write signal internal data bus (1) (3) vector fetch internal processing prefetch of first program instruction high (1) reset exception handling vector address (for a power-on reset, (1) = h'0000; for a manual reset, (1) = h'0002) (2) start address (contents of reset exception handling vector address) (3) start address ((3) = (2)) (4) first program instruction (2) (4) res, mres figure 4-2 reset sequence (modes 2 and 3: not available in the h8s/2237 series and h8s/2227 series)
89 address bus vector fetch internal processing prefetch of first program instruction (1) (3) reset exception handling vector address (for a power-on reset, (1) = h'000000, (3) = h'000002; for a manual reset, (1) = h'000004, (3) = h'000006) (2) (4) start address (contents of reset exception handling vector address) (5) start address ((5) = (2) (4)) (6) first program instruction res, mres (1) (5) high (2) (4) (3) (6) rd hwr, lwr d 15 to d 0 * note: * 3 program wait states are inserted. ** figure 4-3 reset sequence (mode 4) 4.2.4 interrupts after reset if an interrupt is accepted after a reset but before the stack pointer (sp) is initialized, the pc and ccr will not be saved correctly, leading to a program crash. to prevent this, all interrupt requests, including nmi, are disabled immediately after a reset. since the first instruction of a program is always executed immediately after the reset state ends, make sure that this instruction initializes the stack pointer (example: mov.l #xx:32, sp). 4.2.5 state of on-chip supporting modules after reset release after reset release, mstpcra is initialized to h'3f, mstpcrb and mstpcrc are initialized to h'ff, and all modules except the dtc enter module stop mode. consequently, on-chip supporting module registers cannot be read or written to. register reading and writing is enabled when module stop mode is exited.
90 4.3 traces traces are enabled in interrupt control mode 2. trace mode is not activated in interrupt control mode 0, irrespective of the state of the t bit. for details of interrupt control modes, see section 5, interrupt controller. if the t bit in exr is set to 1, trace mode is activated. in trace mode, a trace exception occurs on completion of each instruction. trace mode is canceled by clearing the t bit in exr to 0. it is not affected by interrupt masking. table 4-4 shows the state of ccr and exr after execution of trace exception handling. interrupts are accepted even within the trace exception handling routine. the t bit saved on the stack retains its value of 1, and when control is returned from the trace exception handling routine by the rte instruction, trace mode resumes. trace exception handling is not carried out after execution of the rte instruction. table 4-4 status of ccr and exr after trace exception handling ccr exr interrupt control mode i ui i2 to i0 t 0 trace exception handling cannot be used. 210 legend 1: set to 1 0: cleared to 0 ? retains value prior to execution.
91 4.4 interrupts interrupt exception handling can be requested by nine external sources (nmi, irq7 to irq0) and 53 (h8s/2237) or 36 (h8s/2227) internal sources in the on-chip supporting modules. figure 4-4 classifies the interrupt sources and the number of interrupts of each type. the on-chip supporting modules that can request interrupts include the watchdog timer (wdt), 16-bit timer-pulse unit (tpu), 8-bit timer, serial communication interface (sci), data transfer controller (dtc), pc break controller (pbc) and a/d converter. each interrupt source has a separate vector address. nmi is the highest-priority interrupt. interrupts are controlled by the interrupt controller. the interrupt controller has two interrupt control modes and can assign interrupts other than nmi to eight priority/mask levels to enable multiplexed interrupt control. for details of interrupts, see section 5, interrupt controller. interrupts external interrupts internal interrupts nmi (1) irq7 to irq0 (8) wdt * (2) tpu (2237: 26, 2227: 13) 8-bit timer (6) sci (2237: 16, 2227: 12) dtc (1) a/d converter (1) other (1) numbers in parentheses are the numbers of interrupt sources. * when the watchdog timer is used as an interval timer, it generates an interrupt request at each counter overflow. notes: figure 4-4 interrupt sources and number of interrupts
92 4.5 trap instruction trap instruction exception handling starts when a trapa instruction is executed. trap instruction exception handling can be executed at all times in the program execution state. the trapa instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. table 4-5 shows the status of ccr and exr after execution of trap instruction exception handling. table 4-5 status of ccr and exr after trap instruction exception handling ccr exr interrupt control mode i ui i2 to i0 t 01 210 legend 1: set to 1 0: cleared to 0 ? retains value prior to execution.
93 4.6 stack status after exception handling figure 4-5 shows the stack after completion of trap instruction exception handling and interrupt exception handling. sp sp ccr ccr * pc (16 bits) ccr ccr * pc (16 bits) reserved * exr (a) interrupt control mode 0 (b) interrupt control mode 2 note: * ignored on return. figure 4-5 (1) stack status after exception handling (normal modes: not available in the h8s/2237 series and h8s/2227 series) sp sp ccr pc (24bits) ccr pc (24bits) reserved * exr (a) interrupt control mode 0 (b) interrupt control mode 2 note: * ignored on return. figure 4-5 (2) stack status after exception handling (advanced modes)
94 4.7 notes on use of the stack when accessing word data or longword data, the h8s/2237 series and h8s/2227 series assume that the lowest address bit is 0. the stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (sp: er7) should always be kept even. use the following instructions to save registers: push.w rn (or mov.w rn, @-sp) push.l ern (or mov.l ern, @-sp) use the following instructions to restore registers: pop.w rn (or mov.w @sp+, rn) pop.l ern (or mov.l @sp+, ern) setting sp to an odd value may lead to a malfunction. figure 4-6 shows an example of what happens when the sp value is odd. sp legend note: this diagram illustrates an example in which the interrupt control mode is 0, in advanced mode. sp sp ccr pc r1l pc h'fffefa h'fffefb h'fffefc h'fffefd h'fffeff mov.b r1l, @?r7 sp set to h'fffeff trap instruction executed data saved above sp contents of ccr lost ccr: condition code register pc: program counter r1l: general register r1l sp: stack pointer figure 4-6 operation when sp value is odd
95 section 5 interrupt controller 5.1 overview 5.1.1 features the h8s/2237 series and h8s/2227 series control interrupts by means of an interrupt controller. the interrupt controller has the following features: two interrupt control modes ? any of two interrupt control modes can be set by means of the intm1 and intm0 bits in the system control register (syscr). priorities settable with ipr ? an interrupt priority register (ipr) is provided for setting interrupt priorities. eight priority levels can be set for each module for all interrupts except nmi. ? nmi is assigned the highest priority level of 8, and can be accepted at all times. independent vector addresses ? all interrupt sources are assigned independent vector addresses, making it unnecessary for the source to be identified in the interrupt handling routine. nine external interrupts ? nmi is the highest-priority interrupt, and is accepted at all times. rising edge or falling edge can be selected for nmi. ? falling edge, rising edge, or both edge detection, or level sensing, can be selected for irq7 to irq0. dtc control ? dtc activation is performed by means of interrupts.
96 5.1.2 block diagram a block diagram of the interrupt controller is shown in figure 5-1. syscr nmi input irq input internal interrupt request swdtend to tei3 intm1 intm0 nmieg nmi input unit irq input unit isr iscr ier ipr interrupt controller priority determination interrupt request vector number i, ui i2 to i0 ccr exr cpu iscr ier isr ipr syscr : irq sense control register : irq enable register : irq status register : interrupt priority register : system control register legend figure 5-1 block diagram of interrupt controller
97 5.1.3 pin configuration table 5-1 summarizes the pins of the interrupt controller. table 5-1 interrupt controller pins name symbol i/o function nonmaskable interrupt nmi input nonmaskable external interrupt; rising or falling edge can be selected external interrupt requests 7 to 0 irq7 to irq0 input maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected 5.1.4 register configuration table 5-2 summarizes the registers of the interrupt controller. table 5-2 interrupt controller registers name abbreviation r/w initial value address * 1 system control register syscr r/w h'01 h'fde5 irq sense control register h iscrh r/w h'00 h'fe12 irq sense control register l iscrl r/w h'00 h'fe13 irq enable register ier r/w h'00 h'fe14 irq status register isr r/(w) * 2 h'00 h'fe15 interrupt priority register a ipra r/w h'77 h'fec0 interrupt priority register b iprb r/w h'77 h'fec1 interrupt priority register c iprc r/w h'77 h'fec2 interrupt priority register d iprd r/w h'77 h'fec3 interrupt priority register e ipre r/w h'77 h'fec4 interrupt priority register f iprf r/w h'77 h'fec5 interrupt priority register g iprg r/w h'77 h'fec6 interrupt priority register h iprh r/w h'77 h'fec7 interrupt priority register i ipri r/w h'77 h'fec8 interrupt priority register j iprj r/w h'77 h'fec9 interrupt priority register k iprk r/w h'77 h'feca interrupt priority register o ipro r/w h'77 h'fece notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing.
98 5.2 register descriptions 5.2.1 system control register (syscr) 7 0 r/w 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 0 bit initial value r/w : : : syscr is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for nmi. only bits 5 to 3 are described here; for details of the other bits, see section 3.2.2, system control register (syscr). syscr is initialized to h'01 by a power-on reset and in hardware standby mode. in a manual reset, the intm1, intm0, nmieg, and rame bits are initialized, but the mrese bit is not. syscr is not initialized in software standby mode. bits 5 and 4?nterrupt control mode 1 and 0 (intm1, intm0): these bits select one of two interrupt control modes for the interrupt controller. bit 5 bit 4 interrupt intm1 intm0 control mode description 0 0 0 interrupts are controlled by i bit (initial value) 1 setting prohibited 1 0 2 interrupts are controlled by bits i2 to i0, and ipr 1 setting prohibited bit 3?mi edge select (nmieg): selects the input edge for the nmi pin. bit 3 nmieg description 0 interrupt request generated at falling edge of nmi input (initial value) 1 interrupt request generated at rising edge of nmi input
99 5.2.2 interrupt priority registers a to k, o (ipra to iprk, ipro) 7 0 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 0 0 ipr0 1 r/w 2 ipr2 1 r/w 1 ipr1 1 r/w bit initial value r/w : : : the ipr registers are twelve 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than nmi. the correspondence between ipr settings and interrupt sources is shown in table 5-3. the ipr registers set a priority (level 7 to 0) for each interrupt source other than nmi. the ipr registers are initialized to h'77 by a reset and in hardware standby mode. they are not initialized in software standby mode. bits 7 and 3?eserved: read-only bits, always read as 0. table 5-3 correspondence between interrupt sources and ipr settings bits register 6 to 4 2 to 0 ipra irq0 irq1 iprb irq2 irq3 irq4 irq5 iprc irq6 irq7 dtc iprd watchdog timer 0 * 1 ipre pc break a/d converter, watchdog timer 1 iprf tpu channel 0 tpu channel 1 iprg tpu channel 2 tpu channel 3 * 2 iprh tpu channel 4 * 2 tpu channel 5 * 2 ipri 8-bit timer channel 0 8-bit timer channel 1 iprj * 1 sci channel 0 iprk sci channel 1 sci channel 2 * 2 ipro sci channel 3 * 1 notes: 1. reserved bits. these bits cannot be modified and are always read as 1. 2. h8s/2237 series only.
100 as shown in table 5-3, multiple interrupts are assigned to one ipr. setting a value in the range from h'0 to h'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. the lowest priority level, level 0, is assigned by setting h'0, and the highest priority level, level 7, by setting h'7. when interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the ipr registers is selected. this interrupt level is then compared with the interrupt mask level set by the interrupt mask bits (i2 to i0) in the extend register (exr) in the cpu, and if the priority level of the interrupt is higher than the set mask level, an interrupt request is issued to the cpu. 5.2.3 irq enable register (ier) 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w bit initial value r/w : : : ier is an 8-bit readable/writable register that controls enabling and disabling of interrupt requests irq7 to irq0. ier is initialized to h'00 by a reset and in hardware standby mode. they are not initialized in software standby mode. bits 7 to 0?rq7 to irq0 enable (irq7e to irq0e): these bits select whether irq7 to irq0 are enabled or disabled. bit n irqne description 0 irqn interrupts disabled (initial value) 1 irqn interrupts enabled (n = 7 to 0)
101 5.2.4 irq sense control registers h and l (iscrh, iscrl) iscrh 15 irq7scb 0 r/w 14 irq7sca 0 r/w 13 irq6scb 0 r/w 12 irq6sca 0 r/w 11 irq5scb 0 r/w 8 irq4sca 0 r/w 10 irq5sca 0 r/w 9 irq4scb 0 r/w bit initial value r/w : : : iscrl 7 irq3scb 0 r/w 6 irq3sca 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w bit initial value r/w : : : the iscr registers are 16-bit readable/writable registers that select rising edge, falling edge, or both edge detection, or level sensing, for the input at pins irq7 to irq0 . the iscr registers are initialized to h'0000 by a reset and in hardware standby mode. they are not initialized in software standby mode. bits 15 to 0: irq7 sense control a and b (irq7sca, irq7scb) to irq0 sense control a and b (irq0sca, irq0scb) bits 15 to 0 irq7scb to irq0scb irq7sca to irq0sca description 0 0 interrupt request generated at irq7 to irq0 input low level (initial value) 1 interrupt request generated at falling edge of irq7 to irq0 input 1 0 interrupt request generated at rising edge of irq7 to irq0 input 1 interrupt request generated at both falling and rising edges of irq7 to irq0 input
102 5.2.5 irq status register (isr) 7 irq7f 0 r/(w) * 6 irq6f 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * bit initial value r/w note: * only 0 can be written, to clear the flag. : : : isr is an 8-bit readable/writable register that indicates the status of irq7 to irq0 interrupt requests. isr is initialized to h'00 by a reset and in hardware standby mode. they are not initialized in software standby mode. bits 7 to 0?rq7 to irq0 flags (irq7f to irq0f): these bits indicate the status of irq7 to irq0 interrupt requests. bit n irqnf description 0 [clearing conditions] (initial value) cleared by reading irqnf flag when irqnf = 1, then writing 0 to irqnf flag when interrupt exception handling is executed when low-level detection is set (irqnscb = irqnsca = 0) and irqn input is high when irqn interrupt exception handling is executed when falling, rising, or both-edge detection is set (irqnscb = 1 or irqnsca = 1) when the dtc is activated by an irqn interrupt, and the disel bit in mrb of the dtc is cleared to 0 1 [setting conditions] when irqn input goes low when low-level detection is set (irqnscb = irqnsca = 0) when a falling edge occurs in irqn input when falling edge detection is set (irqnscb = 0, irqnsca = 1) when a rising edge occurs in irqn input when rising edge detection is set (irqnscb = 1, irqnsca = 0) when a falling or rising edge occurs in irqn input when both-edge detection is set (irqnscb = irqnsca = 1) (n = 7 to 0)
103 5.3 interrupt sources interrupt sources comprise external interrupts (nmi and irq7 to irq0) and internal interrupts (53 in the h8s/2237 series, 36 in the h8s/2227 series). 5.3.1 external interrupts there are nine external interrupts: nmi and irq7 to irq0. of these, nmi and irq2 to irq0 can be used to restore the h8s/2237 series and h8s/2227 series from software standby mode. nmi interrupt: nmi is the highest-priority interrupt, and is always accepted by the cpu regardless of the interrupt control mode or the status of the cpu interrupt mask bits. the nmieg bit in syscr can be used to select whether an interrupt is requested at a rising edge or a falling edge on the nmi pin. the vector number for nmi interrupt exception handling is 7. irq7 to irq0 interrupts: interrupts irq7 to irq0 are requested by an input signal at pins irq7 to irq0 . interrupts irq7 to irq0 have the following features: using iscr, it is possible to select whether an interrupt is generated by a low level, falling edge, rising edge, or both edges, at pins irq7 to irq0 . enabling or disabling of interrupt requests irq7 to irq0 can be selected with ier. the interrupt priority level can be set with ipr. the status of interrupt requests irq7 to irq0 is indicated in isr. isr flags can be cleared to 0 by software. a block diagram of interrupts irq7 to irq0 is shown in figure 5-2. irqn interrupt request irqne irqnf s r q clear signal edge/level detection circuit irqnsca, irqnscb irqn input note: n: 7 to 0 figure 5-2 block diagram of interrupts irq7 to irq0
104 figure 5-3 shows the timing of setting irqnf. irqn input pin irqnf figure 5-3 timing of setting irqnf the vector numbers for irq7 to irq0 interrupt exception handling are 23 to 16. detection of irq7 to irq0 interrupts does not depend on whether the relevant pin has been set for input or output. however, when a pin is used as an external interrupt input pin, do not clear the corresponding ddr to 0 and use the pin as an i/o pin for another function. since interrupt request flags irq7f to irq0f are set when the setting condition is satisfied, regardless of the ier setting, only the necessary flags should be referenced. 5.3.2 internal interrupts there are 53 (h8s/2237 series) or 36 (h8s/2227 series) sources for internal interrupts from on- chip supporting modules. for each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. if both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. the interrupt priority level can be set by means of ipr. the dtc can be activated by a tpu, 8-bit timer, sci, or other interrupt request. when the dtc is activated by an interrupt, the interrupt control mode and interrupt mask bits are not affected. 5.3.3 interrupt exception handling vector table table 5-4 shows interrupt exception handling sources, vector addresses, and interrupt priorities. for default priorities, the lower the vector number, the higher the priority. priorities among modules can be set by means of the ipr. the situation when two or more modules are set to the same priority, and priorities within a module, are fixed as shown in table5-4.
105 table 5-4 interrupt sources, vector addresses, and interrupt priorities origin of vector address * interrupt source interrupt source vector number advanced mode ipr priority nmi external 7 h'001c high irq0 pin 16 h'0040 ipra6 to 4 irq1 17 h'0044 ipra2 to 0 irq2 irq3 18 19 h'0048 h'004c iprb6 to 4 irq4 irq5 20 21 h'0050 h'0054 iprb2 to 0 irq6 irq7 22 23 h'0058 h'005c iprc6 to 4 swdtend (software activation interrupt end) dtc 24 h'0060 iprc2 to 0 wovi0 (interval timer) watchdog timer 0 25 h'0064 iprd6 to 4 pc break pc break 27 h'006c ipre6 to 4 adi (a/d conversion end) a/d 28 h'0070 ipre2 to 0 wovi1 (interval timer) watchdog timer 1 29 h'0074 reserved 30 31 h'0078 h'007c tgi0a (tgr0a input capture/compare match) tgi0b (tgr0b input capture/compare match) tgi0c (tgr0c input capture/compare match) tgi0d (tgr0d input capture/compare match) tci0v (overflow 0) tpu channel 0 32 33 34 35 36 h'0080 h'0084 h'0088 h'008c h'0090 iprf6 to 4 reserved 37 38 39 h'0094 h'0098 h'009c low note: * lower 16 bits of the start address.
106 table 5-4 interrupt sources, vector addresses, and interrupt priorities (cont) vector address * 1 interrupt source vector number advanced mode ipr priority tgi1a (tgr1a input capture/compare match) tgi1b (tgr1b input capture/compare match) tci1v (overflow 1) tci1u (underflow 1) tpu channel 1 40 41 42 43 h'00a0 h'00a4 h'00a8 h'00ac iprf2 to 0 high tgi2a (tgr2a input capture/compare match) tgi2b (tgr2b input capture/compare match) tci2v (overflow 2) tci2u (underflow 2) tpu channel 2 44 45 46 47 h'00b0 h'00b4 h'00b8 h'00bc iprg6 to 4 tgi3a (tgr3a input capture/compare match) tgi3b (tgr3b input capture/compare match) tgi3c (tgr3c input capture/compare match) tgi3d (tgr3d input capture/compare match) tci3v (overflow 3) tpu channel 3 * 2 48 49 50 51 52 h'00c0 h'00c4 h'00c8 h'00cc h'00d0 iprg2 to 0 reserved 53 54 55 h'00d4 h'00d8 h'00dc tgi4a (tgr4a input capture/compare match) tgi4b (tgr4b input capture/compare match) tci4v (overflow 4) tci4u (underflow 4) tpu channel 4 * 2 56 57 58 59 h'00e0 h'00e4 h'00e8 h'00ec iprh6 to 4 tgi5a (tgr5a input capture/compare match) tgi5b (tgr5b input capture/compare match) tci5v (overflow 5) tci5u (underflow 5) tpu channel 5 * 2 60 61 62 63 h'00f0 h'00f4 h'00f8 h'00fc iprh2 to 0 low notes: 1. lower 16 bits of the start address. 2. h8s/2237 series only. origin of interrupt source
107 table 5-4 interrupt sources, vector addresses, and interrupt priorities (cont) vector address * 1 interrupt source vector number advanced mode ipr priority cmia0 (compare match a) cmib0 (compare match b) ovi0 (overflow) 8-bit timer channel 0 64 65 66 h'0100 h'0104 h'0108 ipri6 to 4 high reserved 67 h'010c cmia1 (compare match a) cmib1 (compare match b) ovi1 (overflow) 8-bit timer channel 1 68 69 70 h'0110 h'0114 h'0118 ipri2 to 0 reserved 71 h'011c eri0 (receive error 0) rxi0 (reception completed 0) txi0 (transmit data empty 0) tei0 (transmission end 0) sci channel 0 80 81 82 83 h'0140 h'0144 h'0148 h'014c iprj2 to 0 eri1 (receive error 1) rxi1 (reception completed 1) txi1 (transmit data empty 1) tei1 (transmission end 1) sci channel 1 84 85 86 87 h'0150 h'0154 h'0158 h'015c iprk6 to 4 eri2 (receive error 2) rxi2 (reception completed 2) txi2 (transmit data empty 2) tei2 (transmission end 2) sci channel 2 * 2 88 89 90 91 h'0160 h'0164 h'0168 h'016c iprk2 to 0 eri3 (receive error 3) rxi3 (reception completed 3) txi3 (transmit data empty 3) tei3 (transmission end 3) sci channel 3 120 121 122 123 h'01e0 h'01e4 h'01e8 h'01ec ipro6 to 4 low notes: 1. lower 16 bits of the start address. 2. h8s/2237 series only. origin of interrupt source
108 5.4 interrupt operation 5.4.1 interrupt control modes and interrupt operation interrupt operations in the h8s/2237 series and h8s/2227 series differ depending on the interrupt control mode. nmi interrupts are accepted at all times except in the reset state and the hardware standby state. in the case of irq interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. clearing an enable bit to 0 disables the corresponding interrupt request. interrupt sources for which the enable bits are set to 1 are controlled by the interrupt controller. table 5-5 shows the interrupt control modes. the interrupt controller performs interrupt control according to the interrupt control mode set by the intm1 and intm0 bits in syscr, the priorities set in ipr, and the masking state indicated by the i and ui bits in the cpu? ccr, and bits i2 to i0 in exr. table 5-5 interrupt control modes interrupt syscr priority setting interrupt control mode intm1 intm0 registers mask bits description 0 0 0 i interrupt mask control is performed by the i bit. 1 setting prohibited 2 1 0 ipr i2 to i0 8-level interrupt mask control is performed by bits i2 to i0. 8 priority levels can be set with ipr. 1 setting prohibited
109 figure 5-4 shows a block diagram of the priority decision circuit. interrupt acceptance control 8-level mask control default priority determination vector number interrupt control mode 2 ipr interrupt source i2 to i0 interrupt control mode 0 i figure 5-4 block diagram of interrupt control operation (1) interrupt acceptance control in interrupt control mode 0, interrupt acceptance is controlled by the i bit in ccr. table 5-6 shows the interrupts selected in each interrupt control mode. table 5-6 interrupts selected in each interrupt control mode (1) interrupt mask bits interrupt control mode i selected interrupts 0 0 all interrupts 1 nmi interrupts 2 * all interrupts legend * : don't care
110 (2) 8-level control in interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (ipr). the interrupt source selected is the interrupt with the highest priority level, and whose priority level set in ipr is higher than the mask level. table 5-7 interrupts selected in each interrupt control mode (2) interrupt control mode selected interrupts 0 all interrupts 2 highest-priority-level (ipr) interrupt whose priority level is greater than the mask level (ipr > i2 to i0). (3) default priority determination when an interrupt is selected by 8-level control, its priority is determined and a vector number is generated. if the same value is set for ipr, acceptance of multiple interrupts is enabled, and so only the interrupt source with the highest priority according to the preset default priorities is selected and has a vector number generated. interrupt sources with a lower priority than the accepted interrupt source are held pending. table 5-8 shows operations and control signal functions in each interrupt control mode. table 5-8 operations and control signal functions in each interrupt control mode setting interrupt acceptance control 8-level control t intm1 intm0 i i2 to i0 ipr (trace) 000 im x * 2 210 x * 1 im pr t legend : interrupt operation control performed x : no operation. (all interrupts enabled) im : used as interrupt mask bit pr : sets priority. : not used. notes: 1. set to 1 when interrupt is accepted. 2. keep the initial setting. interrupt control mode default priority determination
111 5.4.2 interrupt control mode 0 enabling and disabling of irq interrupts and on-chip supporting module interrupts can be set by means of the i bit in the cpu? ccr. interrupts are enabled when the i bit is cleared to 0, and disabled when set to 1. figure 5-5 shows a flowchart of the interrupt acceptance operation in this case. [1] if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] the i bit is then referenced. if the i bit is cleared to 0, the interrupt request is accepted. if the i bit is set to 1, only an nmi interrupt is accepted, and other interrupt requests are held pending. [3] interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to the priority system is accepted, and other interrupt requests are held pending. [4] when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] the pc and ccr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] next, the i bit in ccr is set to 1. this masks all interrupts except nmi. [7] a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.
112 program execution status interrupt generated? nmi irq0 irq1 tei3 i=0 save pc and ccr i ? 1 read vector address branch to interrupt handling routine yes no yes yes yes no no no yes yes no hold pending figure 5-5 flowchart of procedure up to interrupt acceptance in interruptcontrolmode0
113 5.4.3 interrupt control mode 2 eight-level masking is implemented for irq interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits i2 to i0 of exr in the cpu with ipr. figure 5-6 shows a flowchart of the interrupt acceptance operation in this case. [1] if an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller. [2] when interrupt requests are sent to the interrupt controller, the interrupt with the highest priority according to the interrupt priority levels set in ipr is selected, and lower-priority interrupt requests are held pending. if a number of interrupt requests with the same priority are generated at the same time, the interrupt request with the highest priority according to the priority system shown in table 5-4 is selected. [3] next, the priority of the selected interrupt request is compared with the interrupt mask level set in exr. an interrupt request with a priority no higher than the mask level set at that time is held pending, and only an interrupt request with a priority higher than the interrupt mask level is accepted. [4] when an interrupt request is accepted, interrupt exception handling starts after execution of the current instruction has been completed. [5] the pc, ccr, and exr are saved to the stack area by interrupt exception handling. the pc saved on the stack shows the address of the first instruction to be executed after returning from the interrupt handling routine. [6] the t bit in exr is cleared to 0. the interrupt mask level is rewritten with the priority level of the accepted interrupt. if the accepted interrupt is nmi, the interrupt mask level is set to h'7. [7] a vector address is generated for the accepted interrupt, and execution of the interrupt handling routine starts at the address indicated by the contents of that vector address.
114 yes program execution status interrupt generated? nmi level 6 interrupt? mask level 5 or below? level 7 interrupt? mask level 6 or below? save pc, ccr, and exr clear t bit to 0 update mask level read vector address branch to interrupt handling routine hold pending level 1 interrupt? mask level 0? yes yes no yes yes yes no yes yes no no no no no no figure 5-6 flowchart of procedure up to interrupt acceptance in interrupt?ontrol?ode?
115 5.4.4 interrupt exception handling sequence figure 5-7 shows the interrupt exception handling sequence. the example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. (14) (12) (10) (8) (6) (4) (2) (1) (5) (7) (9) (11) (13) interrupt service routine instruction prefetch internal operation vector fetch stack instruction prefetch internal operation interrupt acceptance interrupt level determination wait for end of instruction interrupt request signal internal address bus internal read signal internal write signal internal data us (3) (1) (2) (4) (3) (5) (7) instruction prefetch address (not executed. this is the contents of the saved pc, the return address.) instruction code (not executed.) instruction prefetch address (not executed.) sp-2 sp-4 saved pc and saved ccr vector address interrupt handling routine start address (vector address contents) interrupt handling routine start address ((13) = (10) (12)) first instruction of interrupt handling routine (6) (8) (9) (11) (10) (12) (13) (14) figure 5-7 interrupt exception handling
116 5.4.5 interrupt response times the h8s/2237 series and h8s/2227 series are capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip rom and the stack area in on-chip ram, enabling high-speed processing. table 5-9 shows interrupt response times - the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. the execution status symbols used in table 5-9 are explained in table 5-10. table 5-9 interrupt response times normal mode * 5 advanced mode no. execution status intm1 = 0 intm1 = 1 intm1 = 0 intm1 = 1 1 interrupt priority determination * 1 33 33 2 number of wait states until executing instruction ends * 2 1 to 19+2? i 1 to 19+2? i 1 to 19+2? i 1 to 19+2? i 3 pc, ccr, exr stack save 2? k 3? k 2? k 3? k 4 vector fetch s i s i 2? i 2? i 5 instruction fetch * 3 2? i 2? i 2? i 2? i 6 internal processing * 4 22 22 total (using on-chip memory) 11 to 31 12 to 32 12 to 32 13 to 33 notes: 1. two states in case of internal interrupt. 2. refers to mulxs and divxs instructions. 3. prefetch after interrupt acceptance and interrupt handling routine prefetch. 4. internal processing after interrupt acceptance and internal processing after vector fetch. 5. not available in the h8s/2237 series and h8s/2227 series.
117 table 5-10 number of states in interrupt handling routine execution statuses object of access external device 8 bit bus 16 bit bus symbol internal memory 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 6+2m 2 3+m branch address read s j stack manipulation s k legend m : number of wait states in an external device access. 5.5 usage notes 5.5.1 contention between interrupt generation and disabling when an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction. in other words, when an interrupt enable bit is cleared to 0 by an instruction such as bclr or mov, if an interrupt is generated during execution of the instruction, the interrupt concerned will still be enabled on completion of the instruction, and so interrupt exception handling for that interrupt will be executed on completion of the instruction. however, if there is an interrupt request of higher priority than that interrupt, interrupt exception handling will be executed for the higher-priority interrupt, and the lower-priority interrupt will be ignored. the same also applies when an interrupt source flag is cleared to 0. figure 5-8 shows and example in which the cmiea bit in 8-bit timer tcr is cleared to 0.
118 internal address bus internal write signal cmiea cmfa cmia interrupt signal tcr write cycle by cpu cmia exception handling tcr address figure 5-8 contention between interrupt generation and disabling the above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while the interrupt is masked. 5.5.2 instructions that disable interrupts instructions that disable interrupts are ldc, andc, orc, and xorc. after any of these instructions is executed, all interrupts including nmi are disabled and the next instruction is always executed. when the i bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.3 times when interrupts are disabled there are times when interrupt acceptance is disabled by the interrupt controller. the interrupt controller disables interrupt acceptance for a 3-state period after the cpu has updated the mask level with an ldc, andc, orc, or xorc instruction. 5.5.4 interrupts during execution of eepmov instruction interrupt operation differs between the eepmov.b instruction and the eepmov.w instruction.
119 with the eepmov.b instruction, an interrupt request (including nmi) issued during the transfer is not accepted until the move is completed. with the eepmov.w instruction, if an interrupt request is issued during the transfer, interrupt exception handling starts at a break in the transfer cycle. the pc value saved on the stack in this case is the address of the next instruction. therefore, if an interrupt is generated during execution of an eepmov.w instruction, the following coding should be used. l1: eepmov.w mov.w r4,r4 bne l1 5.6 dtc activation by interrupt 5.6.1 overview the dtc can be activated by an interrupt. in this case, the following options are available: interrupt request to cpu activation request to dtc selection of a number of the above for details of interrupt requests that can be used with to activate the dtc, see section 8, data transfer controller. 5.6.2 block diagram figure 5-9 shows a block diagram of the dtc interrupt controller.
120 selection circuit dtcer dtvecr control logic determination of priority cpu dtc dtc activation request vector number clear signal cpu interrupt request vector number select signal interrupt request interrupt source clear signal irq interrupt on-chip supporting module clear signal interrupt controller i, i2 to i0 swdte clear signal figure 5-9 interrupt control for dtc 5.6.3 operation the interrupt controller has three main functions in dtc control. (1) selection of interrupt source: interrupt sources can be specified as dtc activation requests or cpu interrupt requests by means of the dtce bit of dtcea to dtcef in the dtc. after a dtc data transfer, the dtce bit can be cleared to 0 and an interrupt request sent to the cpu in accordance with the specification of the disel bit of mrb in the dtc. when the dtc has performed the specified number of data transfers and the transfer counter value is zero, the dtce bit is cleared to 0 and an interrupt request is sent to the cpu after the dtc data transfer. (2) determination of priority: the dtc activation source is selected in accordance with the default priority order, and is not affected by mask or priority levels. see section 8.3.3, dtc vector table, for the respective priorities. (3) operation order: if the same interrupt is selected as a dtc activation source and a cpu interrupt source, the dtc data transfer is performed first, followed by cpu interrupt exception handling. table 5-11 summarizes interrupt source selection and interrupt source clearance control according to the settings of the dtce bit of dtcea to dtcef and dtcei in the dtc, and the disel bit of mrb in the dtc.
121 table 5-11 interrupt source selection and clearing control settings dtc interrupt source selection/clearing control dtce disel dtc cpu 0 * x d 10 d x 1 d legend d : the relevant interrupt is used. interrupt source clearing is performed. (the cpu should clear the source flag in the interrupt handling routine.) : the relevant interrupt is used. the interrupt source is not cleared. x : the relevant bit cannot be used. * : don? care (4) notes on use: sci and a/d converter interrupt sources are cleared when the dtc reads or writes to the prescribed register, and are not dependent upon the disel bit.
122
123 section 6 pc break controller (pbc) 6.1 overview the pc break controller (pbc) provides functions that simplify program debugging. using these functions, it is easy to create a self-monitoring debugger, enabling programs to be debugged with the chip alone, without using an in-circuit emulator. four break conditions can be set in the pbc: instruction fetch, data read, data write, and data read/write. 6.1.1 features the pc break controller has the following features: two break channels (a and b) the following can be set as break compare conditions: ? 24 address bits bit masking possible ? bus cycle instruction fetch data access: data read, data write, data read/write ? bus master either cpu or cpu/dtc can be selected the timing of pc break exception handling after the occurrence of a break condition is as follows: ? immediately before execution of the instruction fetched at the set address (instruction fetch) ? immediately after execution of the instruction that accesses data at the set address (data access) module stop mode can be set ? the initial setting is for pbc operation to be halted. register access is enabled by clearing module stop mode.
124 6.1.2 block diagram figure 6-1 shows a block diagram of the pc break controller. output control mask control output control match signal pc break interrupt match signal mask control bara bcra barb bcrb comparator control logic comparator control logic internal address access status figure 6-1 block diagram of pc break controller
125 6.1.3 register configuration table 6-1 shows the pc break controller registers. table 6-1 pc break controller registers initial value name abbreviation r/w power-on manual address * 1 break address register a bara r/w h'000000 retained h'fe00 break address register b barb r/w h'000000 retained h'fe04 break control register a bcra r(w) * 2 h'00 retained h'fe08 break control register b bcrb r(w) * 2 h'00 retained h'fe09 module stop control register c mstpcrc r/w h'ff retained h'fdea notes: 1. lower 16 bits of the address. 2. only 0 can be written, to clear the flag. 6.2 register descriptions 6.2.1 break address register a (bara) bit initial value read/write 31 unde- fined 24 unde- fined r/w baa 23 23 0 r/w baa 22 22 0 r/w baa 21 21 0 r/w baa 20 20 0 r/w baa 19 19 0 r/w baa 18 18 0 r/w baa 17 17 0 r/w baa 16 16 0 r/w 0 baa 7 7 r/w 0 baa 6 6 r/w 0 baa 5 5 r/w 0 baa 4 4 r/w 0 baa 3 3 r/w 0 baa 2 2 r/w 0 baa 1 1 r/w 0 baa 0 0 ?? ?? ?? ?? ?? ?? ?? ?? bara is a 32-bit readable/writable register that specifies the channel a break address. baa23 to baa0 are initialized to h'000000 by a power-on reset and in hardware standby mode. bits 31 to 24?eserved: these bits return an undefined value if read, and cannot be modified. bits 23 to 0?reak address a23 to a0 (baa23 to baa0): these bits hold the channel a pc break address.
126 6.2.2 break address register b (barb) barb is the channel b break address register. the bit configuration is the same as for bara. 6.2.3 break control register a (bcra) bit note: only 0 can be written to bit 7, to clear this flag. initial value read/write r(w)* 0 cmfa 7 r/w 0 cda 6 r/w 0 bamra2 5 r/w 0 bamra1 4 r/w 0 bamra0 3 r/w 0 csela1 2 r/w 0 csela0 1 r/w 0 biea 0 bcra is an 8-bit readable/writable register that controls channel a pc breaks. bcra (1) selects the break condition bus master, (2) specifies bits subject to address comparison masking, and (3) specifies whether the break condition is applied to an instruction fetch or a data access. it also contains a condition match flag. bcra is initialized to h'00 by a power-on reset and in hardware standby mode. bit 7?ondition match flag a (cmfa): set to 1 when a break condition set for channel a is satisfied. this flag is not cleared to 0. bit 7 cmfa description [clearing condition] when 0 is written to cmfa after reading cmfa = 1 (initial value) [setting condition] when a condition set for channel a is satisfied bit 6?pu cycle/dtc cycle select a (cda): selects the channel a break condition bus master. bit 6 cda description 0 pc break is performed when cpu is bus master (initial value) 1 pc break is performed when cpu or dtc is bus master
127 bits 5 to 3?reak address mask register a2 to a0 (bamra2 to bamra0): these bits specify which bits of the break address (baa23 to baa0) set in bara are to be masked. bit 5 bit 4 bit 3 bamra2 bamra1 bamra0 description 0 0 0 all bara bits are unmasked and included in break conditions (initial value) 1 baa0 (lowest bit) is masked, and not included in break conditions 1 0 baa1 to 0 (lower 2 bits) are masked, and not included in break conditions 1 baa2 to 0 (lower 3 bits) are masked, and not included in break conditions 1 0 0 baa3 to 0 (lower 4 bits) are masked, and not included in break conditions 1 baa7 to 0 (lower 8 bits) are masked, and not included in break conditions 1 0 baa11 to 0 (lower 12 bits) are masked, and not included in break conditions 1 baa15 to 0 (lower 16 bits) are masked, and not included in break conditions bits 2 to 1?reak condition select a (csela1 to csela0): these bits selection an instruction fetch, data read, data write, or data read/write cycle as the channel a break condition. bit 2 bit 1 csela1 csela0 description 0 0 instruction fetch is used as break condition (initial value) 1 data read cycle is used as break condition 1 0 data write cycle is used as break condition 1 data read/write cycle is used as break condition bits 0?reak interrupt enable a (biea): enables or disables channel a pc break interrupts. bit 0 biea description 0 pc break interrupts are disabled (initial value) 1 pc break interrupts are enabled
128 6.2.4 break control register b (bcrb) bcrb is the channel b break control register. the bit configuration is the same as for bcra. 6.2.5 module stop control register c (mstpcrc) 7 mstpc7 1 r/w bit initial value read/write 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w 0 mstpc0 1 r/w mstpcrc is an 8-bit readable/writable register that performs module stop mode control. when the mstpc4 bit is set to 1, pc break controller operation is stopped at the end of the bus cycle, and module stop mode is entered. register read/write accesses are not possible in module stop mode. for details, see section 20.5, module stop mode. mstpcrc is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 4?odule stop (mstpc4): specifies the pc break controller module stop mode. bit 4 mstpc4 description 0 pc break controller module stop mode is cleared 1 pc break controller module stop mode is set (initial value)
129 6.3 operation the operation flow from break condition setting to pc break interrupt exception handling is shown in sections 6.3.1 and 6.3.2, taking the example of channel a. 6.3.1 pc break interrupt due to instruction fetch (1) initial settings ? set the break address in bara. for a pc break caused by an instruction fetch, set the address of the first instruction byte as the break address. ? set the break conditions in bcra. bcra bit 6 (cda): with a pc break caused by an instruction fetch, the bus master must be the cpu. set 0 to select the cpu. bcra bits 5 to 3 (bama2 to 0): set the address bits to be masked. bcra bits 2 to 1 (csela1 to 0): set 00 to specify an instruction fetch as the break condition. bcra bit 0 (biea): set to 1 to enable break interrupts. (2) satisfaction of break condition ? when the instruction at the set address is fetched, a pc break request is generated immediately before execution of the fetched instruction, and the condition match flag (cmfa) is set. (3) interrupt handling ? after priority determination by the interrupt controller, pc break interrupt exception handling is started. 6.3.2 pc break interrupt due to data access (1) initial settings ? set the break address in bara. for a pc break caused by a data access, set the target rom, ram, i/o, or external address space address as the break address. stack operations and branch address reads are included in data accesses. ? set the break conditions in bcra. bcra bit 6 (cda): select the bus master. bcra bits 5 to 3 (bama2 to 0): set the address bits to be masked. bcra bits 2 to 1 (csela1 to 0): set 01, 10, or 11 to specify data access as the break condition. bcra bit 0 (biea): set to 1 to enable break interrupts.
130 (2) satisfaction of break condition ? after execution of the instruction that performs a data access on the set address, a pc break request is generated and the condition match flag (cmfa) is set. (3) interrupt handling ? after priority determination by the interrupt controller, pc break interrupt exception handling is started. 6.3.3 notes on pc break interrupt handling (1) the pc break interrupt is shared by channels a and b. the channel from which the request was issued must be determined by the interrupt handler. (2) the cmfa and cmfb flags are not cleared to 0, so 0 must be written to cmfa or cmfb after first reading the flag while it is set to 1. if the flag is left set to 1, another interrupt will be requested after interrupt handling ends. (3) a pc break interrupt generated when the dtc is the bus master is accepted after the bus has been transferred to the cpu by the bus controller. 6.3.4 operation in transitions to power-down modes the operation when a pc break interrupt is set for an instruction fetch at the address after a sleep instruction is shown below. (1) when the sleep instruction causes a transition from high-speed (medium-speed) mode to sleep mode, or from subactive mode to subsleep mode: after execution of the sleep instruction, a transition is not made to sleep mode or subsleep mode, and pc break interrupt handling is executed. after execution of pc break interrupt handling, the instruction at the address after the sleep instruction is executed (figure 6-2 (a)). (2) when the sleep instruction causes a transition from high-speed (medium-speed) mode to subactive mode: after execution of the sleep instruction, a transition is made to subactive mode via direct transition exception handling. after the transition, pc break interrupt handling is executed, then the instruction at the address after the sleep instruction is executed (figure 6-2 (b)). (3) when the sleep instruction causes a transition from subactive mode to high-speed (medium- speed) mode:
131 after execution of the sleep instruction, and following the clock oscillation settling time, a transition is made to high-speed (medium-speed) mode via direct transition exception handling. after the transition, pc break interrupt handling is executed, then the instruction at the address after the sleep instruction is executed (figure 6-2 (c)). (4) when the sleep instruction causes a transition to software standby mode or watch mode: after execution of the sleep instruction, a transition is made to the respective mode, and pc break interrupt handling is not executed. however, the cmfa or cmfb flag is set (figure 6-2 (d)). sleep instruction execution high-speed (medium-speed) mode sleep instruction execution subactive mode system clock subclock direct transition exception handling pc break exception handling execution of instruction after sleep instruction subclock system clock, oscillation settling time sleep instruction execution transition to respective mode direct transition exception handling pc break exception handling execution of instruction after sleep instruction pc break exception handling execution of instruction after sleep instruction (a) (b) (c) (d) sleep instruction execution figure 6-2 operation in power-down mode transitions 6.3.5 pc break operation in continuous data transfer if a pc break interrupt is generated when the following operations are being performed, exception handling is executed on completion of the specified transfer. (1) when a pc break interrupt is generated at the transfer address of an eepmov.b instruction: pc break exception handling is executed after all data transfers have been completed and the eepmov.b instruction has ended. (2) when a pc break interrupt is generated at a dtc transfer address: pc break exception handling is executed after the dtc has completed the specified number of data transfers, or after data for which the disel bit is set to 1 has been transferred.
132 6.3.6 when instruction execution is delayed by one state caution is required in the following cases, as instruction execution is one state later than usual. (1) when the pbc is enabled (i.e. when the break interrupt enable bit is set to 1), execution of a one-word branch instruction (bcc d:8, bsr, jsr, jmp, trapa, rte, or rts) located in on- chip rom or ram is always delayed by one state. (2) when break interruption by instruction fetch is set, the set address indicates on-chip rom or ram space, and that address is used for data access, the instruction that executes the data access is one state later than in normal operation. (3) when break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction has one of the addressing modes shown below, and that address indicates on-chip rom or ram, the instruction will be one state later than in normal operation. @ern, @(d:16,ern), @(d:32,ern), @-ern/ern+, @aa:8, @aa:24, @aa:32, @(d:8,pc), @(d:16,pc), @@aa:8 (4) when break interruption by instruction fetch is set and a break interrupt is generated, if the executing instruction immediately preceding the set instruction is nop or sleep, or has #xx,rn as its addressing mode, and that instruction is located in on-chip rom or ram, the instruction will be one state later than in normal operation.
133 6.3.7 additional notes (1) when a pc break is set for an instruction fetch at the address following a bsr, jsr, jmp, trapa, rte, or rts instruction: even if the instruction at the address following a bsr, jsr, jmp, trapa, rte, or rts instruction is fetched, it is not executed, and so a pc break interrupt is not generated by the instruction fetch at the next address. (2) when the i bit is set by an ldc, andc, orc, or xorc instruction, a pc break interrupt becomes valid two states after the end of the executing instruction. if a pc break interrupt is set for the instruction following one of these instructions, since interrupts, including nmi, are disabled for a 3-state period in the case of ldc, andc, orc, and xorc, the next instruction is always executed. for details, see section 5, interrupt controller. (3) when a pc break is set for an instruction fetch at the address following a bcc instruction: a pc break interrupt is generated if the instruction at the next address is executed in accordance with the branch condition, but is not generated if the instruction at the next address is not executed. (4) when a pc break is set for an instruction fetch at the branch destination address of a bcc instruction: a pc break interrupt is generated if the instruction at the branch destination is executed in accordance with the branch condition, but is not generated if the instruction at the branch destination is not executed.
134
135 section 7 bus controller 7.1 overview the h8s/2237 series and h8s/2227 series have a built-in bus controller (bsc) that manages the external address space divided into eight areas. the bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily. the bus controller also has a bus arbitration function, and controls the operation of the internal bus masters: the cpu and data transfer controller (dtc). 7.1.1 features the features of the bus controller are listed below. ? manages external address space in area units ? manages the external space as 8 areas of 2-mbytes ? bus specifications can be set independently for each area ? burst rom interface can be set ? basic bus interface ? chip select ( cs0 to cs7 ) can be output for areas 0 to 7 ? 8-bit access or 16-bit access can be selected for each area ? 2-state access or 3-state access can be selected for each area ? program wait states can be inserted for each area ? burst rom interface ? burst rom interface can be set for area 0 ? choice of 1- or 2-state burst access ? idle cycle insertion ? an idle cycle can be inserted in case of an external read cycle between different areas ? an idle cycle can be inserted in case of an external write cycle immediately after an external read cycle ? bus arbitration function ? includes a bus arbiter that arbitrates bus mastership among the cpu and dtc ? other features ? external bus release function
136 7.1.2 block diagram figure 7-1 shows a block diagram of the bus controller. area decoder bus controller abwcr astcr bcrh bcrl internal address bus cs0 to cs7 external bus control signals breq back internal control signals wait controller wcrh wcrl bus mode signal bus arbiter cpu bus request signal dtc bus request signal cpu bus acknowledge signal dtc bus acknowledge signal wait internal data bus figure 7-1 block diagram of bus controller
137 7.1.3 pin configuration table 7-1 summarizes the pins of the bus controller. table 7-1 bus controller pins name symbol i/o function address strobe as output strobe signal indicating that address output on address bus is enabled. read rd output strobe signal indicating that external space is being read. high write hwr output strobe signal indicating that external space is to be written, and upper half (d15 to d8) of data bus is enabled. low write lwr output strobe signal indicating that external space is to be written, and lower half (d7 to d0) of data bus is enabled. chip select 0 to 7 cs0 to cs7 output strobe signal indicating that areas 0 to 7 are selected. wait wait input wait request signal when accessing external 3-state access space. bus request breq input request signal that releases bus to external device. bus request acknowledge back output acknowledge signal indicating that bus has been released.
138 7.1.4 register configuration table 7-2 summarizes the registers of the bus controller. table 7-2 bus controller registers initial value name abbreviation r/w power-on reset manual reset address * 1 bus width control register abwcr r/w h'ff/h'00 * 2 retained h'fed0 access state control register astcr r/w h'ff retained h'fed1 wait control register h wcrh r/w h'ff retained h'fed2 wait control register l wcrl r/w h'ff retained h'fed3 bus control register h bcrh r/w h'd0 retained h'fed4 bus control register l bcrl r/w h'08 retained h'fed5 pin function control register pfcr r/w h'0d/h'00 * 3 retained h'fdeb notes: 1. lower 16 bits of the address. 2. determined by the mcu operating mode. 3. initialized to h'0d in modes 4 and 5, and to h'00 in modes 6 and 7.
139 7.2 register descriptions 7.2.1 bus width control register (abwcr) 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w bit : initial value : modes 5 to 7 mode 4 : rw initial value : : rw abwcr is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access. abwcr sets the data bus width for the external memory space. the bus width for on-chip memory and internal i/o registers is fixed regardless of the settings in abwcr. after a power-on reset and in hardware standby mode, abwcr is initialized to h'ff in modes 5, 6, 7, and to h'00 in mode 4. it is not initialized by a manual reset or in software standby mode. bits 7 to 0?rea 7 to 0 bus width control (abw7 to abw0): these bits select whether the corresponding area is to be designated for 8-bit access or 16-bit access. bit n abwn description 0 area n is designated for 16-bit access 1 area n is designated for 8-bit access (n = 7 to 0)
140 7.2.2 access state control register (astcr) 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w bit initial value r/w : : : astcr is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. astcr sets the number of access states for the external memory space. the number of access states for on-chip memory and internal i/o registers is fixed regardless of the settings in astcr. astcr is initialized to h'ff by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bits 7 to 0?rea 7 to 0 access state control (ast7 to ast0): these bits select whether the corresponding area is to be designated as a 2-state access space or a 3-state access space. wait state insertion is enabled or disabled at the same time. bit n astn description 0 area n is designated for 2-state access wait state insertion in area n external space is disabled 1 area n is designated for 3-state access (initial value) wait state insertion in area n external space is enabled (n = 7 to 0)
141 7.2.3 wait control registers h and l (wcrh, wcrl) wcrh and wcrl are 8-bit readable/writable registers that select the number of program wait states for each area. program waits are not inserted in the case of on-chip memory or internal i/o registers. wcrh and wcrl are initialized to h'ff by a power-on reset and in hardware standby mode. they are not initialized by a manual reset or in software standby mode. (1) wcrh 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 0 w40 1 r/w 2 w50 1 r/w 1 w41 1 r/w bit initial value r/w : : : bits 7 and 6?rea 7 wait control 1 and 0 (w71, w70): these bits select the number of program wait states when area 7 in external space is accessed while the ast7 bit in astcr is set to 1. bit 7 bit 6 w71 w70 description 0 0 program wait not inserted when external space area 7 is accessed 1 1 program wait state inserted when external space area 7 is accessed 1 0 2 program wait states inserted when external space area 7 is accessed 1 3 program wait states inserted when external space area 7 is accessed (initial value)
142 bits 5 and 4?rea 6 wait control 1 and 0 (w61, w60): these bits select the number of program wait states when area 6 in external space is accessed while the ast6 bit in astcr is set to 1. bit 5 bit 4 w61 w60 description 0 0 program wait not inserted when external space area 6 is accessed 1 1 program wait state inserted when external space area 6 is accessed 1 0 2 program wait states inserted when external space area 6 is accessed 1 3 program wait states inserted when external space area 6 is accessed (initial value) bits 3 and 2?rea 5 wait control 1 and 0 (w51, w50): these bits select the number of program wait states when area 5 in external space is accessed while the ast5 bit in astcr is set to 1. bit 3 bit 2 w51 w50 description 0 0 program wait not inserted when external space area 5 is accessed 1 1 program wait state inserted when external space area 5 is accessed 1 0 2 program wait states inserted when external space area 5 is accessed 1 3 program wait states inserted when external space area 5 is accessed (initial value) bits 1 and 0?rea 4 wait control 1 and 0 (w41, w40): these bits select the number of program wait states when area 4 in external space is accessed while the ast4 bit in astcr is set to 1. bit 1 bit 0 w41 w40 description 0 0 program wait not inserted when external space area 4 is accessed 1 1 program wait state inserted when external space area 4 is accessed 1 0 2 program wait states inserted when external space area 4 is accessed 1 3 program wait states inserted when external space area 4 is accessed (initial value)
143 (2) wcrl 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 0 w00 1 r/w 2 w10 1 r/w 1 w01 1 r/w bit initial value r/w : : : bits 7 and 6?rea 3 wait control 1 and 0 (w31, w30): these bits select the number of program wait states when area 3 in external space is accessed while the ast3 bit in astcr is set to 1. bit 7 bit 6 w31 w30 description 0 0 program wait not inserted when external space area 3 is accessed 1 1 program wait state inserted when external space area 3 is accessed 1 0 2 program wait states inserted when external space area 3 is accessed 1 3 program wait states inserted when external space area 3 is accessed (initial value) bits 5 and 4?rea 2 wait control 1 and 0 (w21, w20): these bits select the number of program wait states when area 2 in external space is accessed while the ast2 bit in astcr is set to 1. bit 5 bit 4 w21 w20 description 0 0 program wait not inserted when external space area 2 is accessed 1 1 program wait state inserted when external space area 2 is accessed 1 0 2 program wait states inserted when external space area 2 is accessed 1 3 program wait states inserted when external space area 2 is accessed (initial value)
144 bits 3 and 2?rea 1 wait control 1 and 0 (w11, w10): these bits select the number of program wait states when area 1 in external space is accessed while the ast1 bit in astcr is set to 1. bit 3 bit 2 w11 w10 description 0 0 program wait not inserted when external space area 1 is accessed 1 1 program wait state inserted when external space area 1 is accessed 1 0 2 program wait states inserted when external space area 1 is accessed 1 3 program wait states inserted when external space area 1 is accessed (initial value) bits 1 and 0?rea 0 wait control 1 and 0 (w01, w00): these bits select the number of program wait states when area 0 in external space is accessed while the ast0 bit in astcr is set to 1. bit 1 bit 0 w01 w00 description 0 0 program wait not inserted when external space area 0 is accessed 1 1 program wait state inserted when external space area 0 is accessed 1 0 2 program wait states inserted when external space area 0 is accessed 1 3 program wait states inserted when external space area 0 is accessed (initial value)
145 7.2.4 bus control register h (bcrh) 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : bcrh is an 8-bit readable/writable register that selects enabling or disabling of idle cycle insertion, and the memory interface for area 0. bcrh is initialized to h'd0 by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bit 7?dle cycle insert 1 (icis1): selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas. bit 7 icis1 description 0 idle cycle not inserted in case of successive external read cycles in different areas 1 idle cycle inserted in case of successive external read cycles in different areas (initial value) bit 6?dle cycle insert 0 (icis0): selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read and external write cycles are performed . bit 6 icis0 description 0 idle cycle not inserted in case of successive external read and external write cycles 1 idle cycle inserted in case of successive external read and external write cycles (initial value) bit 5?urst rom enable (brstrm): selects whether area 0 is used as a burst rom interface. bit 5 brstrm description 0 area 0 is basic bus interface (initial value) 1 area 0 is burst rom interface
146 bit 4?urst cycle select 1 (brsts1): selects the number of burst cycles for the burst rom interface. bit 4 brsts1 description 0 burst cycle comprises 1 state 1 burst cycle comprises 2 states (initial value) bit 3?urst cycle select 0 (brsts0): selects the number of words that can be accessed in a burst rom interface burst access. bit 3 brsts0 description 0 max. 4 words in burst access (initial value) 1 max. 8 words in burst access bits 2 to 0?eserved: only 0 should be written to these bits.
147 7.2.5 bus control register l (bcrl) 7 brle 0 r/w 6 0 r/w 5 0 4 0 r/w 3 1 r/w 0 waite 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : bcrl is an 8-bit readable/writable register that performs selection of the external bus-released state protocol, and enabling or disabling of wait pin input. bcrl is initialized to h'08 by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bit 7?us release enable (brle): enables or disables external bus release. bit 7 brle description 0 external bus release is disabled. breq and back can be used as i/o ports. (initial value) 1 external bus release is enabled. bit 6?eserved: only 0 should be written to this bit. bit 5?eserved: this bit cannot be modified and is always read as 0. bit 4?eserved: only 0 should be written to this bit. bit 3?eserved: only 1 should be written to this bit. bits 2 and 1?eserved: only 0 should be written to these bits. bit 0?ait pin enable (waite): selects enabling or disabling of wait input by the wait pin. bit 0 waite description 0 wait input by wait pin disabled. wait pin can be used as i/o port. (initial value) 1 wait input by wait pin enabled
148 7.2.6 pin function control register (pfcr) 7 0 0 r/w 6 0 0 r/w 5 buzze 0 0 r/w 4 0 0 r/w 3 ae3 1 0 r/w 0 ae0 1 0 r/w 2 ae2 1 0 r/w 1 ae1 0 0 r/w bit modes 4 and 5 initial value modes 6 and 7 initial value read/write pfcr is an 8-bit readable/writable register that performs address output control in external expanded mode. pfcr is initialized to h'0d (modes 4 and 5) or h'00 (modes 6 and 7) by a power-on reset and in hardware standby mode. it retains its previous state in a manual reset and in software standby mode. bits 7 and 6?eserved: only 0 should be written to these bits. bit 5?uzz output enable (buzze): enables or disables buzz output from the pf1 pin. the wdt1 input clock selected with bits pss and cks2 to cks0 is output as the buzz signal. for details of buzz output, see section 12.2.4, pin function control register (pfcr). bit 5 buzze description 0 functions as pf1 i/o pin (initial value) 1 functions as buzz output pin bit 4?eserved: only 0 should be written to this bit. bits 3 to 0?ddress output enable 3 to 0 (ae3?e0): these bits select enabling or disabling of address outputs a8 to a23 in romless expanded mode and modes with rom. when a pin is enabled for address output, the address is output regardless of the corresponding ddr setting. when a pin is disabled for address output, it becomes an output port when the corresponding ddr bit is set to 1.
149 bit 3 bit 2 bit 1 bit 0 ae3 ae2 ae1 ae0 description 0000a8 to a23 address output disabled (initial value * 1 ) 1 a8 address output enabled; a9 to a23 address output disabled 1 0 a8, a9 address output enabled; a10 to a23 address output disabled 1 a8 to a10 address output enabled; a11 to a23 address output disabled 1 0 0 a8 to a11 address output enabled; a12 to a23 address output disabled 1 a8 to a12 address output enabled; a13 to a23 address output disabled 1 0 a8 to a13 address output enabled; a14 to a23 address output disabled 1 a8 to a14 address output enabled; a15 to a23 address output disabled 1000a8 to a15 address output enabled; a16 to a23 address output disabled 1 a8 to a16 address output enabled; a17 to a23 address output disabled 1 0 a8 to a17 address output enabled; a18 to a23 address output disabled 1 a8 to a18 address output enabled; a19 to a23 address output disabled 1 0 0 a8 to a19 address output enabled; a20 to a23 address output disabled 1 a8 to a20 address output enabled; a21 to a23 address output disabled (initial value * 2 ) 1 0 a8 to a21 address output enabled; a22, a23 address output disabled 1 a8 to a23 address output enabled notes: 1. in expanded mode with rom, bits ae3 to ae0 are initialized to b'0000. in expanded mode with rom, address pins a0 to a7 are made address outputs by setting the corresponding ddr bits to 1. 2. in romless expanded mode, bits ae3 to ae0 are initialized to b'1101. in romless expanded mode, address pins a0 to a7 are always made address output.
150 7.3 overview of bus control 7.3.1 area partitioning in advanced mode, the bus controller partitions the 16 mbytes address space into eight areas, 0 to 7, in 2-mbyte units, and performs bus control for external space in area units. in normal mode*, it controls a 64-kbyte address space comprising part of area 0 (not available in the h8s/2237 series and h8s/2227 series). figure 7-2 shows an outline of the memory map. chip select signals ( cs0 to cs7 ) can be output for each area. area 0 (2mbytes) h'000000 h'ffffff (1) (2) h'0000 h'1fffff h'200000 area 1 (2mbytes) h'3fffff h'400000 area 2 (2mbytes) h'5fffff h'600000 area 3 (2mbytes) h'7fffff h'800000 area 4 (2mbytes) h'9fffff h'a00000 area 5 (2mbytes) h'bfffff h'c00000 area 6 (2mbytes) h'dfffff h'e00000 area 7 (2mbytes) h'ffff advanced mode normal mode * note: * not available in the h8s/2237 series and h8s/2227 series. figure 7-2 overview of area partitioning
151 7.3.2 bus specifications the external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. the bus width and number of access states for on-chip memory and internal i/o registers are fixed, and are not affected by the bus controller. (1) bus width: a bus width of 8 or 16 bits can be selected with abwcr. an area for which an 8-bit bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected functions as a16-bit access space. if all areas are designated for 8-bit access, 8-bit bus mode is set; if any area is designated for 16-bit access, 16-bit bus mode is set. when the burst rom interface is designated, 16-bit bus mode is always set. (2) number of access states: two or three access states can be selected with astcr. an area for which 2-state access is selected functions as a 2-state access space, and an area for which 3- state access is selected functions as a 3-state access space. with the burst rom interface, the number of access states may be determined without regard to astcr. when 2-state access space is designated, wait insertion is disabled. (3) number of program wait states: when 3-state access space is designated by astcr, the number of program wait states to be inserted automatically is selected with wcrh and wcrl. from 0 to 3 program wait states can be selected. table 7-3 shows the bus specifications for each basic bus interface area.
152 table 7-3 bus specifications for each area (basic bus interface) abwcr astcr wcrh, wcrl bus specifications (basic bus interface) abwn astn wn1 wn0 bus width access states program wait states 0016 2 0 100 3 0 11 10 2 13 108 2 0 100 3 0 11 10 2 13 7.3.3 memory interfaces the h8s/2237 series and h8s/2227 series memory interfaces comprise a basic bus interface that allows direct connection of rom, sram, and so on, and a burst rom interface (for area 0 only) that allows direct connection of burst rom. an area for which the basic bus interface is designated functions as normal space, and an area for which the burst rom interface is designated functions as burst rom space.
153 7.3.4 interface specifications for each area the initial state of each area is basic bus interface, 3-state access space. the initial bus width is selected according to the operating mode. the bus specifications described here cover basic items only, and the sections on each memory interface (7.4 and 7.5) should be referred to for further details. area 0: area 0 includes on-chip rom, and in rom-disabled expansion mode, all of area 0 is external space. in rom-enabled expansion mode, the space excluding on-chip rom is external space. when area 0 external space is accessed, the cs0 signal can be output. either basic bus interface or burst rom interface can be selected for area 0. areas 1 to 6: in external expansion mode, all of areas 1 to 6 is external space. when area 1 to 6 external space is accessed, the cs1 to cs6 pin signals respectively can be output. only the basic bus interface can be used for areas 1 to 6. area 7: area 7 includes the on-chip ram and internal i/o registers. in external expansion mode, the space excluding the on-chip ram and internal i/o registers is external space. the on-chip ram is enabled when the rame bit in the system control register (syscr) is set to 1; when the rame bit is cleared to 0, the on-chip ram is disabled and the corresponding space becomes external space. when area 7 external space is accessed, the cs7 signal can be output. only the basic bus interface can be used for the area 7.
154 7.3.5 chip select signals the h8s/2237 series and h8s/2227 series can output chip select signals ( cs0 to cs7 ) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. figure 7-3 shows an example of csn (n = 0 to 7) output timing. enabling or disabling of the csn signal is performed by setting the data direction register (ddr) for the port corresponding to the particular csn pin. in rom-disabled expansion mode, the cs0 pin is placed in the output state after a power-on reset. pins cs1 to cs7 are placed in the input state after a power-on reset, and so the corresponding ddr should be set to 1 when outputting signals cs1 to cs7 . in rom-enabled expansion mode, pins cs0 to cs7 are all placed in the input state after a power- on reset, and so the corresponding ddr should be set to 1 when outputting signals cs0 to cs7 . for details, see section 9, i/o ports. bus cycle t 1 t 2 t 3 area n external address address bus csn figure 7-3 csn signal output timing (n = 0 to 7)
155 7.4 basic bus interface 7.4.1 overview the basic bus interface enables direct connection of rom, sram, and so on. the bus specifications can be selected with abwcr, astcr, wcrh, and wcrl (see table 7- 3). 7.4.2 data size and data alignment data sizes for the cpu and other internal bus masters are byte, word, and longword. the bus controller has a data alignment function, and when accessing external space, controls whether the upper data bus (d15 to d8) or lower data bus (d7 to d0) is used according to the bus specifications for the area being accessed (8-bit access space or 16-bit access space) and the data size. 8-bit access space: figure 7-4 illustrates data alignment control for the 8-bit access space. with the 8-bit access space, the upper data bus (d15 to d8) is always used for accesses. the amount of data that can be accessed at one time is one byte: a word transfer instruction is performed as two byte accesses, and a longword transfer instruction, as four byte accesses. d15 d8 d7 d0 upper data bus lower data bus byte size word size 1st bus cycle 2nd bus cycle longword size 1st bus cycle 2nd bus cycle 3rd bus cycle 4th bus cycle figure 7-4 access sizes and data alignment control (8-bit access space)
156 16-bit access space: figure 7-5 illustrates data alignment control for the 16-bit access space. with the 16-bit access space, the upper data bus (d15 to d8) and lower data bus (d7 to d0) are used for accesses. the amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. in byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd. the upper data bus is used for an even address, and the lower data bus for an odd address. d15 d8 d7 d0 upper data bus byte size word size 1st bus cycle 2nd bus cycle longword size ?even address byte size ?odd address lower data bus figure 7-5 access sizes and data alignment control (16-bit access space)
157 7.4.3 valid strobes table 7-4 shows the data buses used and valid strobes for the access spaces. in a read, the rd signal is valid without discrimination between the upper and lower halves of the data bus. in a write, the hwr signal is valid for the upper half of the data bus, and the lwr signal for the lower half. table 7-4 data buses used and valid strobes area access size read/ write address valid strobe upper data bus (d15 to d8) lower data bus (d7 to d0) 8-bit access byte read rd valid invalid space write hwr hi-z 16-bit access byte read even rd valid invalid space odd invalid valid write even hwr valid hi-z odd lwr hi-z valid word read rd valid valid write hwr , lwr valid valid note: hi-z: high impedance. invalid: input state; input value is ignored.
158 7.4.4 basic timing 8-bit 2-state access space: figure 7-6 shows the bus timing for an 8-bit 2-state access space. when an 8-bit access space is accessed , the upper half (d15 to d8) of the data bus is used. wait states cannot be inserted. bus cycle t1 t2 address bus csn as rd d15 to d8 valid d7 to d0 invalid read hwr lwr (16-bit bus mode) d15 to d8 valid d7 to d0 write note: n = 0 to 7 high high impedance lwr (8-bit bus mode) high impedance figure 7-6 bus timing for 8-bit 2-state access space
159 8-bit 3-state access space: figure 7-7 shows the bus timing for an 8-bit 3-state access space. when an 8-bit access space is accessed, the upper half (d15 to d8) of the data bus is used. wait states can be inserted. bus cycle t1 t2 address bus csn as rd d15 to d8 valid d7 to d0 invalid read hwr d15 to d8 valid d7 to d0 high impedance write note: n = 0 to 7 t3 lwr (16-bit bus mode) lwr (8-bit bus mode) high high impedance figure 7-7 bus timing for 8-bit 3-state access space
160 16-bit 2-state access space: figures 7-8 to 7-10 show bus timings for a 16-bit 2-state access space. when a 16-bit access space is accessed, the upper half (d15 to d8) of the data bus is used for the even address, and the lower half (d7 to d0) for the odd address. wait states cannot be inserted. bus cycle t1 t2 address bus csn as rd d15 to d8 valid d7 to d0 invalid read hwr lwr d15 to d8 valid d7 to d0 write high note: n = 0 to 7 high impedance figure 7-8 bus timing for 16-bit 2-state access space (1) (even address byte access)
161 bus cycle t1 t2 address bus csn as rd d15 to d8 invalid d7 to d0 valid read hwr lwr d15 to d8 d7 to d0 valid write note: n = 0 to 7 high high impedance figure 7-9 bus timing for 16-bit 2-state access space (2) (odd address byte access)
162 bus cycle t1 t2 address bus csn as rd d15 to d8 valid d7 to d0 valid read hwr lwr d15 to d8 valid d7 to d0 valid write note: n = 0 to 7 figure 7-10 bus timing for 16-bit 2-state access space (3) (word access)
163 16-bit 3-state access space: figures 7-11 to 7-13 show bus timings for a 16-bit 3-state access space. when a 16-bit access space is accessed , the upper half (d15 to d8) of the data bus is used for the even address, and the lower half (d7 to d0) for the odd address. wait states can be inserted. bus cycle t1 t2 address bus csn as rd d15 to d8 valid d7 to d0 invalid read hwr lwr d15 to d8 valid d7 to d0 high impedance write high note: n = 0 to 7 t3 figure 7-11 bus timing for 16-bit 3-state access space (1) (even address byte access)
164 bus cycle t1 t2 address bus csn as rd d15 to d8 invalid d7 to d0 valid read hwr lwr d15 to d8 d7 to d0 valid write high note: n = 0 to 7 t3 high impedance figure 7-12 bus timing for 16-bit 3-state access space (2) (odd address byte access)
165 bus cycle t1 t2 address bus csn as rd d15 to d8 valid d7 to d0 valid read hwr lwr d15 to d8 valid d7 to d0 valid write note: n = 0 to 7 t3 figure 7-13 bus timing for 16-bit 3-state access space (3) (word access)
166 7.4.5 wait control when accessing external space, the h8s/2237 series and h8s/2227 series can extend the bus cycle by inserting one or more wait states (t w ). there are two ways of inserting wait states: program wait insertion and pin wait insertion using the wait pin. program wait insertion from 0 to 3 wait states can be inserted automatically between the t 2 state and t 3 state on an individual area basis in 3-state access space, according to the settings of wcrh and wcrl. pin wait insertion setting the waite bit in bcrh to 1 enables wait insertion by means of the wait pin. when external space is accessed in this state, program wait insertion is first carried out according to the settings in wcrh and wcrl. then , if the wait pin is low at the falling edge of ?in the last t 2 or t w state, a t w state is inserted. if the wait pin is held low, t w states are inserted until it goes high. this is useful when inserting four or more t w states, or when changing the number of t w states for different external devices. the waite bit setting applies to all areas.
167 figure 7-14 shows an example of wait state insertion timing. by program wait t1 address bus as rd data bus read data read hwr, lwr write data write note: indicates the timing of wait pin sampling. wait data bus t2 tw tw tw t3 by wait pin figure 7-14 example of wait state insertion timing the settings after a power-on reset are: 3-state access, 3 program wait state insertion, and wait input disabled. when a manual reset is performed, the contents of bus controller registers are retained, and the wait control settings remain the same as before the reset.
168 7.5 burst rom interface 7.5.1 overview with the h8s/2237 series and h8s/2227 series, external space area 0 can be designated as burst rom space, and burst rom interfacing can be performed. the burst rom space interface enables 16-bit configuration rom with burst access capability to be accessed at high speed. area 0 can be designated as burst rom space by means of the brstrm bit in bcrh. consecutive burst accesses of a maximum of 4 words or 8 words can be performed for cpu instruction fetches only. one or two states can be selected for burst access. 7.5.2 basic timing the number of states in the initial cycle (full access) of the burst rom interface is in accordance with the setting of the ast0 bit in astcr. also, when the ast0 bit is set to 1, wait state insertion is possible. one or two states can be selected for the burst cycle, according to the setting of the brsts1 bit in bcrh. wait states cannot be inserted. when area 0 is designated as burst rom space, it becomes 16-bit access space regardless of the setting of the abw0 bit in abwcr. when the brsts0 bit in bcrh is cleared to 0, burst access of up to 4 words is performed; when the brsts0 bit is set to 1, burst access of up to 8 words is performed. the basic access timing for burst rom space is shown in figures 7-15 (a) and (b). the timing shown in figure 7-15 (a) is for the case where the ast0 and brsts1 bits are both set to 1, and that in figure 7-15 (b) is for the case where both these bits are cleared to 0.
169 t1 address bus cs0 as data bus t2 t3 t1 t2 t1 full access t2 rd burst access only lower address changed read data read data read data figure 7-15 (a) example of burst rom access timing (when ast0 = brsts1 = 1)
170 t1 address bus cs0 as data bus t2 t1 t1 full access rd burst access only lower address changed read data read data read data figure 7-15 (b) example of burst rom access timing (when ast0 = brsts1 = 0) 7.5.3 wait control as with the basic bus interface, either program wait insertion or pin wait insertion using the wait pin can be used in the initial cycle (full access) of the burst rom interface. see section 7.4.5, wait control. wait states cannot be inserted in a burst cycle.
171 7.6 idle cycle 7.6.1 operation when the h8s/2237 series and h8s/2227 series accesse external space , it can insert a 1-state idle cycle (t i ) between bus cycles in the following two cases: (1) when read accesses between different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. by inserting an idle cycle it is possible, for example, to avoid data collisions between rom, with a long output floating time, and high-speed memory, i/o interfaces, and so on. (1) consecutive reads between different areas if consecutive reads between different areas occur while the icis1 bit in bcrh is set to 1, an idle cycle is inserted at the start of the second read cycle. figure 7-16 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a read cycle from sram, each being located in a different area. in (a), an idle cycle is not inserted, and a collision occurs in cycle b between the read data from rom and that from sram. in (b), an idle cycle is inserted, and a data collision is prevented. t1 address bus rd bus cycle a data bus t2 t3 t1 t2 bus cycle b bus cycle a bus cycle b long output floating time data collision (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) t1 address bus ? rd data bus t2 t3 ti t1 t2 cs (area a) cs (area b) cs (area a) cs (area b) figure 7-16 example of idle cycle operation (1)
172 (2) write after read if an external write occurs after an external read while the icis0 bit in bcrh is set to 1, an idle cycle is inserted at the start of the write cycle. figure 7-17 shows an example of the operation in this case. in this example, bus cycle a is a read cycle from rom with a long output floating time, and bus cycle b is a cpu write cycle. in (a), an idle cycle is not inserted, and a collision occurs in cycle b between the read data from rom and the cpu write data. in (b), an idle cycle is inserted, and a data collision is prevented. t1 address bus rd bus cycle a data bus t2 t3 t1 t2 bus cycle b long output floating time data collision t1 address bus ? rd bus cycle a data bus t2 t3 ti t1 bus cycle b t2 hwr hwr cs (area a) cs (area b) cs (area a) cs (area b) (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) figure 7-17 example of idle cycle operation (2)
173 (3) relationship between chip select ( cs ) signal and read ( rd ) signal depending on the system? load conditions, the rd signal may lag behind the cs signal. an example is shown in figure 7.18. in this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle a rd signal and the bus cycle b cs signal. setting idle cycle insertion, as in (b), however, will prevent any overlap between the rd and cs signals. in the initial state after reset release, idle cycle insertion (b) is set. t1 address bus rd bus cycle a t2 t3 t1 t2 bus cycle b possibility of overlap between cs (area b) and rd t1 address bus ? bus cycle a t2 t3 ti t1 bus cycle b t2 cs (area a) cs (area b) rd cs (area a) cs (area b) (a) idle cycle not inserted (icis1 = 0) (b) idle cycle inserted (initial value icis1 = 1) figure 7.18 relationship between chip select ( cs ) and read ( rd )
174 7.6.2 pin states in idle cycle table 7-5 shows pin states in an idle cycle. table 7-5 pin states in idle cycle pins pin state a23 to a0 contents of next bus cycle d15 to d0 high impedance csn high as high rd high hwr high lwr high
175 7.7 bus release 7.7.1 overview the h8s/2237 series and h8s/2227 series can release the external bus in response to a bus request from an external device. in the external bus released state, the internal bus master continues to operate as long as there is no external access. 7.7.2 operation in external expansion mode, the bus can be released to an external device by setting the brle bit in bcrl to 1. driving the breq pin low issues an external bus request to the h8s/2237 series and h8s/2227 series. when the breq pin is sampled, at the prescribed timing the back pin is driven low, and the address bus, data bus, and bus control signals are placed in the high- impedance state, establishing the external bus-released state. in the external bus released state, an internal bus master can perform accesses using the internal bus. when an internal bus master wants to make an external access, it temporarily defers activation of the bus cycle, and waits for the bus request from the external bus master to be dropped. when the breq pin is driven high, the back pin is driven high at the prescribed timing and the external bus released state is terminated. in the event of simultaneous external bus release request and external access request generation, the order of priority is as follows: (high) external bus release > internal bus master external access (low)
176 7.7.3 pin states in external bus released state table 7-6 shows pin states in the external bus released state. table 7-6 pin states in bus released state pins pin state a23 to a0 high impedance d15 to d0 high impedance csn high impedance as high impedance rd high impedance hwr high impedance lwr high impedance
177 7.7.4 transition timing figure 7-19 shows the timing for transition to the bus-released state. cpu cycle external bus released state cpu cycle address minimum 1 state t0 t1 t2 address bus data bus csn as hwr , lwr breq back high impedance [1] [2] [3] [4] [5] [1] [2] [3] [4] [5] note: n= 0 to 7 low level of breq pin is sampled at rise of t 2 state. back pin is driven low at end of cpu read cycle, releasing bus to external bus master. breq pin state is still sampled in external bus released state. high level of breq pin is sampled. back pin is driven high, ending bus release cycle. high impedance high impedance high impedance high impedance rd high impedance figure 7-19 bus-released state transition timing
178 7.7.5 usage note when mstpcr is set to h'ffffff and a transition is made to sleep mode, the external bus release function halts. therefore, mstpcr should not be set to h'ffffff if the external bus release function is to be used in sleep mode. 7.8 bus arbitration 7.8.1 overview the h8s/2237 series and h8s/2227 series have a bus arbiter that arbitrates bus master operations. there are two bus masters, the cpu and dtc, which perform read/write operations when they have possession of the bus. each bus master requests the bus by means of a bus request signal. the bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a bus request acknowledge signal. the selected bus master then takes possession of the bus and begins its operation. 7.8.2 operation the bus arbiter detects the bus masters?bus request signals, and if the bus is requested, sends a bus request acknowledge signal to the bus master making the request. if there are bus requests from more than one bus master, the bus request acknowledge signal is sent to the one with the highest priority. when a bus master receives the bus request acknowledge signal, it takes possession of the bus until that signal is canceled. the order of priority of the bus masters is as follows: (high) dtc > cpu (low) an internal bus access by an internal bus master, and external bus release, can be executed in parallel. in the event of simultaneous external bus release request, and internal bus master external access request generation, the order of priority is as follows: (high) external bus release > internal bus master external access (low)
179 7.8.3 bus transfer timing even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately. there are specific times at which each bus master can relinquish the bus. cpu: the cpu is the lowest-priority bus master, and if a bus request is received from the dtc, the bus arbiter transfers the bus to the bus master that issued the request. the timing for transfer of the bus is as follows: ? the bus is transferred at a break between bus cycles. however, if a bus cycle is executed in discrete operations, as in the case of a longword-size access, the bus is not transferred between the operations. see appendix a-5, bus states during instruction execution, for timings at which the bus is not transferred. ? if the cpu is in sleep mode, it transfers the bus immediately. dtc: the dtc sends the bus arbiter a request for the bus when an activation request is generated. the dtc can release the bus after a vector read, a register information read (3 states), a single data transfer, or a register information write (3 states). it does not release the bus during a register information read (3 states), a single data transfer, or a register information write (3 states). 7.8.4 external bus release usage note external bus release can be performed on completion of an external bus cycle. the cs signal remains low until the end of the external bus cycle. therefore, when external bus release is performed, the cs signal may change from the low level to the high-impedance state. 7.9 resets and the bus controller in a power-on reset, the h8s/2237 series and h8s/2227 series, including the bus controller, enter the reset state at that point, and an executing bus cycle is discontinued. in a manual reset, the bus controller? registers and internal state are maintained, and an executing external bus cycle is completed. in this case, wait input is ignored and write data is not guaranteed.
180
181 section 8 data transfer controller (dtc) 8.1 overview the h8s/2237 series and h8s/2227 series include a data transfer controller (dtc). the dtc can be activated by an interrupt or software, to transfer data. 8.1.1 features the features of the dtc are: ? transfer possible over any number of channels ? transfer information is stored in memory ? one activation source can trigger a number of data transfers (chain transfer) ? wide range of transfer modes ? normal, repeat, and block transfer modes available ? incrementing, decrementing, and fixing of source and destination addresses can be selected ? direct specification of 16-mbyte address space possible ? 24-bit transfer source and destination addresses can be specified ? transfer can be set in byte or word units ? a cpu interrupt can be requested for the interrupt that activated the dtc ? an interrupt request can be issued to the cpu after one data transfer ends ? an interrupt request can be issued to the cpu after the specified data transfers have completely ended ? activation by software is possible ? module stop mode can be set ? the initial setting enables dtc registers to be accessed. dtc operation is halted by setting module stop mode.
182 8.1.2 block diagram figure 8-1 shows a block diagram of the dtc. the dtc? register information is stored in the on-chip ram*. a 32-bit bus connects the dtc to the on-chip ram (1 kbyte), enabling 32-bit/1-state reading and writing of the dtc register information. note: * when the dtc is used, the rame bit in syscr must be set to 1. interrupt request interrupt controller dtc internal address bus dtc service request control logic register information mra mrb cra crb dar sar cpu interrupt request on-chip ram internal data bus legend mra, mrb cra, crb sar dar dtcera to dtcerf, dtceri dtvecr dtcera to dtcerf, dtceri dtvecr : dtc mode registers a and b : dtc transfer count registers a and b : dtc source address register : dtc destination address register : dtc enable registers a to f and i : dtc vector register figure 8-1 block diagram of dtc
183 8.1.3 register configuration table 8-1 summarizes the dtc registers. table 8-1 dtc registers name abbreviation r/w initial value address * 1 dtc mode register a mra * 2 undefined * 3 dtc mode register b mrb * 2 undefined * 3 dtc source address register sar * 2 undefined * 3 dtc destination address register dar * 2 undefined * 3 dtc transfer count register a cra * 2 undefined * 3 dtc transfer count register b crb * 2 undefined * 3 dtc enable registers dtcer r/w h'00 h'ff16 to h'fe1b, h'fe1e dtc vector register dtvecr r/w h'00 h'fe1f module stop control register a mstpcra r/w h'3f h'fde8 notes: 1. lower 16 bits of the address. 2. registers within the dtc cannot be read or written to directly. 3. register information is located in on-chip ram addresses h'ebc0 to h'efbf. it cannot be located in external memory space. when the dtc is used, do not clear the rame bit in syscr to 0.
184 8.2 register descriptions 8.2.1 dtc mode register a (mra) 7 sm1 6 sm0 5 dm1 4 dm0 3 md1 0 sz 2 md0 1 dts bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined mra is an 8-bit register that controls the dtc operating mode. bits 7 and 6?ource address mode 1 and 0 (sm1, sm0): these bits specify whether sar is to be incremented, decremented, or left fixed after a data transfer. bit 7 bit 6 sm1 sm0 description 0 sar is fixed 1 0 sar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 1 sar is decremented after a transfer (by ? when sz = 0; by ? when sz = 1) bits 5 and 4?estination address mode 1 and 0 (dm1, dm0): these bits specify whether dar is to be incremented, decremented, or left fixed after a data transfer. bit 5 bit 4 dm1 dm0 description 0 dar is fixed 1 0 dar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) 1 dar is decremented after a transfer (by ? when sz = 0; by ? when sz = 1)
185 bits 3 and 2?tc mode (md1, md0): these bits specify the dtc transfer mode. bit 3 bit 2 md1 md0 description 0 0 normal mode 1 repeat mode 1 0 block transfer mode 1 bit 1?tc transfer mode select (dts): specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode. bit 1 dts description 0 destination side is repeat area or block area 1 source side is repeat area or block area bit 0?tc data transfer size (sz): specifies the size of data to be transferred. bit 0 sz description 0 byte-size transfer 1 word-size transfer
186 8.2.2 dtc mode register b (mrb) 7 chne 6 disel 5 4 3 0 2 1 bit initial value : : r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined mrb is an 8-bit register that controls the dtc operating mode. bit 7?tc chain transfer enable (chne): specifies chain transfer. with chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. in data transfer with chne set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of dtcer is not performed. bit 7 chne description 0 end of dtc data transfer (activation waiting state is entered) 1 dtc chain transfer (new register information is read, then data is transferred) bit 6?tc interrupt select (disel): specifies whether interrupt requests to the cpu are disabled or enabled after a data transfer. bit 6 disel description 0 after a data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 (the dtc clears the interrupt source flag of the activating interrupt to 0) 1 after a data transfer ends, the cpu interrupt is enabled (the dtc does not clear the interrupt source flag of the activating interrupt to 0) bits 5 to 0?eserved: these bits have no effect on dtc operation in the h8s/2237 series and h8s/2227 series, and should always be written with 0.
187 8.2.3 dtc source address register (sar) 23 22 21 20 19 43210 bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined sar is a 24-bit register that designates the source address of data to be transferred by the dtc. for word-size transfer, specify an even source address. 8.2.4 dtc destination address register (dar) 23 22 21 20 19 43210 bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined dar is a 24-bit register that designates the destination address of data to be transferred by the dtc. for word-size transfer, specify an even destination address. 8.2.5 dtc transfer count register a (cra) 15 14 13 12 11109876543210 crah cral bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined cra is a 16-bit register that designates the number of times data is to be transferred by the dtc. in normal mode, the entire cra functions as a 16-bit transfer counter (1 to 65536). it is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. in repeat mode or block transfer mode, the cra is divided into two parts: the upper 8 bits (crah) and the lower 8 bits (cral). crah holds the number of transfers while cral functions as an 8-bit transfer counter (1 to 256). cral is decremented by 1 every time data is transferred, and the contents of crah are sent when the count reaches h'00. this operation is repeated.
188 8.2.6 dtc transfer count register b (crb) 15 14 13 12 11109876543210 bit initial value : : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined r/w : crb is a 16-bit register that designates the number of times data is to be transferred by the dtc in block transfer mode. it functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1 every time data is transferred, and transfer ends when the count reaches h'0000. 8.2.7 dtc enable registers (dtcer) 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w bit initial value r/w : : : the dtc enable registers comprise seven 8-bit readable/writable registers, dtcera to dtcerf and dtceri, with bits corresponding to the interrupt sources that can control enabling and disabling of dtc activation. these bits enable or disable dtc service for the corresponding interrupt sources. the dtc enable registers are initialized to h'00 by a reset and in hardware standby mode. bit n?tc activation enable (dtcen) bit n dtcen description 0 dtc activation by this interrupt is disabled (initial value) [clearing conditions] ? when the disel bit is 1 and the data transfer has ended ? when the specified number of transfers have ended 1 dtc activation by this interrupt is enabled [holding condition] when the disel bit is 0 and the specified number of transfers have not ended (n = 7 to 0) a dtce bit can be set for each interrupt source that can activate the dtc. the correspondence between interrupt sources and dtce bits is shown in table 8-4, together with the vector number generated for each interrupt controller.
189 for dtce bit setting, use bit manipulation instructions such as bset and bclr for reading and writing. if all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register. 8.2.8 dtc vector register (dtvecr) 7 swdte 0 r/(w) * 1 6 dtvec6 0 r/w * 2 5 dtvec5 0 r/w * 2 4 dtvec4 0 r/w * 2 3 dtvec3 0 r/w * 2 0 dtvec0 0 r/w * 2 2 dtvec2 0 r/w * 2 1 dtvec1 0 r/w * 2 notes: 1. only 1 can be written to the swdte bit. 2. bits dtvec6 to dtvec0 can be written to when swdte = 0. bit initial value r/w : : : dtvecr is an 8-bit readable/writable register that enables or disables dtc activation by software, and sets a vector number for the software activation interrupt. dtvecr is initialized to h'00 by a reset and in hardware standby mode. bit 7?tc software activation enable (swdte): enables or disables dtc activation by software. bit 7 swdte description 0 dtc software activation is disabled (initial value) [clearing condition] ? when the disel bit is 0 and the specified number of transfers have not ended ? when 0 is written to the disel bit after a software-activated data transfer end interrupt (swdtend) request has been sent to the cpu 1 dtc software activation is enabled [holding conditions] ? when the disel bit is 1 and data transfer has ended ? when the specified number of transfers have ended ? during data transfer due to software activation bits 6 to 0?tc software activation vectors 6 to 0 (dtvec6 to dtvec0): these bits specify a vector number for dtc software activation. the vector address is expressed as h'0400 + ((vector number) << 1). <<1 indicates a one-bit left- shift. for example, when dtvec6 to dtvec0 = h'10, the vector address is h'0420.
190 8.2.9 module stop control register a (mstpcra) 7 mstpa7 0 r/w bit initial value read/write 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w 0 mstpa0 1 r/w mstpcra is a 8-bit readable/writable register that performs module stop mode control. when the mstpa6 bit in mstpcra is set to 1, the dtc operation stops at the end of the bus cycle and a transition is made to module stop mode. however, 1 cannot be written in the mstpa6 bit while the dtc is operating. for details, see section 20.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 6?odule stop (mstpa6): specifies the dtc module stop mode. bit 6 mstpa6 description 0 dtc module stop mode cleared (initial value) 1 dtc module stop mode set
191 8.3 operation 8.3.1 overview when activated, the dtc reads register information that is already stored in memory and transfers data on the basis of that register information. after the data transfer, it writes updated register information back to memory. pre-storage of register information in memory makes it possible to transfer data over any required number of channels. setting the chne bit to 1 makes it possible to perform a number of transfers with a single activation. figure 8-2 shows a flowchart of dtc operation. start read dtc vector next transfer read register information data transfer write register information clear an activation flag chne=1 end no no yes yes transfer counter= 0 or disel= 1 clear dtcer interrupt exception handling figure 8-2 flowchart of dtc operation
192 the dtc transfer mode can be normal mode, repeat mode, or block transfer mode. the 24-bit sar designates the dtc transfer source address and the 24-bit dar designates the transfer destination address. after each transfer, sar and dar are independently incremented, decremented, or left fixed. table 8-2 outlines the functions of the dtc. table 8-2 dtc functions address registers transfer mode activation source transfer source transfer destination ? normal mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? up to 65,536 transfers possible ? repeat mode ? one transfer request transfers one byte or one word ? memory addresses are incremented or decremented by 1 or 2 ? after the specified number of transfers (1 to 256), the initial state resumes and operation continues ? block transfer mode ? one transfer request transfers a block of the specified size ? block size is from 1 to 256 bytes or words ? up to 65,536 transfers possible ? a block area can be designated at either the source or destination ? irq ? tpu tgi ? 8-bit timer cmi ? sci txi or rxi ? a/d converter adi ? software 24 bits 24 bits
193 8.3.2 activation sources the dtc operates when activated by an interrupt or by a write to dtvecr by software. an interrupt request can be directed to the cpu or dtc, as designated by the corresponding dtcer bit. an interrupt becomes a dtc activation source when the corresponding bit is set to 1, and a cpu interrupt source when the bit is cleared to 0. at the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the activation source or corresponding dtcer bit is cleared. table 8-3 shows activation source and dtcer clearance. the activation source flag, in the case of rxi0, for example, is the rdrf flag of sci0. table 8-3 activation source and dtcer clearance activation source when the disel bit is 0 and the specified number of transfers have not ended when the disel bit is 1, or when the specified number of transfers have ended software activation the swdte bit is cleared to 0 the swdte bit remains set to 1 an interrupt is issued to the cpu interrupt activation the corresponding dtcer bit remains set to 1 the activation source flag is cleared to 0 the corresponding dtcer bit is cleared to 0 the activation source flag remains set to 1 a request is issued to the cpu for the activation source interrupt figure 8-3 shows a block diagram of activation source control. for details see section 5, interrupt controller. on-chip supporting module irq interrupt dtvecr selection circuit interrupt controller cpu dtc dtcer clear controller select interrupt request source flag cleared clear clear request interrupt mask figure 8-3 block diagram of dtc activation source control
194 when an interrupt has been designated a dtc activation source, existing cpu mask level and interrupt controller priorities have no effect. if there is more than one activation source at the same time, the dtc operates in accordance with the default priorities. 8.3.3 dtc vector table figure 8-4 shows the correspondence between dtc vector addresses and register information. table 8-4 shows the correspondence between activation and vector addresses. when the dtc is activated by software, the vector address is obtained from: h'0400 + (dtvecr[6:0] < 195 table 8-4 interrupt sources, dtc vector addresses, and corresponding dtces interrupt source origin of interrupt source vector number vector address dtce * priority write to dtvecr software dtvecr h'0400+ (dtvecr [6:0] <<1) high irq0 external pin 16 h'0420 dtcea7 irq1 17 h'0422 dtcea6 irq2 18 h'0424 dtcea5 irq3 19 h'0426 dtcea4 irq4 20 h'0428 dtcea3 irq5 21 h'042a dtcea2 irq6 22 h'042c dtcea1 irq7 23 h'042e dtcea0 adi (a/d conversion end) a/d 28 h'0438 dtceb6 tgi0a (gr0a compare match/ input capture) tpu channel 0 32 h'0440 dtceb5 tgi0b (gr0b compare match/ input capture) 33 h'0442 dtceb4 tgi0c (gr0c compare match/ input capture) 34 h'0444 dtceb3 tgi0d (gr0d compare match/ input capture) 35 h'0446 dtceb2 tgi1a (gr1a compare match/ input capture) tpu channel 1 40 h'0450 dtceb1 tgi1b (gr1b compare match/ input capture) 41 h'0452 dtceb0 tgi2a (gr2a compare match/ input capture) tpu channel 2 44 h'0458 dtcec7 tgi2b (gr2b compare match/ input capture) 45 h'045a dtcec6 low note: * dtce bits with no corresponding interrupt are reserved, and should be written with 0.
196 table 8-4 interrupt sources, dtc vector addresses, and corresponding dtces (cont) interrupt source origin of interrupt source vector number vector address dtce priority tgi3a (gr3a compare match/ input capture) tpu channel 3 48 h'0460 dtcec5 high tgi3b (gr3b compare match/ input capture) 49 h'0462 dtcec4 tgi3c (gr3c compare match/ input capture) 50 h'0464 dtcec3 tgi3d (gr3d compare match/ input capture) 51 h'0466 dtcec2 tgi4a (gr4a compare match/ input capture) tpu channel 4 56 h'0470 dtcec1 tgi4b (gr4b compare match/ input capture) 57 h'0472 dtcec0 tgi5a (gr5a compare match/ input capture) tpu channel 5 60 h'0478 dtced5 tgi5b (gr5b compare match/ input capture) 61 h'047a dtced4 cmia0 8-bit timer 64 h'0480 dtced3 cmib0 channel 0 65 h'0482 dtced2 cmia1 8-bit timer 68 h'0488 dtced1 cmib1 channel 1 69 h'048a dtced0 rxi0 (reception complete 0) sci 81 h'04a2 dtcee3 txi0 (transmit data empty 0) channel 0 82 h'04a4 dtcee2 rxi1 (reception complete 1) sci 85 h'04aa dtcee1 txi1 (transmit data empty 1) channel 1 86 h'04ac dtcee0 rxi2 (reception complete 2) sci 89 h'04b2 dtcef7 txi2 (transmit data empty 2) channel 2 90 h'04b4 dtcef6 rxi3 (reception complete 3) sci 121 h'04f2 dtcei7 txi3 (transmit data empty 3) channel 3 122 h'04f4 dtcei6 low
197 register information start address register information chain transfer dtc vector address figure 8-4 correspondence between dtc vector address and register information 8.3.4 location of register information in address space figure 8-5 shows how the register information should be located in the address space. locate the mra, sar, mrb, dar, cra, and crb registers, in that order, from the start address of the register information (contents of the vector address). in the case of chain transfer, register information should be located in consecutive areas. locate the register information in the on-chip ram (addresses: h'ffebc0 to h'ffefbf). register information start address chain transfer register information for 2nd transfer in chain transfer mra sar mrb dar cra crb 4 bytes lower address cra crb register information mra 0 123 sar mrb dar figure 8-5 location of register information in address space
198 8.3.5 normal mode in normal mode, one operation transfers one byte or one word of data. from 1 to 65,536 transfers can be specified. once the specified number of transfers have ended, a cpu interrupt can be requested. table 8-5 lists the register information in normal mode and figure 8-6 shows memory mapping in normal mode. table 8-5 register information in normal mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register a cra designates transfer count dtc transfer count register b crb not used transfer sar dar figure 8-6 memory mapping in normal mode
199 8.3.6 repeat mode in repeat mode, one operation transfers one byte or one word of data. from 1 to 256 transfers can be specified. once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. in repeat mode the transfer counter value does not reach h'00, and therefore cpu interrupts cannot be requested when disel = 0. table 8-6 lists the register information in repeat mode and figure 8-7 shows memory mapping in repeat mode. table 8-6 register information in repeat mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds number of transfers dtc transfer count register al cral designates transfer count dtc transfer count register b crb not used transfer sar or dar dar or sar repeat area figure 8-7 memory mapping in repeat mode
200 8.3.7 block transfer mode in block transfer mode, one operation transfers one block of data. either the transfer source or the transfer destination is designated as a block area. the block size is 1 to 256. when the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. the other address register is then incremented, decremented, or left fixed. from 1 to 65,536 transfers can be specified. once the specified number of transfers have ended, a cpu interrupt is requested. table 8-7 lists the register information in block transfer mode and figure 8-8 shows memory mapping in block transfer mode. table 8-7 register information in block transfer mode name abbreviation function dtc source address register sar designates source address dtc destination address register dar designates destination address dtc transfer count register ah crah holds block size dtc transfer count register al cral designates block size count dtc transfer count register b crb transfer count
201 transfer sar or dar dar or sar block area first block nth block figure 8-8 memory mapping in block transfer mode
202 8.3.8 chain transfer setting the chne bit to 1 enables a number of data transfers to be performed consectutively in response to a single transfer request. sar, dar, cra, crb, mra, and mrb, which define data transfers, can be set independently. figure 8-9 shows the memory map for chain transfer. source source destination destination dtc vector address register information start address register information chne = 1 register information chne = 0 figure 8-9 chain transfer memory map in the case of transfer with chne set to 1, an interrupt request to the cpu is not generated at the end of the specified number of transfers or by setting of the disel bit to 1, and the interrupt source flag for the activation source is not affected.
203 8.3.9 operation timing figures 8-10 to 8-12 show an example of dtc operation timing. dtc activation request dtc request address vector read transfer information read transfer information write data transfer read write figure 8-10 dtc operation timing (example in normal mode or repeat mode) read write read write data transfer transfer information write transfer information read vector read dtc activation request dtc request address figure 8-11 dtc operation timing (example of block transfer mode, with block size of 2)
204 read write read write address dtc activation request dtc request data transfer data transfer transfer information write transfer information write transfer information read transfer information read vector read figure 8-12 dtc operation timing (example of chain transfer) 8.3.10 number of dtc execution states table 8-8 lists execution statuses for a single dtc data transfer, and table 8-9 shows the number of states required for each execution status. table 8-8 dtc execution statuses mode vector read i register information read/write j data read k data write l internal operations m normal 1 6 1 1 3 repeat 1 6 1 1 3 block transfer 1 6 n n 3 n: block size (initial setting of crah and cral)
205 table 8-9 number of states required for each execution status object to be accessed on- chip ram on- chip rom on-chip i/o registers external devices bus width 32 16 8 16 8 16 access states 11222323 vector read s i 1 4 6+2m 2 3+m execution status register s j information read/write byte data read s k word data read s k byte data write s l word data write s l 1 1 1 1 1 1 1 1 1 2 4 2 4 2 2 2 2 2 4 2 4 3+m 6+2m 3+m 6+2m 2 2 2 2 3+m 3+m 3+m 3+m internal operation s m 1 the number of execution states is calculated from the formula below. note that s means the sum of all transfers activated by one activation event (the number in which the chne bit is set to 1, plus 1). number of execution states = i ?s i + s (j ?s j + k ?s k + l ?s l ) + m ?s m for example, when the dtc vector address table is located in on-chip rom, normal mode is set, and data is transferred from the on-chip rom to an internal i/o register, the time required for the dtc operation is 13 states. the time from activation to the end of the data write is 10 states.
206 8.3.11 procedures for using dtc activation by interrupt: the procedure for using the dtc with interrupt activation is as follows: [1] set the mra, mrb, sar, dar, cra, and crb register information in the on-chip ram. [2] set the start address of the register information in the dtc vector address. [3] set the corresponding bit in dtcer to 1. [4] set the enable bits for the interrupt sources to be used as the activation sources to 1. the dtc is activated when an interrupt used as an activation source is generated. [5] after the end of one data transfer, or after the specified number of data transfers have ended, the dtce bit is cleared to 0 and a cpu interrupt is requested. if the dtc is to continue transferring data, set the dtce bit to 1. activation by software: the procedure for using the dtc with software activation is as follows: [1] set the mra, mrb, sar, dar, cra, and crb register information in the on-chip ram. [2] set the start address of the register information in the dtc vector address. [3] check that the swdte bit is 0. [4] write 1 to swdte bit and the vector number to dtvecr. [5] check the vector number written to dtvecr. [6] after the end of one data transfer, if the disel bit is 0 and a cpu interrupt is not requested, the swdte bit is cleared to 0. if the dtc is to continue transferring data, set the swdte bit to 1. when the disel bit is 1, or after the specified number of data transfers have ended, the swdte bit is held at 1 and a cpu interrupt is requested.
207 8.3.12 examples of use of the dtc (1) normal mode an example is shown in which the dtc is used to receive 128 bytes of data via the sci. [1] set mra to fixed source address (sm1 = sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), normal mode (md1 = md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one data transfer by one interrupt (chne = 0, disel = 0). set the sci rdr address in sar, the start address of the ram area where the data will be received in dar, and 128 (h'0080) in cra. crb can be set to any value. [2] set the start address of the register information at the dtc vector address. [3] set the corresponding bit in dtcer to 1. [4] set the sci to the appropriate receive mode. set the rie bit in scr to 1 to enable the reception complete (rxi) interrupt. since the generation of a receive error during the sci reception operation will disable subsequent reception, the cpu should be enabled to accept receive error interrupts. [5] each time reception of one byte of data ends on the sci, the rdrf flag in ssr is set to 1, an rxi interrupt is generated, and the dtc is activated. the receive data is transferred from rdr to ram by the dtc. dar is incremented and cra is decremented. the rdrf flag is automatically cleared to 0. [6] when cra becomes 0 after the 128 data transfers have ended, the rdrf flag is held at 1, the dtce bit is cleared to 0, and an rxi interrupt request is sent to the cpu. the interrupt handling routine should perform wrap-up processing.
208 (2) software activation an example is shown in which the dtc is used to transfer a block of 128 bytes of data by means of software activation. the transfer source address is h'1000 and the destination address is h'2000. the vector number is h'60, so the vector address is h'04c0. [1] set mra to incrementing source address (sm1 = 1, sm0 = 0), incrementing destination address (dm1 = 1, dm0 = 0), block transfer mode (md1 = 1, md0 = 0), and byte size (sz = 0). the dts bit can have any value. set mrb for one block transfer by one interrupt (chne = 0). set the transfer source address (h'1000) in sar, the destination address (h'2000) in dar, and 128 (h'8080) in cra. set 1 (h'0001) in crb. [2] set the start address of the register information at the dtc vector address (h'04c0). [3] check that the swdte bit in dtvecr is 0. check that there is currently no transfer activated by software. [4] write 1 to the swdte bit and the vector number (h'60) to dtvecr. the write data is h'e0. [5] read dtvecr again and check that it is set to the vector number (h'60). if it is not, this indicates that the write failed. this is presumably because an interrupt occurred between steps 3 and 4 and led to a different software activation. to activate this transfer, go back to step 3. [6] if the write was successful, the dtc is activated and a block of 128 bytes of data is transferred. [7] after the transfer, an swdtend interrupt occurs. the interrupt handling routine should clear the swdte bit to 0 and perform other wrap-up processing.
209 8.4 interrupts an interrupt request is issued to the cpu when the dtc finishes the specified number of data transfers, or a data transfer for which the disel bit was set to 1. in the case of interrupt activation, the interrupt set as the activation source is generated. these interrupts to the cpu are subject to cpu mask level and interrupt controller priority level control. in the case of activation by software, a software activated data transfer end interrupt (swdtend) is generated. when the disel bit is 1 and one data transfer has ended, or the specified number of transfers have ended, after data transfer ends, the swdte bit is held at 1 and an swdtend interrupt is generated. the interrupt handling routine should clear the swdte bit to 0. when the dtc is activated by software, an swdtend interrupt is not generated during a data transfer wait or during data transfer even if the swdte bit is set to 1. 8.5 usage notes module stop: when the mstpa6 bit in mstpcra is set to 1, the dtc clock stops, and the dtc enters the module stop state. however, 1 cannot be written in the mstpa6 bit while the dtc is operating. on-chip ram: the mra, mrb, sar, dar, cra, and crb registers are all located in on-chip ram. when the dtc is used, the rame bit in syscr must not be cleared to 0. dtce bit setting: for dtce bit setting, use bit manipulation instructions such as bset and bclr. if all interrupts are masked, multiple activation sources can be set at one time by writing data after executing a dummy read on the relevant register.
210
211 section 9 i/o ports 9.1 overview the h8s/2237 series and h8s/2227 series have ten i/o ports (ports 1, 3, 7, and a to g), and two input-only ports (ports 4 and 9). table 9-1 summarizes the port functions. the pins of each port also have other functions. each port includes a data direction register (ddr) that controls input/output (not provided for the input-only ports), a data register (dr) that stores output data, and a port register (port) used to read the pin states. ports a to e have a built-in mos input pull-up function, and in addition to dr and ddr, have a mos input pull-up control register (pcr) to control the on/off status of the mos input pull-ups. ports 3 and a include an open-drain control register (odr) that controls the on/off status of the output buffer pmos. all the ports can drive a single ttl load and 30 pf capacitive load. the irq pins are schmitt-triggered inputs. block diagrams of each port are give in appendix c, i/o port block diagrams.
212 table 9-1 (a) h8s/2237 series port functions port description pins mode 4 mode 5 mode 6 mode 7 port 1 8-bit i/o port schmitt-triggered input ( irq0 , irq1 ) p17/tiocb2/tclkd p16/tioca2/ irq1 p15/tiocb1/tclkc p14/tioca1/ irq0 p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 p10/tioca0/a20 8-bit i/o port also functioning as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, tiocb2), interrupt input pins ( irq0 , irq1 ), and address output (a20 to a23) 8-bit i/o port also functioning as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, tiocb2) and interrupt input pins ( irq0 , irq1 ) port 3 7-bit i/o port open-drain output capability schmitt-triggered input ( irq4 , irq5 ) p36 p35/sck1/ irq5 p34/rxd1 p33/txd1 p32/sck0/ irq4 p31/rxd0 p30/txd0 7-bit i/o port also functioning as sci (channel 0 and 1) i/o pins (txd0, rxd0, sck0, txd1, rxd1, sck1) and interrupt input pins ( irq4 , irq5 ) port 4 8-bit input port p47/an7 p46/an6 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 p40/an0 8-bit input port also functioning as a/d converter analog input (an7 to an0) port 7 8-bit i/o port p77/txd3 p77/rxd3 p75/sck3 p74/ mres 8-bit i/o port also functioning as sci (channel 3) i/o pins (txd3, rxd3, sck3), manual reset pin ( mres ), and 8-bit timer (channel 0 and 1) i/o pins (tmri01, tmci01, tmo0, tmo1) p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci01/ cs4 when ddr = 0: dual function as input ports and 8-bit timer (channel 0 and 1) i/o pins (tmri01, tmci01, tmo0, tmo1) when ddr = 1: dual function as 8-bit timer (channel 0 and 1) i/o pins (tmri01, tmci01, tmo0, tmo1) and cs7 to cs4 output port 9 2-bit input port p97/da1 p96/da0 2-bit input port also functioning as d/a converter analog output (da1, da0) port a 4-bit i/o port ?built-in mos input pull-up ?open-drain output capability pa3/a19/sck2 pa2/a18/rxd2 pa1/a17/txd2 pa0/a16 4-bit i/o port also functioning as sci (channel 2) i/o pins (txd2, rxd2, sck2) and address output (a19 to a16) 4-bit i/o port also functioning as sci (channel 2) i/o pins (txd2, rxd2, sck2)
213 table 9-1 (a) h8s/2237 series port functions (cont) port description pins mode 4 mode 5 mode 6 mode 7 port b 8-bit i/o port built-in mos input pull-up pb7/a15/tiocb5 pb6/a14/tioca5 pb5/a13/tiocb4 pb4/a12/tioca4 pb3/a11/tiocd3 pb2/a10/tiocc3 pb1/a9/tiocb3 pb0/a8/tioca3 8-bit i/o port also functioning as tpu i/o pins (tiocb5, tioca5, tiocb4, tioca4, tiocd3, tiocc3, tiocb3, tioca3) and address output (a15 to a8) 8-bit i/o port also functioning as tpu i/o pins (tiocb5, tioca5, tiocb4, tioca4, tiocd3, tiocc3, tiocb3, tioca3) port c 8-bit i/o port built-in mos input pull-up pc7/a7 to pc0/a0 address output (a7?0) when ddr = 0: input port when ddr = 1: address output 8-bit i/o port port d 8-bit i/o port built-in mos input pull-up pd7/d15 to pd0/d8 data bus input/output i/o port port e 8-bit i/o port built-in mos input pull-up pe7/d7 to pe0/d0 in 8-bit bus mode: i/o port in 16-bit bus mode: data bus input/output i/o port port f 8-bit i/o port schmitt-triggered input ( irq3 , irq2 ) pf7/ when ddr = 0: input port when ddr = 1 (after reset): ?output when ddr = 0 (after reset): input port when ddr = 1: output pf6/ as pf5/ rd pf4/ hwr as , rd , hwr output i/o port pf3/ lwr / adtrg / irq3 in 16-bit bus mode: lwr output in 8-bit bus mode: i/o ports also functioning as interrupt input pin ( irq3 ) and a/d converter input ( adtrg ) i/o ports also functioning as interrupt input pin ( irq3 ) and a/d converter input ( adtrg ) pf2/ wait when waite = 0 (after reset): i/o port when waite = 1: wait input i/o port pf1/ back /buzz pf0/ breq / irq2 when brle = 0 (after reset): i/o ports also functioning as wdt output pin (buzz) and interrupt input pin ( irq2 ) when brle = 1: breq input, back output, and interrupt input pin ( irq2 ) i/o ports also functioning as wdt output pin (buzz) and interrupt input pin ( irq2 ) port g 5-bit i/o port schmitt-triggered input ( irq7 , irq6 ) pg4/ cs0 pg3/ cs1 pg2/ cs2 pg1/ cs3 / irq7 when ddr = 0 * 1 : input port when ddr = 1 * 2 : cs0 output when ddr = 0 (after reset): input ports also functioning as interrupt input pin ( irq7 ) when ddr = 1: cs1 , cs2 , cs3 output and interrupt input pin ( irq7 ) i/o port i/o ports also functioning as interrupt input pin ( irq7 ) pg0/ irq6 i/o port also functioning as interrupt input pin ( irq6 ) i/o port also functioning as interrupt input pin ( irq6 ) notes: 1. after mode 6 reset 2. after mode 4 or 5 reset
214 table 9-1 (b) h8s/2227 series port functions port description pins mode 4 mode 5 mode 6 mode 7 port 1 8-bit i/o port ?schmitt-triggered input ( irq0 , irq1 ) p17/tiocb2/tclkd p16/tioca2/ irq1 p15/tiocb1/tclkc p14/tioca1/ irq0 p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 p10/tioca0/a20 8-bit i/o port also functioning as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, tiocb2), interrupt input pins ( irq0 , irq1 ), and address output (a20 to a23) 8-bit i/o port also functioning as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, tiocb2) and interrupt input pins ( irq0 , irq1 ) port 3 7-bit i/o port open-drain output capability schmitt-triggered input ( irq4 , irq5 ) p36 p35/sck1/ irq5 p34/rxd1 p33/txd1 p32/sck0/ irq4 p31/rxd0 p30/txd0 7-bit i/o port also functioning as sci (channel 0 and 1) i/o pins (txd0, rxd0, sck0, txd1, rxd1, sck1) and interrupt input pins ( irq4 , irq5 ) port 4 8-bit input port p47/an7 p46/an6 p45/an5 p44/an4 p43/an3 p42/an2 p41/an1 p40/an0 8-bit input port also functioning as a/d converter analog input (an7 to an0) port 7 8-bit i/o port p77/txd3 p77/rxd3 p75/sck3 p74/ mres 8-bit i/o port also functioning as sci (channel 3) i/o pins (txd3, rxd3, sck3), manual reset pin ( mres ), and 8-bit timer (channel 0 and 1) i/o pins (tmri01, tmci01, tmo0, tmo1) p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci01/ cs4 when ddr = 0: input ports also functioning as 8-bit timer (channel 0 and 1) i/o pins (tmri01, tmci01, tmo0, tmo1) when ddr = 1: dual function as 8-bit timer (channel 0 and 1) i/o pins (tmri01, tmci01, tmo0, tmo1) and cs7 to cs4 output port 9 2-bit input port p97 p96 2-bit input port port a 4-bit i/o port built-in mos input pull-up open-drain output capability pa3/a19 to pa0/a16 4-bit i/o port also functioning as address output (a19 to a16) 4-bit i/o port port b 8-bit i/o port built-in mos input pull-up pb7/a15 to pb0/a8 8-bit i/o port also functioning as address output (a15 to a8) 8-bit i/o port
215 table 9-1 (b) h8s/2227 series port functions (cont) port description pins mode 4 mode 5 mode 6 mode 7 port c 8-bit i/o port built-in mos input pull-up pc7/a7 to pc0/a0 address output (a7 to a0) when ddr = 0: input port when ddr = 1: address output 8-bit i/o port port d 8-bit i/o port built-in mos input pull-up pd7/d15 to pd0/d8 data bus input/output i/o port port e 8-bit i/o port built-in mos input pull-up pe7/d7 to pe0/d0 in 8-bit bus mode: i/o port in 16-bit bus mode: data bus input/output i/o port port f 8-bit i/o port schmitt-triggered input ( irq3 , irq2 ) pf7/ when ddr = 0: input port when ddr = 1 (after reset): ?output when ddr = 0 (after reset): input port when ddr = 1: output pf6/ as pf5/ rd pf4/ hwr as , rd , hwr output i/o port pf3/ lwr / adtrg / irq3 in 16-bit bus mode: lwr output in 8-bit bus mode: i/o ports also functioning as interrupt input pin ( irq3 ) and a/d converter input ( adtrg ) i/o ports also functioning as interrupt input pin ( irq3 ) and a/d converter input ( adtrg ) pf2/ wait when waite = 0 (after reset): i/o port when waite = 1: wait input i/o port pf1/ back /buzz pf0/ breq / irq2 when brle = 0 (after reset): i/o ports also functioning as wdt output pin (buzz) and interrupt input pin ( irq2 ) when brle = 1: breq input, back output, and interrupt input pin ( irq2 ) i/o ports also functioning as wdt output pin (buzz) and interrupt input pin ( irq2 ) port g 5-bit i/o port schmitt-triggered input ( irq7 , irq6 ) pg4/ cs0 pg3/ cs1 pg2/ cs2 pg1/ cs3 / irq7 when ddr = 0 * 1 : input port when ddr = 1 * 2 : cs0 output when ddr = 0 (after reset): input ports also functioning as interrupt input pin ( irq7 ) when ddr = 1: cs1 , cs2 , cs3 output and interrupt input pin ( irq7 ) i/o port i/o ports also functioning as interrupt input pin ( irq7 ) pg0/ irq6 i/o port also functioning as interrupt input pin ( irq6 ) i/o port also functioning as interrupt input pin ( irq6 ) notes: 1. after mode 6 reset 2. after mode 4 or 5 reset
216 9.2 port 1 9.2.1 overview port 1 is an 8-bit i/o port. port 1 pins also function as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2), external interrupt pins ( irq0 and irq1 ), and address bus output pins (a23 to a20). port 1 pin functions depend on the operating mode. the interrupt input pins ( irq0 and irq1 ) are schmitt-triggered inputs. figure 9-1 shows the port 1 pin configuration. p17 p16 p15 p14 p13 p12 p11 p10 (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) /tiocb2 /tioca2 /tiocb1 /tioca1 /tiocd0 /tiocc0 /tiocb0 /tioca0 /tclkd (input) /tclkc (input) /tclkb (input)/ /tclka (input)/ port 1 pins: pin functions in modes 4 to 6 /irq1 (input) /irq0 (input) a23 (output) a22 (output) /a21 (output) /a20 (output) p17 p16 p15 p14 p13 p12 p11 p10 (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) /tiocb2 /tioca2 /tiocb1 /tioca1 /tiocd0 /tiocc0 /tiocb0 /tioca0 /tclkd /tclkc (input) /tclkb (input) /tclka (input) (input) pin functions in mode 7 /irq1 (input) /irq0 (input) port 1 figure 9-1 port 1 pin functions
217 9.2.2 register configuration table 9-2 shows the port 1 register configuration. table 9-2 port 1 registers name abbreviation r/w initial value address * port 1 data direction register p1ddr w h'00 h'fe30 port 1 data register p1dr r/w h'00 h'ff00 port 1 register port1 r undefined h'ffb0 note: * lower 16 bits of the address. (1) port 1 data direction register (p1ddr) 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 0 p10ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w bit initial value read/write p1ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 1. p1ddr cannot be read; if it is, an undefined value will be read. p1ddr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. as the tpu is initialized by a manual reset, the pin states in this case are determined by the p1ddr and p1dr specifications. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. (a) modes 4, 5, and 6 if address output is enabled by the setting of bits ae3 to ae0 in pfcr, pins p13 to p10 are address outputs. pins p17 to p14, and pins p13 to p10 when address output is disabled, are output ports when the corresponding p1ddr bits are set to 1, and input ports when the corresponding p1ddr bits are cleared to 0. (b) mode 7 setting a p1ddr bit to 1 makes the corresponding port 1 pin an output port, while clearing the bit to 0 makes the pin an input port.
218 (2) port 1 data register (p1dr) 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 0 p10dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w bit initial value read/write p1dr is an 8-bit readable/writable register that stores output data for the port 1 pins (p17 to p10). p1dr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port 1 register (port1) 7 p17 * r 6 p16 * r 5 p15 * r 4 p14 * r 3 p13 * r 0 p10 * r 2 p12 * r 1 p11 * r bit initial value read/write note: * determined by the state of pins p17 to p10. port1 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 1 pins (p17 to p10) must always be performed on p1dr. if a port 1 read is performed while p1ddr bits are set to 1, the p1dr values are read. if a port 1 read is performed while p1ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port1 contents are determined by the pin states, as p1ddr and p1dr are initialized. port1 retains its previous state after a manual reset and in software standby mode.
219 9.2.3 pin functions port 1 pins also function as tpu i/o pins (tclka, tclkb, tclkc, tclkd, tioca0, tiocb0, tiocc0, tiocd0, tioca1, tiocb1, tioca2, and tiocb2), external interrupt input pins ( irq0 and irq1 ), and address output pins (a23 to a20). port 1 pin functions are shown in table 9-3. table 9-3 port 1 pin functions pin pin functions and selection method p17/ tiocb2/ tclkd the pin function is switched as shown below according to the combination of the tpu channel 2 settings (bits md3 to md0 in tmdr2, bits iob3 to iob0 in tior2, and bits cclr1 and cclr0 in tcr2), bits tpsc2 to tpsc0 in tcr0 and tcr5, and bit p17ddr. tpu channel 2 settings (1) in table below (2) in table below p17ddr 0 1 pin function tiocb2 output p17 input p17 output tiocb2 input * 1 tclkd input * 2 notes: 1. tiocb2 input when md3 to md0 = b'0000 or b'01xx and iob3 = 1. 2. tclkd input when the setting for either tcr0 or tcr5 is: tpsc2 to tpsc0 = b'111. also, tclkd input when channels 2 and 4 are set to phase counting mode. tpu channel 2 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: don? care
220 table 9-3 port 1 pin functions (cont) pin pin functions and selection method p16/ tioca2/ irq1 the pin function is switched as shown below according to the combination of the tpu channel 2 settings (bits md3 to md0 in tmdr2, bits ioa3 to ioa0 in tior2, and bits cclr1 and cclr0 in tcr2) and bit p16ddr. tpu channel 2 settings (1) in table below (2) in table below p16ddr 0 1 pin function tioca2 output p16 input p16 output tioca2 input * 1 irq1 input * 2 notes: 1. tioca2 input when md3 to md0 = b'0000 or b'01xx and ioa3 = 1. 2. when used as an external interrupt pin, do not use for another function. tpu channel 2 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm mode 1 output * 3 pwm mode 2 output x: don? care note: 3. output is disabled for tiocb2.
221 table 9-3 port 1 pin functions (cont) pin pin functions and selection method p15/ tiocb1/ tclkc the pin function is switched as shown below according to the combination of the tpu channel 1 settings (bits md3 to md0 in tmdr1, bits iob3 to iob0 in tior1, and bits cclr1 and cclr0 in tcr1), bits tpsc2 to tpsc0 in tcr0, tcr2, tcr4, and tcr5, and bit p15ddr. tpu channel 1 settings (1) in table below (2) in table below p15ddr 0 1 pin function tiocb1 output p15 input p15 output tiocb1 input * 1 tclkc input * 2 notes: 1. tiocb1 input when md3 to md0 = b'0000 or b'01xx and iob3 to iob0 = b'10xx. 2. tclkc input when the setting for either tcr0 or tcr2 is: tpsc2 to tpsc0 = b'110, or the setting for either tcr4 or tcr5 is: tpsc2 to tpsc0 = b'101. also, tclkc input when channels 2 and 4 are set to phase counting mode. tpu channel 1 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr1, cclr0 other than b'10 b'10 output function output compare output pwm mode 2 output x: don? care
222 table 9-3 port 1 pin functions (cont) pin pin functions and selection method p14/ tioca1/ irq0 the pin function is switched as shown below according to the combination of the tpu channel 1 settings (bits md3 to md0 in tmdr1, bits ioa3 to ioa0 in tior1, and bits cclr1 and cclr0 in tcr1) and bit p14ddr. tpu channel 1 settings (1) in table below (2) in table below p14ddr 0 1 pin function tioca1 output p14 input p14 output tioca1 input * 1 irq0 input * 2 notes: 1. tioca1 input when md3 to md0 = b'0000 or b'01xx and ioa3 to ioa0= b'10xx. 2. when used as an external interrupt pin, do not use for another function. tpu channel 1 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000, b'01xx b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr1, cclr0 other than b'01 b'01 output function output compare output pwm mode 1 output * 3 pwm mode 2 output x: don? care note: 3. output is disabled for tiocb1.
223 table 9-3 port 1 pin functions (cont) pin pin functions and selection method p13/ tiocd0/ tclkb/ a23 the pin function is switched as shown below according to the combination of the operating mode, the tpu channel 0 settings (bits md3 to md0 in tmdr0, bits iod3 to iod0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr2, bits ae3 to ae0 in pfcr, and bit p13ddr. operating mode modes 4, 5, 6 mode 7 ae3 to ae0 other than b'1111 b'1111 tpu channel 0 settings (1) in table below (2) in table below (1) in table below (2) in table below p13ddr 0 1 0 1 pin function tiocd0 output p13 input p13 output tiocd0 output p13 input p13 output tiocd0 input * 1 tiocd0 input * 1 tclkb input * 2 a23 output tclkb input * 2 notes: 1. tiocd0 input when md3 to md0 = b'0000 and iod3 to iod0 = b'10xx. 2. tclkb input when the setting for any of tcr0 to tcr2 is: tpsc2 to tpsc0 = b'101. also, tclkb input when channels 1 and 5 are set to phase counting mode. tpu channel 0 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iod3 to iod0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'110 b'110 output function output compare output pwm mode 2 output x: don? care
224 table 9-3 port 1 pin functions (cont) pin pin functions and selection method p12/ tiocc0/ tclka/ a22 the pin function is switched as shown below according to the combination of the operating mode, the tpu channel 0 settings (bits md3 to md0 in tmdr0, bits ioc3 to ioc0 in tior0l, and bits cclr2 to cclr0 in tcr0), bits tpsc2 to tpsc0 in tcr0 to tcr5, bits ae3 to ae0 in pfcr, and bit p12ddr. operating mode modes 4, 5, 6 mode 7 ae3 to ae0 other than b'1111 b'1111 tpu channel 0 settings (1) in table below (2) in table below (1) in table below (2) in table below p12ddr 0 1 0 1 pin function tiocc0 output p12 input p12 output tiocc0 output p12 input p12 output tiocc0 input * 1 tiocc0 input * 1 tclka input * 2 a22 output tclka input * 2 notes: 1. tiocc0 input when md3 to md0 = b'0000 and ioc3 to ioc0 = b'10xx. 2. tclka input when the setting for any of tcr0 to tcr5 is: tpsc2 to tpsc0 = b'100. also, tclka input when channels 1 and 5 are set to phase counting mode. tpu channel 0 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioc3 to ioc0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr2 to cclr0 other than b'101 b'101 output function output compare output pwm mode 1 output * 3 pwm mode 2 output x: don? care note: 3. output is disabled for tiocd0. when bfa = 1 or bfb = 1 in tmdr0, output is disabled and the settings in (2) apply.
225 table 9-3 port 1 pin functions (cont) pin pin functions and selection method p11/ tiocb0/ a21 the pin function is switched as shown below according to the combination of the operating mode, the tpu channel 0 settings (bits md3 to md0 in tmdr0 and bits iob3 to iob0 in tior0h), bits ae3 to ae0 in pfcr, and bit p11ddr. operating mode modes 4, 5, 6 mode 7 ae3 to ae0 other than b'111x b'111x tpu channel 0 settings (1) in table below (2) in table below (1) in table below (2) in table below p11ddr 0 1 0 1 pin function tiocb0 output p11 input p11 output tiocb0 output p11 input p11 output tiocb0 input * 1 a21 output tiocb0 input * 1 note: 1. tiocb0 input when md3 to md0 = b'0000 and iob3 to iob0 = b'10xx. tpu channel 0 settings (2) (1) (2) (2) (1) (2) md3 to md0 b'0000 b'0010 b'0011 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'010 b'010 output function output compare output pwm mode 2 output x: don? care
226 table 9-3 port 1 pin functions (cont) pin pin functions and selection method p10/ tioca0/ a20 the pin function is switched as shown below according to the combination of the operating mode, the tpu channel 0 settings (bits md3 to md0 in tmdr0, bits ioa3 to ioa0 in tior0h, and bits cclr2 to cclr0 in tcr0), bits ae3 to ae0 in pfcr, and bit p10ddr. operating mode modes 4, 5, 6 mode 7 ae3 to ae0 other than (b'1101 or b'111x) b'1101 or b'111x tpu channel 0 settings (1) in table below (2) in table below (1) in table below (2) in table below p10ddr 0 1 0 1 pin function tioca0 output p10 input p10 output tioca0 output p10 input p10 output tioca0 input * 1 a20 output tioca0 input * 1 note: 1. tioca0 input when md3 to md0 = b'0000 and ioa3 to ioa0 = b'10xx. tpu channel 0 settings (2) (1) (2) (1) (1) (2) md3 to md0 b'0000 b'001x b'0010 b'0011 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 other than b'xx00 other than b'xx00 cclr2 to cclr0 other than b'001 b'001 output function output compare output pwm mode 1 output * 2 pwm mode 2 output x: don? care note: 2. output is disabled for tiocb0.
227 9.3 port 3 9.3.1 overview port 3 is a 7-bit i/o port. port 3 pins also function as sci i/o pins (txd0, rxd0, sck0, txd1, rxd1, and sck1) and external interrupt input pins ( irq4 and irq5 ). port 3 pin functions are the same in all operating modes. the interrupt input pins ( irq4 and irq5 ) are schmitt-triggered inputs. figure 9-2 shows the port 3 pin configuration. p36 p35 p34 p33 p32 p31 p30 (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) /sck1(input/output)/irq5 (input) /rxd1 (input) /txd1 (output) /sck0(input/output)/irq4 (input) /rxd0 (input) /txd0 (output) port 3 pins port 3 figure 9-2 port 3 pin functions 9.3.2 register configuration table 9-4 shows the port 3 register configuration. table 9-4 port 3 registers name abbreviation r/w initial value * 2 address * 1 port 3 data direction register p3ddr w h'00 h'fe32 port 3 data register p3dr r/w h'00 h'ff02 port 3 register port3 r h'00 h'ffb2 port 3 open-drain control register p3odr r/w h'00 h'fe46 notes: 1. lower 16 bits of the address. 2. value of bits 6 to 0.
228 (1) port 3 data direction register (p3ddr) 7 undefined 6 p36ddr 0 w 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 0 p30ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w bit initial value read/write p3ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. p3ddr cannot be read; if it is, an undefined value will be returned. bit 7 is reserved; this bit cannot be modified and will return an undefined value if read. setting a p3ddr bit to 1 makes the corresponding port 3 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p3ddr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. as the sci is initialized by a manual reset, the pin states in this case are determined by the p3ddr and p3dr specifications. (2) port 3 data register (p3dr) 7 undefined 6 p36dr 0 r/w 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 0 p30dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w bit initial value read/write p3dr is an 8-bit readable/writable register that stores output data for the port 3 pins (p36 to p30). bit 7 is reserved; this bit cannot be modified and will return an undefined value if read. p3dr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port 3 register (port3) 7 undefined 6 p36 * r 5 p35 * r 4 p34 * r 3 p33 * r 0 p30 * r 2 p32 * r 1 p31 * r bit initial value read/write note: * determined by the state of pins p36 to p30. port3 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 3 pins (p36 to p30) must always be performed on p3dr. bit 7 is reserved; this bit cannot be modified and will return an undefined value if read.
229 if a port 3 read is performed while p3ddr bits are set to 1, the p3dr values are read. if a port 3 read is performed while p3ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port3 contents are determined by the pin states, as p3ddr and p3dr are initialized. port3 retains its previous state after a manual reset and in software standby mode. (4) port 3 open-drain control register (p3odr) 7 undefined 6 p36odr 0 r/w 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 0 p30odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w bit initial value read/write p3odr is an 8-bit readable/writable register that controls the pmos on/off status for each port 3 pin (p36 to p30). bit 7 is reserved; this bit cannot be modified and will return an undefined value if read. setting a p3odr bit to 1 makes the corresponding port 3 pin an nmos open-drain output pin, while clearing the bit to 0 makes the pin a cmos output pin. p3odr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode.
230 9.3.3 pin functions port 3 pins also function as sci i/o pins (txd0, rxd0, sck0, txd1, rxd1, and sck1) and interrupt input pins ( irq4 and irq5 ). port 3 pin functions are shown in table 9-5. table 9-5 port 3 pin functions pin pin functions and selection method p36 the pin function is switched as shown below according to the setting of the p36ddr bit. p36ddr 0 1 pin function p36 input p36 output * note: * nmos open-drain output when p36odr = 1. p35/sck1/ irq5 the pin function is switched as shown below according to the combination of bit c/ a in smr of sci1, bits cke0 and cke1 in scr, and bit p35ddr. cke1 0 1 c/ a 01 cke0 0 1 p35ddr 0 1 pin function p35 input p35 output * 1 sck1 output * 1 sck1 output * 1 sck1 input irq5 input * 2 notes: 1. nmos open-drain output when p35odr = 1. 2. when used as an external interrupt pin, do not use for another function. p34/rxd1 the pin function is switched as shown below according to the combination of bit re in scr of sci1 and bit p34ddr. re 0 1 p34ddr 0 1 pin function p34 input p34 output * rxd1 input note: * nmos open-drain output when p34odr = 1.
231 table 9-5 port 3 pin functions (cont) pin pin functions and selection method p33/txd1 the pin function is switched as shown below according to the combination of bit te in scr of sci1 and bit p33ddr. te 0 1 p33ddr 0 1 pin function p33 input p33 output * txd1 output * note: * nmos open-drain output when p33odr = 1. p32/sck0/ irq4 the pin function is switched as shown below according to the combination of bit c/ a in smr of sci0, bits cke0 and cke1 in scr, and bit p32ddr. cke1 0 1 c/ a 01 cke0 0 1 p32ddr 0 1 pin function p32 input p32 output * 1 sck0 output * 1 sck0 output * 1 sck0 input irq4 input * 2 notes: 1. nmos open-drain output when p32odr = 1. 2. when used as an external interrupt pin, do not use for another function. p31/rxd0 the pin function is switched as shown below according to the combination of bit re in scr of sci0 and bit p31ddr. re 0 1 p31ddr 0 1 pin function p31 input p31 output * rxd0 input note: * nmos open-drain output when p31odr = 1. p30/txd0 the pin function is switched as shown below according to the combination of bit te in scr of sci0 and bit p30ddr. te 0 1 p30ddr 0 1 pin function p30 input p30 output * txd0 output * note: * nmos open-drain output when p30odr = 1.
232 9.4 port 4 9.4.1 overview port 4 is an 8-bit input-only port. port 4 pins also function as a/d converter analog input pins (an0 to an7). port 4 pin functions are the same in all operating modes. figure 9-3 shows the port 4 pin configuration. p47 p46 p45 p44 p43 p42 p41 p40 (input) (input) (input) (input) (input) (input) (input) (input) /an7 /an6 /an5 /an4 /an3 /an2 /an1 /an0 (input) (input) (input) (input) (input) (input) (input) (input) port 4 pins port 4 figure 9-3 port 4 pin functions 9.4.2 register configuration table 9-6 shows the port 4 register configuration. port 4 is an input-only register, and does not have a data direction register or data register. table 9-6 port 4 registers name abbreviation r/w initial value address * port 4 register port4 r undefined h'ffb3 note: * lower 16 bits of the address.
233 (1) port 4 register (port4) 7 p47 * r 6 p46 * r 5 p45 * r 4 p44 * r 3 p43 * r 0 p40 * r 2 p42 * r 1 p41 * r bit initial value read/write note: * determined by the state of pins p47 to p40. port4 is an 8-bit read-only register. the pin states are always read when a port 4 read is performed. this register cannot be written to. 9.4.3 pin functions port 4 pins also function as a/d converter analog input pins (an0 to an7).
234 9.5 port 7 9.5.1 overview port 7 is an 8-bit i/o port. port 7 pins also function as 8-bit timer i/o pins (tmri01, tmci01, tmo0, and tmo1), bus control output pins ( cs4 to cs7 ), sci i/o pins (sck3, rxd3, and txd3), and the manual reset input pin ( mres ). the functions of pins p77 to p74 are the same in all operating mode, but the functions of pins p73 to p70 depend on the operating mode. figure 9-4 shows the port 7 pin configuration. p77 / txd3 p76 / rxd3 p75 /sck3 p74 /mres p73 / tmo1/cs7 p72 / tmo0/cs6 p71 / cs5 p70 / tmri01/tmci01/cs4 p77 p76 p75 p74 p73 p72 p71 p70 (input/output) (input/output) (input/output) (input/output) (input)/tmo1 (output)/cs7 (output) (input)/tmo0 (output)/cs6 (output) (input)/cs5 (output) (input)/tmri01 (input)/tmci01 (input)/cs4 (output) /txd3 (output) /rxd3 (input) /sck3 (input/output) /mres (input) port 7 pins pin functions in modes 4 to 6 p77 p76 p75 p74 p73 p72 p71 p70 (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) /txd3 (output) /rxd3 (input) /sck3 (input/output) /mres (input) /tmo1 (output) /tmo0 (output) /tmri01 (input)/tmci01 (input) pin functions in mode 7 port 7 figure 9-4 port 7 pin functions
235 9.5.2 register configuration table 9-7 shows the port 7 register configuration. table 9-7 port 7 registers name abbreviation r/w initial value address * port 7 data direction register p7ddr w h'00 h'fe36 port 7 data register p7dr r/w h'00 h'ff06 port 7 register port7 r undefined h'ffb6 note: * lower 16 bits of the address. (1) port 7 data direction register (p7ddr) 7 p77ddr 0 w 6 p76ddr 0 w 5 p75ddr 0 w 4 p74ddr 0 w 3 p73ddr 0 w 0 p70ddr 0 w 2 p72ddr 0 w 1 p71ddr 0 w bit initial value read/write p7ddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 7. p7ddr cannot be read; if it is, an undefined value will be read. setting a p7ddr bit to 1 makes the corresponding port 7 pin an output pin, while clearing the bit to 0 makes the pin an input pin. p7ddr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. as the 8-bit timer and sci are initialized by a manual reset, the pin states in this case are determined by the p7ddr and p7dr specifications. (2) port 7 data register (p7dr) 7 p77dr 0 r/w 6 p76dr 0 r/w 5 p75dr 0 r/w 4 p74dr 0 r/w 3 p73dr 0 r/w 0 p70dr 0 r/w 2 p72dr 0 r/w 1 p71dr 0 r/w bit initial value read/write p7dr is an 8-bit readable/writable register that stores output data for the port 7 pins (p77 to p70). p7dr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode.
236 (3) port 7 register (port7) 7 p77 * r 6 p76 * r 5 p75 * r 4 p74 * r 3 p73 * r 0 p70 * r 2 p72 * r 1 p71 * r bit initial value read/write note: * determined by the state of pins p77 to p70. port7 is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port 7 pins (p77 to p70) must always be performed on p7dr. if a port 7 read is performed while p7ddr bits are set to 1, the p7dr values are read. if a port 7 read is performed while p7ddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, port7 contents are determined by the pin states, as p7ddr and p7dr are initialized. port7 retains its previous state after a manual reset and in software standby mode.
237 9.5.3 pin functions port 7 pins also function as 8-bit timer i/o pins (tmri01, tmci01, tmo0, and tmo1), bus control output pins ( cs4 to cs7 ), sci i/o pins (sck3, rxd3, and txd3), and the manual reset input pin ( mres ). port 7 pin functions are shown in table 9-8. table 9-8 port 7 pin functions pin pin functions and selection method p77/txd3 the pin function is switched as shown below according to the combination of bit te in scr of sci3 and bit p77ddr. te 0 1 p77ddr 0 1 pin function p77 input p77 output txd3 output p76/rxd3 the pin function is switched as shown below according to the combination of bit re in scr of sci3 and bit p76ddr. re 0 1 p76ddr 0 1 pin function p76 input p76 output rxd3 output p75/sck3 the pin function is switched as shown below according to the combination of bit c/ a in smr of sci3, bits cke0 and cke1 of scr, and bit p75ddr. cke1 0 1 c/ a 01 cke0 0 1 p75ddr 0 1 pin function p75 input p75 output sck3 output sck3 output sck3 input
238 table 9-8 port 7 pin functions (cont) pin pin functions and selection method p74/ mres the pin function is switched as shown below according to the combination of bit mrese in syscr and bit p74ddr. mrese 0 1 p74ddr 0 1 0 pin function p74 input p74 output mres input p73/tmo1/ cs7 the pin function is switched as shown below according to the combination of the operating mode, bits os3 to os0 in tcsr1 of the 8-bit timer, and bit p73ddr. operating mode modes 4, 5, 6 mode 7 os3 to os0 all 0 not all 0 all 0 not all 0 p73ddr 0 1 0 1 pin function p73 input cs7 output tmo1 output p73 input p73 output tmo1 output p72/tmo0/ cs6 the pin function is switched as shown below according to the combination of the operating mode, bits os3 to os0 in tcsr0 of the 8-bit timer, and bit p72ddr. operating mode modes 4, 5, 6 mode 7 os3 to os0 all 0 not all 0 all 0 not all 0 p72ddr 0 1 0 1 pin function p72 input cs6 output tmo0 output p72 input p72 output tmo0 output p71/ cs5 the pin function is switched as shown below according to the combination of the operating mode and bit p71ddr. operating mode modes 4, 5, 6 mode 7 p71ddr 0101 pin function p71 input cs5 output p71 input p71 output the pin function is switched as shown below according to the combination of the operating mode and bit p70ddr. operating mode modes 4, 5, 6 mode 7 p70ddr 0101 pin function p70 input cs4 output p70 input p70 output tmri01/tmci01 input p70/ tmri01/ tmci01/ cs4
239 9.6 port 9 9.6.1 overview port 9 is a 2-bit input-only port. port 9 pins also function as d/a converter analog output pins (da0 and da1). port 9 pin functions are the same in all operating modes. figure 9-5 shows the port 9 pin configuration. p97 (input)/da1(output) p96 (input)/da0(output) port 9 pins port 9 figure 9-5 port 9 pin functions 9.6.2 register configuration table 9-9 shows the port 9 register configuration. port 9 is an input-only register, and does not have a data direction register or data register. table 9-9 port 9 registers name abbreviation r/w initial value address * port 9 register port9 r undefined h'ffb8 note: * lower 16 bits of the address. (1) port 9 register (port9) 7 p97 * r 6 p96 * r 5 r 4 r 3 r 0 r 2 r 1 r bit initial value read/write note: * determined by the state of pins p97 to p96. port9 is an 8-bit read-only register. the pin states are always read when a port 9 read is performed. this register cannot be written to. bits 5 to 0 are reserved, and will return an undefined value if read.
240 9.6.3 pin functions port 9 pins also function as d/a converter analog output pins (da0 and da1). 9.7 port a 9.7.1 overview port a is an 8-bit i/o port. port a pins also function as address bus outputs and sci2 i/o pins (sck2, rxd2, and txd2). the pin functions depend on the operating mode. port a has a built-in mos input pull-up function that can be controlled by software. figure 9-6 shows the port a pin configuration. pa3/a19/sck2 pa2/ a18/rxd2 pa1/ a17/txd2 pa0/ a16 pa3 (input/output) pa2 (input/output) pa1 (input/output) pa0 (input/output) /sck2 (input/output) /rxd2 (input) /txd2 (output) port a pins pin functions in mode 7 pa3 (input/output) pa2 (input/output) pa1 (input/output) pa0 (input/output)/a16 (output) /a19 (output) /a18 (output) /a17 (output) /sck2 (input/output) /rxd2 (input) /txd2 (output) pin functions in modes 4, 5, and 6 port a figure 9-6 port a pin functions
241 9.7.2 register configuration table 9-10 shows the port a register configuration. table 9-10 port a registers name abbreviation r/w initial value * 2 address * 1 port a data direction register paddr w h'0 h'fe39 port a data register padr r/w h'0 h'ff09 port a register porta r undefined h'ffb9 port a mos pull-up control register papcr r/w h'0 h'fe40 port a open-drain control register paodr r/w h'0 h'fe47 notes: 1. lower 16 bits of the address. 2. value of bits 3 to 0. (1) port a data direction register (paddr) 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3ddr 0 w 0 pa0ddr 0 w 2 pa2ddr 0 w 1 pa1ddr 0 w bit initial value read/write paddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port a. paddr cannot be read; if it is, an undefined value will be read. bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. paddr is initialized to h'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high- impedance when a transition is made to software standby mode. (a) modes 4, 5, and 6 if address output is enabled by the setting of bits ae3 to ae0 in pfcr, the corresponding port a pins are address outputs. when address output is disabled, setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port. (b) mode 7 setting a paddr bit to 1 makes the corresponding port a pin an output port, while clearing the bit to 0 makes the pin an input port.
242 (2) port a data register (padr) 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3dr 0 r/w 0 pa0dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w bit initial value read/write padr is an 8-bit readable/writable register that stores output data for the port a pins (pa3 to pa0). bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. padr is initialized to h? (bits 3 to 0) by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port a register (porta) 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3 * r 0 pa0 * r 2 pa2 * r 1 pa1 * r bit initial value read/write note: * determined by the state of pins pa3 to pa0. porta is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port a pins (pa3 to pa0) must always be performed on padr. bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. if a port a read is performed while paddr bits are set to 1, the padr values are read. if a port a read is performed while paddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, porta contents are determined by the pin states, as paddr and padr are initialized. porta retains its previous state after a manual reset and in software standby mode.
243 (4) port a mos pull-up control register (papcr) 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3pcr 0 r/w 0 pa0pcr 0 r/w 2 pa2pcr 0 r/w 1 pa1pcr 0 r/w bit initial value read/write papcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port a on a bit-by-bit basis. bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. papcr is valid for port input and sci input pins. when a paddr bit is cleared to 0 (input port setting), setting the corresponding papcr bit to 1 turns on the mos input pull-up for the corresponding pin. papcr is initialized to h? (bits 3 to 0) by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (5) port a open-drain control register (paodr) 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3odr 0 r/w 0 pa0odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w bit initial value read/write paodr is an 8-bit readable/writable register that controls the pmos on/off status for each port a pin (pa3 to pa0). bits 7 to 4 are reserved; these bits cannot be modified and will return an undefined value if read. paodr is valid for port output and sci output pins. setting a paodr bit to 1 makes the corresponding port a pin an nmos open-drain output pin, while clearing the bit to 0 makes the pin a cmos output pin. paodr is initialized to h'0 (bits 3 to 0) by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. 9.7.3 pin functions port a pins also function as sci2 i/o pins (txd2, rxd2, and sck2) and address output pins (a19 to a16). port a pin functions are shown in table 9-11.
244 table 9-11 port a pin functions pin pin functions and selection method pa3/a19/ sck2 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, sci channel 2 settings, and bit pa3ddr. operating mode modes 4 to 6 ae3 to ae0 11xx other than 11xx cke1 0 1 c/a 0 1 cke0 0 1 pa3ddr 0 1 pin function a19 output pa3 input pa3 output * 1 sck2 output * 1 sck2 output * 1 sck2 input operating mode mode 7 ae3 to ae0 cke1 0 1 c/a 0 1 cke0 0 1 pa3ddr 0 1 pin function pa3 input pa3 output * 1 sck2 output * 1 sck2 output * 1 sck2 input note: 1. nmos open-drain output when pa3odr = 1 in paodr. pa2/a18/ rxd2 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, sci channel 2 settings, and bit pa2ddr. operating mode modes 4 to 6 mode 7 ae3 to ae0 1011 or 11xx other than (1011 or 11xx) re 0101 pa2ddr 0 1 0 1 pin function a18 output pa2 input pa2 output * 1 rxd2 input pa2 input pa2 output * 1 rxd2 input note: 1. nmos open-drain output when pa2odr = 1 in paodr.
245 table 9-11 port a pin functions (cont) pin pin functions and selection method pa1/a17/ txd2 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, sci channel 2 settings, and bit pa1ddr. operating mode modes 4 to 6 mode 7 ae3 to ae0 101x or 11xx other than (101x or 11xx) te 0101 pa1ddr 0 1 0 1 pin function a17 output pa1 input pa1 output * 1 txd2 output * 1 pa1 input pa1 output * 1 txd2 output * 1 note: 1. nmos open-drain output when pa1odr = 1 in paodr. pa0/a16 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, and bit pa0ddr. operating mode modes 4 to 6 mode 7 ae3 to ae0 other than (0xxx or 1000) 0xxx or 1000 pa1ddr 0101 pin function a16 output pa0 input pa0 output * 1 pa0 input pa0 output * 1 note: 1. nmos open-drain output when pa0odr = 1 in paodr.
246 9.7.4 mos input pull-up function port a has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be specified as on or off for individual bits. with port input and sci input pins, when a paddr bit is cleared to 0, setting the corresponding papcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset and in hardware standby mode. the previous state is retained after a manual reset and in software standby mode. table 9-11 summarizes the mos input pull-up states. table 9-11 mos input pull-up states (port a) pins power-on reset hardware standby mode manual reset software standby mode in other operations address output, port output, sci output off off off off off port input, sci input off off on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when paddr = 0 and papcr = 1; otherwise off.
247 9.8 port b 9.8.1 overview port b is an 8-bit i/o port. port b pins also function as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, and tiocb5) and address bus outputs. the pin functions depend on the operating mode. port b has a built-in mos input pull-up function that can be controlled by software. figure 9-7 shows the port b pin configuration. pb7/a15/tiocb5 pb6/a14/tioca5 pb5/a13/tiocb4 pb4/a12/tioca4 pb3/a11/tiocd3 pb2/a10/tiocc3 pb1/a9/tiocb3 pb0/a8/tioca3 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 (input) (input) (input) (input) (input) (input) (input) (input) /a15 /a14 /a13 /a12 /a11 /a10 /a9 /a8 /tiocb5 /tioca5 /tiocb4 /tioca4 /tiocd3 /tiocc3 /tiocb3 /tioca3 (input/output)/tiocb5 (input/output) (input/output)/tioca5 (input/output) (input/output)/tiocb4 (input/output) (input/output)/tioca4 (input/output) (input/output)/tiocd3 (input/output) (input/output)/tiocc3 (input/output) (input/output)/tiocb3 (input/output) (input/output)/tioca3 (input/output) (output) (output) (output) (output) (output) (output) (output) (output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) (input/output) port b pins pin functions in modes 4, 5, and 6 pin functions in mode 7 pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 port b figure 9-7 port b pin functions
248 9.8.2 register configuration table 9-12 shows the port b register configuration. table 9-12 port b registers name abbreviation r/w initial value address * port b data direction register pbddr w h'00 h'fe3a port b data register pbdr r/w h'00 h'ff0a port b register portb r undefined h'ffba port b mos pull-up control register pbpcr r/w h'00 h'fe41 note: * lower 16 bits of the address. (1) port b data direction register (pbddr) 7 pb7ddr 0 w 6 pb6ddr 0 w 5 pb5ddr 0 w 4 pb4ddr 0 w 3 pb3ddr 0 w 0 pb0ddr 0 w 2 pb2ddr 0 w 1 pb1ddr 0 w bit initial value read/write pbddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port b. pbddr cannot be read; if it is, an undefined value will be read. pbddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. (a) modes 4, 5, and 6 if address output is enabled by the setting of bits ae3 to ae0 in pfcr, the corresponding port b pins are address outputs. when address output is disabled, setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port. (b) mode 7 setting a pbddr bit to 1 makes the corresponding port b pin an output port, while clearing the bit to 0 makes the pin an input port.
249 (2) port b data register (pbdr) 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 0 pb0dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w bit initial value read/write pbdr is an 8-bit readable/writable register that stores output data for the port b pins (pb7 to pb0). pbdr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port b register (portb) 7 pb7 * r 6 pb6 * r 5 pb5 * r 4 pb4 * r 3 pb3 * r 0 pb0 * r 2 pb2 * r 1 pb1 * r bit initial value read/write note: * determined by the state of pins pb7 to pb0. portb is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port b pins (pb7 to pb0) must always be performed on pbdr. if a port b read is performed while pbddr bits are set to 1, the pbdr values are read. if a port b read is performed while pbddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portb contents are determined by the pin states, as pbddr and pbdr are initialized. portb retains its previous state after a manual reset and in software standby mode. (4) port b mos pull-up control register (pbpcr) 7 pb7pcr 0 r/w 6 pb6pcr 0 r/w 5 pb5pcr 0 r/w 4 pb4pcr 0 r/w 3 pb3pcr 0 r/w 0 pb0pcr 0 r/w 2 pb2pcr 0 r/w 1 pb1pcr 0 r/w bit initial value read/write pbpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port b on a bit-by-bit basis. pbpcr is valid for port input and tpu input pins.
250 when a pbddr bit is cleared to 0 (input port setting), setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pbpcr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. 9.8.3 pin functions port b pins also function as tpu i/o pins (tioca3, tiocb3, tiocc3, tiocd3, tioca4, tiocb4, tioca5, and tiocb5) and address output pins (a15 to a8). port b pin functions are shown in table 9-13.
251 table 9-13 port b pin functions pin pin functions and selection method pb7/a15/ tiocb5 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, tpu channel 5 settings (bits md3 to md0 in tmdr5, bits iob3 to iob0 in tior5, and bits cclr1 and cclr0 in tcr5) and bit pb7ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'1xxx other than b'1xxx tpu channel 5 settings (1) in table below (2) in table below pb7ddr 0 1 pin function a15 output tiocb5 output pb7 input pb7 output tiocb5 input * 1 operating mode mode 7 ae3 to ae0 in pfcr tpu channel 5 settings (1) in table below (2) in table below pb7ddr 0 1 pin function tiocb5 output pb7 input pb7 output tiocb5 input * 1 note: 1. tiocb5 input when md3 to md0 = b'0000 or b'01xx and iob3 = 1. tpu channel 5 settings (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 cclr1 to cclr0 output pin output compare output tpu channel 5 settings (2) (1) (2) md3 to md0 b'0011 iob3 to iob0 b'xx00 other than b'xx00 cclr1 to cclr0 other than b'10 b'10 output pin pwm mode 2 output
252 table 9-13 port b pin functions (cont) pin pin functions and selection method pb6/a14/ tioca5 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, tpu channel 5 settings (bits md3 to md0 in tmdr5, bits ioa3 to ioa0 in tior5, and bits cclr1 and cclr0 in tcr5) and bit pb6ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'0111 or b'1xxx other than (b'0111 or b'1xxx) tpu channel 5 settings (1) in table below (2) in table below pb6ddr 0 1 pin function a14 output tioca5 output pb6 input pb6 output tioca5 input operating mode mode 7 ae3 to ae0 in pfcr tpu channel 5 settings (1) in table below (2) in table below pb6ddr 0 1 pin function tioca5 output pb6 input pb6 output tioca5 input * 1 note: 1. tioca5 input when md3 to md0 = b'0000 or b'01xx and ioa3 = 1. tpu channel 5 settings (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 cclr1 to cclr0 output pin output compare output tpu channel 5 settings (1) (1) (2) md3 to md0 b'0010 b'0011 ioa3 to ioa0 other than b'xx00 cclr1 to cclr0 other than b'01 b'10 output pin pwm mode 1 output * 2 pwm mode 2 output note: 2. output is disabled for tioca5.
253 table 9-13 port b pin functions (cont) pin pin functions and selection method pb5/a13/ tiocb4 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, tpu channel 4 settings (bits md3 to md0 in tmdr4, bits iob3 to iob0 in tior4, and bits cclr1 and cclr0 in tcr4) and bit pb5ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'011x or b'1xxx other than (b'011x or b'1xxx) tpu channel 4 settings (1) in table below (2) in table below pb5ddr 0 1 pin function a13 output tiocb4 output pb5 input pb5 output tiocb4 input * 1 operating mode mode 7 ae3 to ae0 in pfcr tpu channel 4 settings (1) in table below (2) in table below pb5ddr 0 1 pin function tiocb4 output pb5 input pb5 output tiocb4 input * 1 note: 1. tiocb4 input when md3 to md0 = b'0000 or b'01xx and iob3 to iob0 = b'10xx. tpu channel 4 settings (2) (1) (2) md3 to md0 b'0000, b'01xx b'0010 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 cclr1 to cclr0 output pin output compare output tpu channel 4 settings (2) (1) (2) md3 to md0 b'0011 iob3 to iob0 b'xx00 other than b'xx00 cclr1 to cclr0 other than b'10 b'10 output pin pwm mode 2 output
254 table 9-13 port b pin functions (cont) pin pin functions and selection method pb4/a12/ tioca4 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, tpu channel 4 settings (bits md3 to md0 in tmdr4, bits ioa3 to ioa0 in tior4, and bits cclr1 and cclr0 in tcr4) and bit pb4ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'0100 or b'00xx other than (b'0100 or b'00xx) tpu channel 4 settings (1) in table below (2) in table below pb5ddr 0 1 pin function tioca4 output pb4 input pb4 output a12 output tioca4 input * 1 operating mode mode 7 ae3 to ae0 in pfcr tpu channel 4 settings (1) in table below (2) in table below pb4ddr 0 1 pin function tioca4 output pb4 input pb4 output tioca4 input * 1 note: 1. tioca4 input when md3 to md0 = b'0000 or b'01xx and ioa3 to ioa0 = b'10xx. tpu channel 4 settings (2) (1) (2) md3 to md0 b'0000, b'01xx b'001x ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 cclr2 to cclr0 output pin output compare output tpu channel 4 settings (1) (1) (2) md3 to md0 b'0010 b'0011 ioa3 to ioa0 other than b'xx00 cclr1 to cclr0 other than b'x01 b'x01 output pin pwm mode 1 output * 2 pwm mode 2 output note: 2. output is disabled for tiocb4.
255 table 9-13 port b pin functions (cont) pin pin functions and selection method pb3/a11/ tiocd3 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, tpu channel 3 settings (bits md3 to md0 in tmdr3, bits iod3 to iod0 in tior3l, and bits cclr2 to cclr0 in tcr3) and bit pb3ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'00xx other than b'00xx tpu channel 3 settings (1) in table below (2) in table below pb3ddr 0 1 pin function tiocd3 output pb3 input pb3 output a11 output tiocd3 input * 1 operating mode mode 7 ae3 to ae0 in pfcr tpu channel 3 settings (1) in table below (2) in table below pb3ddr 0 1 pin function tiocd3 output pb3 input pb3 output tiocd3 input * 1 note: 1. tiocd3 input when md3 to md0 = b'0000 and iod3 to iod0 = b'10xx. tpu channel 3 settings (2) (1) (2) md3 to md0 b'0000 b'0010 iod3 to iod0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 cclr2 to cclr0 output pin output compare output tpu channel 3 settings (2) (1) (2) md3 to md0 b'0011 iod3 to iod0 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'110 b'110 output pin pwm mode 2 output
256 table 9-13 port b pin functions (cont) pin pin functions and selection method pb2/a10/ tiocc3 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, tpu channel 3 settings (bits md3 to md0 in tmdr3, bits ioc3 to ioc0 in tior3l, and bits cclr2 to cclr0 in tcr3) and bit pb2ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'0010 or b'000x other than b'0010 or b'000x tpu channel 3 settings (1) in table below (2) in table below pb2ddr 0 1 pin function tiocc3 output pb2 input pb2 output a10 output tiocc3 input * 1 operating mode mode 7 ae3 to ae0 in pfcr tpu channel 3 settings (1) in table below (2) in table below pb2ddr 0 1 pin function tiocc3 output pb2 input pb2 output tiocc3 input * 1 note: 1. tiocc3 input when md3 to md0 = b'0000 and ioc3 to ioc0 = b'10xx. tpu channel 3 settings (2) (1) (2) md3 to md0 b'0000 b'001x ioc3 to ioc0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 b'xx00 cclr2 to cclr0 output pin output compare output tpu channel 3 settings (1) (1) (2) md3 to md0 b'0010 b'0011 ioc3 to ioc0 other than b'xx00 cclr2 to cclr0 other than b'101 b'101 output pin pwm mode 1 output * 2 pwm mode 2 output note: 2. output is disabled for tiocd3.
257 table 9-13 port b pin functions (cont) pin pin functions and selection method pb1/a9/ tiocb3 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, tpu channel 3 settings (bits md3 to md0 in tmdr3, bits iob3 to iob0 in tior3h, and bits cclr2 to cclr0 in tcr3) and bit pb1ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'000x other than b'000x tpu channel 3 settings (1) in table below (2) in table below pb1ddr 0 1 pin function tiocb3 output pb1 input pb1 output a9 output tiocb3 input * 1 operating mode mode 7 ae3 to ae0 in pfcr tpu channel 3 settings (1) in table below (2) in table below pb1ddr 0 1 pin function tiocb3 output pb1 input pb1 output tiocb3 input * 1 note: 1. tiocb3 input when md3 to md0 = b'0000 and iob3 to iob0 = b'10xx. tpu channel 3 settings (2) (1) (2) md3 to md0 b'0000 b'0010 iob3 to iob0 b'0000 b'0100 b'1xxx b'0001 to b'0011 b'0101 to b'0111 cclr2 to cclr0 output pin output compare output tpu channel 3 settings (2) (1) (2) md3 to md0 b'0011 iob3 to iob0 b'xx00 other than b'xx00 cclr2 to cclr0 other than b'010 b'010 output pin pwm mode 2 output
258 table 9-13 port b pin functions (cont) pin pin functions and selection method pb0/a8/ tioca3 the pin function is switched as shown below according to the combination of the operating mode, pfcr setting, tpu channel 3 settings (bits md3 to md0 in tmdr3, bits ioa3 to ioa0 in tior3h, and bits cclr2 to cclr0 in tcr3) and bit pb1ddr. operating mode modes 4 to 6 ae3 to ae0 in pfcr b'0000 other than b'0000 tpu channel 3 settings (1) in table below (2) in table below p30ddr 0 1 pin function tioca3 output pb0 input pb0 output a8 output tioca3 input * 1 operating mode mode 7 ae3 to ae0 in pfcr tpu channel 3 settings (1) in table below (2) in table below pb0ddr 0 1 pin function tioca3 output pb0 input pb0 output tioca3 input * 1 note: 1. tioca3 input when md3 to md0 = b'0000 and ioa3 to ioa0 = b'10xx. tpu channel 3 settings (2) (1) (2) md3 to md0 b'0000 b'001x ioa3 to ioa0 b'0000 b'0100 b'1xxx b'0000 to b'0011 b'0101 to b'0111 b'xx00 cclr2 to cclr0 output pin output compare output tpu channel 3 settings (1) (1) (2) md3 to md0 b'0010 b'0011 ioa3 to ioa0 other than b'xx00 cclr2 to cclr0 other than b'001 b'001 output pin pwm mode 1 output * 2 pwm mode 2 output note: 2. output is disabled for tiocb3.
259 9.8.4 mos input pull-up function port b has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be specified as on or off for individual bits. with port input and tpu input pins, when a pbddr bit is cleared to 0, setting the corresponding pbpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset and in hardware standby mode. the previous state is retained after a manual reset and in software standby mode. table 9-13 summarizes the mos input pull-up states. table 9-13 mos input pull-up states (port b) pins power-on reset hardware standby mode manual reset software standby mode in other operations address output, port output, tpu output off off off off off port input, tpu input off off on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when pbddr = 0 and pbpcr = 1; otherwise off.
260 9.9 port c 9.9.1 overview port c is an 8-bit i/o port. port c pins also function as address bus outputs. the pin functions depend on the operating mode. port c has a built-in mos input pull-up function that can be controlled by software. figure 9-8 shows the port c pin configuration. pc7/ a7 pc6/ a6 pc5/ a5 pc4/ a4 pc3/ a3 pc2/ a2 pc1/ a1 pc0/ a0 pc7 (input)/a7 (output) pc6 (input)/a6 (output) pc5 (input)/a5 (output) pc4 (input)/a4 (output) pc3 (input)/a3 (output) pc2 (input)/a2 (output) pc1 (input)/a1 (output) pc0 (input)/a0 (output) port c pins pin functions in mode 6 a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output) a0 (output) pin functions in modes 4 and 5 port c pin functions in mode 7 pc7 (input/output) pc6 (input/output) pc5 (input/output) pc4 (input/output) pc3 (input/output) pc2 (input/output) pc1 (input/output) pc0 (input/output) figure 9-8 port c pin functions
261 9.9.2 register configuration table 9-14 shows the port c register configuration. table 9-14 port c registers name abbreviation r/w initial value address * port c data direction register pcddr w h'00 h'fe3b port c data register pcdr r/w h'00 h'ff0b port c register portc r undefined h'ffbb port c mos pull-up control register pcpcr r/w h'00 h'fe42 note: * lower 16 bits of the address. (1) port c data direction register (pcddr) 7 pc7ddr 0 w 6 pc6ddr 0 w 5 pc5ddr 0 w 4 pc4ddr 0 w 3 pc3ddr 0 w 0 pc0ddr 0 w 2 pc2ddr 0 w 1 pc1ddr 0 w bit initial value read/write pcddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port c. pcddr cannot be read; if it is, an undefined value will be read. pcddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. the ope bit in sbycr is used to select whether the address output pins retain their output state or become high-impedance when a transition is made to software standby mode. (a) modes 4 and 5 port c pins are address outputs regardless of the pcddr settings. (b) mode 6 setting a pcddr bit to 1 makes the corresponding port c pin an address output, while clearing the bit to 0 makes the pin an input port. (c) mode 7 setting a pcddr bit to 1 makes the corresponding port c pin an output port, while clearing the bit to 0 makes the pin an input port.
262 (2) port c data register (pcdr) 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 0 pc0dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w bit initial value read/write pcdr is an 8-bit readable/writable register that stores output data for the port c pins (pc7 to pc0). pcdr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port c register (portc) 7 pc7 * r 6 pc6 * r 5 pc5 * r 4 pc4 * r 3 pc3 * r 0 pc0 * r 2 pc2 * r 1 pc1 * r bit initial value read/write note: * determined by the state of pins pc7 to pc0. portc is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port c pins (pc7 to pc0) must always be performed on pcdr. if a port c read is performed while pcddr bits are set to 1, the pcdr values are read. if a port c read is performed while pcddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portc contents are determined by the pin states, as pcddr and pcdr are initialized. portc retains its previous state after a manual reset and in software standby mode. (4) port c mos pull-up control register (pcpcr) 7 pc7pcr 0 r/w 6 pc6pcr 0 r/w 5 pc5pcr 0 r/w 4 pc4pcr 0 r/w 3 pc3pcr 0 r/w 0 pc0pcr 0 r/w 2 pc2pcr 0 r/w 1 pc1pcr 0 r/w bit initial value read/write pcpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port c on a bit-by-bit basis. pcpcr is valid for port input (modes 6 and 7).
263 when a pcddr bit is cleared to 0 (input port setting), setting the corresponding pcpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pcpcr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. 9.9.3 pin functions in each mode (1) modes 4 and 5 in modes 4 and 5, port c pins function as address outputs automatically. port c pin functions in modes 4 and 5 are shown in figure 9-9. a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output) a0 (output) port c figure 9-9 port c pin functions (modes 4 and 5)
264 (2) mode 6 in mode 6, port c pins function as address outputs or input ports, and input or output can be specified bit by bit. setting a pcddr bit to 1 makes the corresponding port c pin an address output, while clearing the bit to 0 makes the pin an input port. port c pin functions in mode 6 are shown in figure 9-10. a7 (output) a6 (output) a5 (output) a4 (output) a3 (output) a2 (output) a1 (output) a0 (output) pc7 (input) pc6 (input) pc5 (input) pc4 (input) pc3 (input) pc2 (input) pc1 (input) pc0 (input) when pcddr = 1 when pcddr = 0 port c figure 9-10 port c pin functions (mode 6) (3) mode 7 in mode 7, port c functions as an i/o port, and input or output can be specified bit by bit. setting a pcddr bit to 1 makes the corresponding port c pin an output port, while clearing the bit to 0 makes the pin an input port. port c pin functions in mode 7 are shown in figure 9-11. pc7 (input/output) pc6 (input/output) pc5 (input/output) pc4 (input/output) pc3 (input/output) pc2 (input/output) pc1 (input/output) pc0 (input/output) port c figure 9-11 port c pin functions (mode 7)
265 9.9.4 mos input pull-up function port c has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be used in modes 6 and 7, and can be specified as on or off for individual bits. with the port input pin function (modes 6 and 7), when a pcddr bit is cleared to 0, setting the corresponding pcpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset and in hardware standby mode. the previous state is retained after a manual reset and in software standby mode. table 9-15 summarizes the mos input pull-up states. table 9-15 mos input pull-up states (port c) pins power-on reset hardware standby mode manual reset software standby mode in other operations address output (modes 4 and 5), port output (modes 6 and 7) off off off off off port input (modes 6 and 7) off off on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when pcddr = 0 and pcpcr = 1; otherwise off.
266 9.10 port d 9.10.1 overview port d is an 8-bit i/o port. port d pins also function as data bus input/output pins. the pin functions depend on the operating mode. port d has a built-in mos input pull-up function that can be controlled by software. figure 9-12 shows the port d pin configuration. pd7/ d15 pd6/ d14 pd5/ d13 pd4/ d12 pd3/ d11 pd2/ d10 pd1/ d9 pd0/ d8 d15 (input/output) d14 (input/output) d13 (input/output) d12 (input/output) d11 (input/output) d10 (input/output) d9 (input/output) d8 (input/output) port d pin pin functions in modes 4 to 6 pd7 (input/output) pd6 (input/output) pd5 (input/output) pd4 (input/output) pd3 (input/output) pd2 (input/output) pd1 (input/output) pd0 ( input/output ) pin functions in mode 7 port d figure 9-12 port d pin functions
267 9.10.2 register configuration table 9-16 shows the port d register configuration. table 9-16 port d registers name abbreviation r/w initial value address * port d data direction register pdddr w h'00 h'fe3c port d data register pddr r/w h'00 h'ff0c port d register portd r undefined h'ffbc port d mos pull-up control register pdpcr r/w h'00 h'fe43 note: * lower 16 bits of the address. (1) port d data direction register (pdddr) 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 0 pd0ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w bit initial value read/write pdddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port d. pdddr cannot be read; if it is, an undefined value will be read. pdddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (a) modes 4 to 6 the input/output direction settings in pdddr are ignored, and port d pins automatically function as data input/output pins. (b) mode 7 setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port.
268 (2) port d data register (pddr) 7 pd7dr 0 r/w 6 pd6dr 0 r/w 5 pd5dr 0 r/w 4 pd4dr 0 r/w 3 pd3dr 0 r/w 0 pd0dr 0 r/w 2 pd2dr 0 r/w 1 pd1dr 0 r/w bit initial value read/write pddr is an 8-bit readable/writable register that stores output data for the port d pins (pd7 to pd0). pddr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port d register (portd) 7 pd7 * r 6 pd6 * r 5 pd5 * r 4 pd4 * r 3 pd3 * r 0 pd0 * r 2 pd2 * r 1 pd1 * r bit initial value read/write note: * determined by the state of pins pd7 to pd0. portd is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port d pins (pd7 to pd0) must always be performed on pddr. if a port d read is performed while pdddr bits are set to 1, the pddr values are read. if a port d read is performed while pdddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portd contents are determined by the pin states, as pdddr and pddr are initialized. portd retains its previous state after a manual reset and in software standby mode. (4) port d mos pull-up control register (pdpcr) 7 pd7pcr 0 r/w 6 pd6pcr 0 r/w 5 pd5pcr 0 r/w 4 pd4pcr 0 r/w 3 pd3pcr 0 r/w 0 pd0pcr 0 r/w 2 pd2pcr 0 r/w 1 pd1pcr 0 r/w bit initial value read/write pdpcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port d on a bit-by-bit basis.
269 pdpcr is valid for port input pins (mode 7). when a pdddr bit is cleared to 0 (input port setting), setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for the corresponding pin. pdpcr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. 9.10.3 pin functions in each mode (1) modes 4 to 6 in modes 4 to 6, port d pins function as data input/output pins automatically. port d pin functions in modes 4 to 6 are shown in figure 9-13. d15 (input/output) d14 (input/output) d13 (input/output) d12 (input/output) d11 (input/output) d10 (input/output) d9 (input/output) d8 (input/output) port d figure 9-13 port d pin functions (modes 4 to 6) (2) mode 7 in mode 7, port d functions as an i/o port, and input or output can be specified bit by bit. setting a pdddr bit to 1 makes the corresponding port d pin an output port, while clearing the bit to 0 makes the pin an input port. port d pin functions in mode 7 are shown in figure 9-14.
270 pd7 (input/output) pd6 (input/output) pd5 (input/output) pd4 (input/output) pd3 (input/output) pd2 (input/output) pd1 (input/output) pd0 (input/output) port d figure 9-14 port d pin functions (mode 7) 9.10.4 mos input pull-up function port d has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be used in mode 7, and can be specified as on or off for individual bits. with the port input pin function (mode 7), when a pdddr bit is cleared to 0, setting the corresponding pdpcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset and in hardware standby mode. the previous state is retained after a manual reset and in software standby mode. table 9-17 summarizes the mos input pull-up states. table 9-17 mos input pull-up states (port d) pins power-on reset hardware standby mode manual reset software standby mode in other operations data input/output (modes 4 to 6), port output (mode 7) off off off off off port input (mode 7) off off on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when pdddr = 0 and pdpcr = 1; otherwise off.
271 9.11 port e 9.11.1 overview port e is an 8-bit i/o port. port e pins also function as data bus input/output pins. the pin functions depend on the operating mode and on whether 8-bit or 16-bit bus mode is used. port e has a built-in mos input pull-up function that can be controlled by software. figure 9-15 shows the port e pin configuration. pe7/ d7 pe6/ d6 pe5/ d5 pe4/ d4 pe3/ d3 pe2/ d2 pe1/ d1 pe0/ d0 pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 port e pins pin functions in modes 4 to 6 pin functions in mode 7 (input/output)/d7 (input/output) (input/output)/d6 (input/output) (input/output)/d5 (input/output) (input/output)/d4 (input/output) (input/output)/d3 (input/output) (input/output)/d2 (input/output) (input/output)/d1 (input/output) (input/output)/d0 (input/output) pe7 (input/output) pe6 (input/output) pe5 (input/output) pe4 (input/output) pe3 (input/output) pe2 (input/output) pe1 (input/output) pe0 ( input/output ) port e figure 9-15 port e pin functions
272 9.11.2 register configuration table 9-18 shows the port e register configuration. table 9-18 port e registers name abbreviation r/w initial value address * port e data direction register peddr w h'00 h'fe3d port e data register pedr r/w h'00 h'ff0d port e register porte r undefined h'ffbd port e mos pull-up control register pepcr r/w h'00 h'fe44 note: * lower 16 bits of the address. (1) port e data direction register (peddr) 7 pe7ddr 0 w 6 pe6ddr 0 w 5 pe5ddr 0 w 4 pe4ddr 0 w 3 pe3ddr 0 w 0 pe0ddr 0 w 2 pe2ddr 0 w 1 pe1ddr 0 w bit initial value read/write peddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port e. peddr cannot be read; if it is, an undefined value will be read. peddr is initialized to h'00 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (a) modes 4 to 6 when 8-bit bus mode is selected, port e functions as an i/o port. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode is selected, the input/output direction settings in peddr are ignored, and port e pins automatically function as data input/output pins. for details of the 8-bit and 16-bit bus modes, see section 7, bus controller. (b) mode 7 setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port.
273 (2) port e data register (pedr) 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 0 pe0dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w bit initial value read/write pedr is an 8-bit readable/writable register that stores output data for the port e pins (pe7 to pe0). pedr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port e register (porte) 7 pe7 * r 6 pe6 * r 5 pe5 * r 4 pe4 * r 3 pe3 * r 0 pe0 * r 2 pe2 * r 1 pe1 * r bit initial value read/write note: * determined by the state of pins pe7 to pe0. porte is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port e pins (pe7 to pe0) must always be performed on pedr. if a port e read is performed while peddr bits are set to 1, the pedr values are read. if a port e read is performed while peddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, porte contents are determined by the pin states, as peddr and pedr are initialized. porte retains its previous state after a manual reset and in software standby mode. (4) port e mos pull-up control register (pepcr) 7 pe7pcr 0 r/w 6 pe6pcr 0 r/w 5 pe5pcr 0 r/w 4 pe4pcr 0 r/w 3 pe3pcr 0 r/w 0 pe0pcr 0 r/w 2 pe2pcr 0 r/w 1 pe1pcr 0 r/w bit initial value read/write pepcr is an 8-bit readable/writable register that controls the mos input pull-up function incorporated into port e on a bit-by-bit basis. pepcr is valid for port input pins (modes 4 to 6 in 8-bit bus mode, or mode 7).
274 when a peddr bit is cleared to 0 (input port setting), setting the corresponding pepcr bit to 1 turns on the mos input pull-up for the corresponding pin. pepcr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. 9.11.3 pin functions in each mode (1) modes 4 to 6 in modes 4 to 6, if 8-bit access space is designated and 8-bit bus mode is selected, port e functions as an i/o port. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. when 16-bit bus mode is selected, the input/output direction settings in peddr are ignored, and port e pins function as data input/output pins. port e pin functions in modes 4 to 6 are shown in figure 9-16. pe7 (input/output) pe6 (input/output) pe5 (input/output) pe4 (input/output) pe3 (input/output) pe2 (input/output) pe1 (input/output) pe0 (input/output) d7 (input/output) d6 (input/output) d5 (input/output) d4 (input/output) d3 (input/output) d2 (input/output) d1 (input/output) d0 (input/output) 8-bit bus mode port e 16-bit bus mode figure 9-16 port e pin functions (modes 4 to 6)
275 (2) mode 7 in mode 7, port e functions as an i/o port, and input or output can be specified bit by bit. setting a peddr bit to 1 makes the corresponding port e pin an output port, while clearing the bit to 0 makes the pin an input port. port e pin functions in mode 7 are shown in figure 9-17. pe7 (input/output) pe6 (input/output) pe5 (input/output) pe4 (input/output) pe3 (input/output) pe2 (input/output) pe1 (input/output) pe0 (input/output) port e figure 9-17 port e pin functions (mode 7) 9.11.4 mos input pull-up function port e has a built-in mos input pull-up function that can be controlled by software. mos input pull-up can be used in modes 4 to 6 in 8-bit bus mode, or in mode 7, and can be specified as on or off for individual bits. with the port input pin function (modes 4 to 6 in 8-bit bus mode, or mode 7), when a peddr bit is cleared to 0, setting the corresponding pepcr bit to 1 turns on the mos input pull-up for that pin. the mos input pull-up function is in the off state after a power-on reset and in hardware standby mode. the previous state is retained after a manual reset and in software standby mode. table 9-19 summarizes the mos input pull-up states.
276 table 9-19 mos input pull-up states (port e) pins power-on reset hardware standby mode manual reset software standby mode in other operations data input/output (modes 4 to 6 with 16-bit bus), port output (modes 4 to 6 with 8-bit bus, mode 7) off off off off off port input (modes 4 to 6 with 8-bit bus, mode 7) off off on/off on/off on/off legend: off: mos input pull-up is always off. on/off: on when peddr = 0 and pepcr = 1; otherwise off.
277 9.12 port f 9.12.1 overview port f is an 8-bit i/o port. port f pins also function as external interrupt input pins ( irq2 and irq3 ), the buzz output pin, the a/d trigger input pin ( adtrg ), bus control signal i/o pins ( as , rd , hwr , lwr , wait , breq , and back ), and the system clock (? output pin. the interrupt input pins ( irq2 and irq3 ) are schmitt-triggered inputs. figure 9-18 shows the port f pin configuration. pf7/ pf6/ as pf5/ rd pf4/ hwr pf3/ lwr/ adtrg/ irq3 pf2/ wait pf1/ back /buzz pf0/ breq/ i rq2 port f pins port f pf7 (input)/?(output) pf6 (input/output) pf5 (input/output) pf4 (input/output) pf3 (input/output)/ adtrg (input)/ irq3 (input) pf2 (input/output) pf1 (input/output) /buzz (output) pf0 (input/output)/ irq2 (input) pin functions in mode 7 pf7 as rd hwr pf3 pf2 pf1 pf0 (input)/?(output) (output) (output) (output) (input/output)/ lwr (output)/ adtrg (input)/ irq3 (input) (input/output)/wait (input) (input/output)/back (output) /buzz (output) (input/output)/breq (input)/ irq2 (input) pin functions in modes 4 to 6 figure 9-18 port f pin functions
278 9.12.2 register configuration table 9-20 shows the port f register configuration. table 9-20 port f registers name abbreviation r/w initial value address * 1 port f data direction register pfddr w h'80/h'00 * 2 h'fe3e port f data register pfdr r/w h'00 h'ff0e port f register portf r undefined h'ffbe notes: 1. lower 16 bits of the address. 2. initial value depends on the mode. (1) port f data direction register (pfddr) 7 pf7ddr 1 w 0 w 6 pf6ddr 0 w 0 w 5 pf5ddr 0 w 0 w 4 pf4ddr 0 w 0 w 3 pf3ddr 0 w 0 w 0 pf0ddr 0 w 0 w 2 pf2ddr 0 w 0 w 1 pf1ddr 0 w 0 w bit modes 4 to 6 initial value read/write mode 7 initial value read/write pfddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port f. pfddr cannot be read; if it is, an undefined value will be read.. pfddr is initialized to h'80 (modes 4 to 6) or h'00 (mode 7) by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. (a) modes 4 to 6 pin pf7 functions as the ?output pin when the corresponding pfddr bit is set to 1, and as an input port when the bit is cleared to 0. the input/output direction specification in pfddr is ignored for pins pf6 to pf3, which are automatically designated as bus control outputs ( as , rd , hwr , and lwr ). pins pf2 to pf0 are made bus control input/output pins ( wait , back , and breq ) by bus controller settings. otherwise, setting a pfddr bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port.
279 (b) mode 7 setting a pfddr bit to 1 makes the corresponding port f pin pf6 to pf0 an output port, or in the case of pin pf7, the ?output pin. clearing the bit to 0 makes the pin an input port. (2) port f data register (pfdr) 7 pf7dr 0 r/w 6 pf6dr 0 r/w 5 pf5dr 0 r/w 4 pf4dr 0 r/w 3 pf3dr 0 r/w 0 pf0dr 0 r/w 2 pf2dr 0 r/w 1 pf1dr 0 r/w bit initial value read/write pfdr is an 8-bit readable/writable register that stores output data for the port f pins (pf7 to pf0). pfdr is initialized to h?0 by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port f register (portf) 7 pf7 * r 6 pf6 * r 5 pf5 * r 4 pf4 * r 3 pf3 * r 0 pf0 * r 2 pf2 * r 1 pf1 * r bit initial value read/write note: * determined by the state of pins pf7 to pf0. portf is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port f pins (pf7 to pf0) must always be performed on pfdr. if a port f read is performed while pfddr bits are set to 1, the pfdr values are read. if a port f read is performed while pfddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portf contents are determined by the pin states, as pfddr and pfdr are initialized. portf retains its previous state after a manual reset and in software standby mode. 9.12.3 pin functions port f pins also function as external interrupt input pins ( irq2 and irq3 ), the buzz output pin, the a/d trigger input pin ( adtrg ), bus control signal i/o pins ( as , rd , hwr , lwr , wait , breq , and back ), and the system clock (? output pin. the pin functions differ between modes 4 to 6 and mode 7. port f pin functions are shown in table 9-21.
280 table 9-21 port f pin functions pin pin functions and selection method pf7/ the pin function is switched as shown below according to bit pf7ddr. pf7ddr 0 1 pin function pf7 input ?output pf6/ as the pin function is switched as shown below according to the operating mode and bit pf6ddr. operating mode modes 4 to 6 mode 7 pf6ddr 0 1 pin function as output pf6 input pf6 output pf5/ rd the pin function is switched as shown below according to the operating mode and bit pf5ddr. operating mode modes 4 to 6 mode 7 pf5ddr 0 1 pin function rd output pf5 input pf5 output pf4/ hwr the pin function is switched as shown below according to the operating mode and bit pf4ddr. operating mode modes 4 to 6 mode 7 pf4ddr 0 1 pin function hwr output pf4 input pf4 output pf3/ lwr / adtrg / the pin function is switched as shown below according to the operating mode, the bus mode, a/d converter bits trgs1 and trgs0, and bit pf3ddr. irq3 operating mode modes 4 to 6 mode 7 bus mode 16-bit bus mode 8-bit bus mode pf3ddr 0101 pin function lwr output pf3 input pf3 output pf3 input pf3 output adtrg input * 1 irq3 input * 2 notes: 1. adtrg input when trgs0 = trgs1 = 1. 2. when used as an external interrupt input pin, do not use as an i/o pin for another function.
281 table 9-21 port f pin functions (cont) pin pin functions and selection method pf2/ wait the pin function is switched as shown below according to the operating mode, bit waite, and bit pf2ddr. operating mode modes 4 to 6 mode 7 waite 0 1 pf2ddr 0 1 0 1 pin function pf2 input pf2 output wait input pf2 input pf2 output pf1/ back / buzz the pin function is switched as shown below according to the operating mode, bit brle, bit buzze in pfcr, and bit pf1ddr. operating mode modes 4 to 6 mode 7 brle 0 1 buzze 0 1 0 1 pf1ddr 0 1 0 1 pin function pf1 input pf1 output buzz output back output pf1 input pf1 output buzz output pf0/ breq / irq2 the pin function is switched as shown below according to the operating mode, bit brle, and bit pf0ddr. operating mode modes 4 to 6 mode 7 brle 0 1 pf0ddr 0 1 0 1 pin function pf0 input pf0 output breq input pf0 input pf0 output irq2 input * note: * when used as an external interrupt input pin, do not use as an i/o pin for another function.
282 9.13 port g 9.13.1 overview port g is a 5-bit i/o port. port g pins also function as external interrupt input pins ( irq6 and irq7 ) and bus control signal output pins ( cs0 to cs3 ). the interrupt input pins ( irq6 and irq7 ) are schmitt-triggered inputs. figure 9-19 shows the port g pin configuration. pg4/ cs0 pg3/ cs1 pg2/ cs2 pg1/ cs3/ irq7 pg0/ irq6 pg4 (input/output) pg3 (input/output) pg2 (input/output) pg1 (input/output)/ irq7 (input) pg0 (input/output)/ irq6 (input) port g pins pin functions in mode 7 pin functions in modes 4 to 6 pg4 (input)/cs0 (output) pg3 (input)/cs1 (output) pg2 (input)/cs2 (output) pg1 (input)/cs3 (output)/irq7 (input) pg0 (input/output)/ irq6 (input) port g figure 9-19 port g pin functions
283 9.13.2 register configuration table 9-25 shows the port g register configuration. table 9-25 port g registers name abbreviation r/w initial value * 2 address * 1 port g data direction register pgddr w h'10/h'00 * 3 h'fe3f port g data register pgdr r/w h'00 h'ff0f port g register portg r undefined h'ffbf notes: 1. lower 16 bits of the address. 2. value of bits 4 to 0. 3. initial value depends on the mode. (1) port g data direction register (pgddr) 7 undefined undefined 6 undefined undefined 5 undefined undefined 4 pg4ddr 1 w 0 w 3 pg3ddr 0 w 0 w 0 pg0ddr 0 w 0 w 2 pg2ddr 0 w 0 w 1 pg1ddr 0 w 0 w bit modes 4 and 5 initial value read/write modes 6 and 7 initial value read/write pgddr is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port g. pgddr cannot be read. also, bits 7 to 5 are reserved, and will return an undefined value if read. bit pg4ddr is initialized to 1 (modes 4 and 5) or 0 (modes 6 and 7) by a power-on reset and in hardware standby mode. pgddr retains its previous state after a manual reset and in software standby mode. the ope bit in sbycr is used to select whether the bus control output pins retain their output state or become high-impedance when a transition is made to software standby mode. (a) modes 4 to 6 pins pg4 to pg1 function as bus control signal output pins ( cs0 to cs3 ) when the corresponding pgddr bits are set to 1, and as input ports when the bits are cleared to 0. pin pg0 functions as an output port when the corresponding pgddr bit is set to 1, and as an input port when the bit is cleared to 0.
284 (b) mode 7 setting a pgddr bit to 1 makes the corresponding pin an output port, while clearing the bit to 0 makes the pin an input port. (2) port g data register (pgdr) 7 undefined 6 undefined 5 undefined 4 pg4dr 0 r/w 3 pg3dr 0 r/w 0 pg0dr 0 r/w 2 pg2dr 0 r/w 1 pg1dr 0 r/w bit initial value read/write pgdr is an 8-bit readable/writable register that stores output data for the port g pins (pg4 to pg0). bits 7 to 5 are reserved; these bits cannot be modified and will return an undefined value if read. pgdr is initialized to h?0 (bits 4 to 0) by a power-on reset and in hardware standby mode. it retains its previous state after a manual reset and in software standby mode. (3) port g register (portg) 7 undefined 6 undefined 5 undefined 4 pg4 * r 3 pg3 * r 0 pg0 * r 2 pg2 * r 1 pg1 * r bit initial value read/write note: * determined by the state of pins pg4 to pg0. portg is an 8-bit read-only register that shows the pin states. it cannot be written to. writing of output data for the port g pins (pg4 to pg0) must always be performed on pgdr. bits 7 to 5 are reserved; these bits cannot be modified and will return an undefined value if read. if a port g read is performed while pgddr bits are set to 1, the pgdr values are read. if a port g read is performed while pgddr bits are cleared to 0, the pin states are read. after a power-on reset and in hardware standby mode, portg contents are determined by the pin states, as pgddr and pgdr are initialized. portg retains its previous state after a manual reset and in software standby mode.
285 9.13.3 pin functions port g pins also function as external interrupt input pins ( irq6 and irq7 ) and bus control signal output pins ( cs0 to cs3 ). the pin functions differ between modes 4 to 6 and mode 7. port g pin functions are shown in table 9-22. table 9-22 port g pin functions pin pin functions and selection method pg4/ cs0 the pin function is switched as shown below according to the operating mode and bit pg4ddr. operating mode modes 4 to 6 mode 7 pg4ddr 0101 pin function pg4 input cs0 output pg4 input pg4 output pg3/ cs1 the pin function is switched as shown below according to the operating mode and bit pg3ddr. operating mode modes 4 to 6 mode 7 pg3ddr 0101 pin function pg3 input cs1 output pg3 input pg3 output pg2/ cs2 the pin function is switched as shown below according to the operating mode and bit pg2ddr. operating mode modes 4 to 6 mode 7 pg2ddr 0101 pin function pg2 input cs2 output pg2 input pg2 output pg1/ cs3 / irq7 the pin function is switched as shown below according to the operating mode and bit pg1ddr. operating mode modes 4 to 6 mode 7 pg1ddr 0101 pin function pg1 input cs3 output pg1 input pg1 output irq7 input * note: * when used as an external interrupt input pin, do not use as an i/o pin for another function.
286 table 9-22 port g pin functions pin pin functions and selection method pg0/ irq6 the pin function is switched as shown below according to bit pg0ddr. pg0ddr 0 1 pin function pg0 input pg0 output irq6 input * note: * when used as an external interrupt input pin, do not use as an i/o pin for another function.
287 section 10 16-bit timer pulse unit (tpu) 10.1 overview the h8s/2237 series and h8s/2227 series have an on-chip 16-bit timer pulse unit (tpu) that comprises six 16-bit timer channels. 10.1.1 features h8s/2237 series: 6 channels (channels 0, 1, 2, 3, 4, 5) h8s/2227 series: 3 channels (channels 0, 1, 2) pulse input/output capability h8s/2237 series: max. 16 outputs h8s/2227 series: max. 8 outputs ? a total of 16 timer general registers (tgrs) are provided (four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5), each of which can be set independently as an output compare/input capture register ? tgrc and tgrd for channels 0 and 3 can also be used as buffer registers selection of 8 counter input clocks for each channel the following operations can be set for each channel: ? waveform output at compare match: selection of 0, 1, or toggle output ? input capture function: selection of rising edge, falling edge, or both edge detection ? counter clear operation: counter clearing possible by compare match or input capture ? synchronous operation: multiple timer counters (tcnt) can be written to simultaneously simultaneous clearing by compare match and input capture possible register simultaneous input/output possible by counter synchronous operation ? pwm mode: any pwm output duty can be set maximum of 15-phase pwm output possible by combination with synchronous operation buffer operation settable for channels 0 and 3 ? input capture register double-buffering possible ? automatic rewriting of output compare register possible phase counting mode settable independently for each of channels 1, 2, 4, and 5 ? two-phase encoder pulse up/down-count possible
288 cascaded operation (h8s/2237 series only) ? channel 2 (channel 5) input clock operates as 32-bit counter by setting channel 1 (channel 4) overflow/underflow fast access via internal 16-bit bus ? fast access is possible via a 16-bit bus interface 26 interrupt sources ? for channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently ? for channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently automatic transfer of register data ? block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer controller (dtc) activation a/d converter conversion start trigger can be generated ? channel 0 to 5 compare match a/input capture a signals can be used as a/d converter conversion start trigger module stop mode can be set ? as the initial setting, tpu operation is halted. register access is enabled by exiting module stop mode. table 10-1 lists the functions of the tpu.
289 table 10-1 tpu functions item channel 0 channel 1 channel 2 channel 3 * channel 4 * channel 5 * count clock ?1 ?4 ?16 ?64 tclka tclkb tclkc tclkd ?1 ?4 ?16 ?64 ?256 tclka tclkb ?1 ?4 ?16 ?64 ?1024 tclka tclkb tclkc ?1 ?4 ?16 ?64 ?256 ?1024 ?4096 tclka ?1 ?4 ?16 ?64 ?1024 tclka tclkc ?1 ?4 ?16 ?64 ?256 tclka tclkc tclkd general registers tgr0a tgr0b tgr1a tgr1b tgr2a tgr2b tgr3a tgr3b tgr4a tgr4b tgr5a tgr5b general registers/ buffer registers tgr0c tgr0d tgr3c tgr3d i/o pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 counter clear function tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture compare 0 output match 1 output output toggle output input capture function synchronous operation pwm mode phase counting mode buffer operation legend : possible : not possible note: * applies to the h8s/2237 series only.
290 table 10-1 tpu functions (cont) item channel 0 channel 1 channel 2 channel 3 * channel 4 * channel 5 * dtc activation tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture tgr compare match or input capture a/d converter trigger tgr0a compare match or input capture tgr1a compare match or input capture tgr2a compare match or input capture tgr3a compare match or input capture tgr4a compare match or input capture tgr5a compare match or input capture interrupt sources 5 sources compare match or input capture 0a compare match or input capture 0b compare match or input capture 0c compare match or input capture 0d overflow 4 sources compare match or input capture 1a compare match or input capture 1b overflow underflow 4 sources compare match or input capture 2a compare match or input capture 2b overflow underflow 5 sources compare match or input capture 3a compare match or input capture 3b compare match or input capture 3c compare match or input capture 3d overflow 4 sources compare match or input capture 4a compare match or input capture 4b overflow underflow 4 sources compare match or input capture 5a compare match or input capture 5b overflow underflow legend : not possible
291 10.1.2 block diagram figure 10-1 shows a block diagram of the tpu. channel 3 tmdr tiorl tsr tcr tiorh tier tgra tcnt tgrb tgrc tgrd channel 4 tmdr tsr tcr tior tier tgra tcnt tgrb control logic tmdr tsr tcr tior tier tgra tcnt tgrb control logic for channels 3 to 5 tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 tmdr tsr tcr tiorh tier control logic for channels 0 to 2 tgra tcnt tgrb tgrd tsyr tstr input/output pins tioca3 tiocb3 tiocc3 tiocd3 tioca4 tiocb4 tioca5 tiocb5 clock input ?1 ?4 ?16 ?64 ?256 ?1024 ?4096 tclka tclkb tclkc tclkd input/output pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 interrupt request signals channel 3: channel 4: channel 5: interrupt request signals channel 0: channel 1: channel 2: internal data bus a/d conversion start request signal tiorl module data bus tgi3a tgi3b tgi3c tgi3d tci3v tgi4a tgi4b tci4v tci4u tgi5a tgi5b tci5v tci5u tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u channel 3: channel 4: channel 5: internal clock: external clock: channel 0: channel 1: channel 2: legend tstr: timer start register tsyr: timer synchro register tcr: timer control register tmdr: timer mode register tior (h, l): timer i/o control registers (h, l) tier: timer interrupt enable register tsr: timer status register tgr (a, b, c, d): timer general registers (a, b, c, d) channel 2 common channel 5 bus interface figure 10-1 block diagram of h8s/2237 series tpu
292 control logic tmdr tsr tcr tior tier tgra tcnt tgrb tgrc channel 1 tmdr tsr tcr tior tier tgra tcnt tgrb channel 0 tmdr tsr tcr tiorh tier control logic for channels 0 to 2 tgra tcnt tgrb tgrd tsyr tstr clock input ?1 ?4 ?16 ?64 ?256 ?1024 tclka tclkb tclkc tclkd input/output pins tioca0 tiocb0 tiocc0 tiocd0 tioca1 tiocb1 tioca2 tiocb2 interrupt request signals channel 0: channel 1: channel 2: internal data bus a/d conversion start request signal tiorl module data bus tgi0a tgi0b tgi0c tgi0d tci0v tgi1a tgi1b tci1v tci1u tgi2a tgi2b tci2v tci2u internal clock: external clock: channel 0: channel 1: channel 2: channel 2 common bus interface legend tstr: timer start register tsyr: timer synchro register tcr: timer control register tmdr: timer mode register tior (h, l): timer i/o control registers (h, l) tier: timer interrupt enable register tsr: timer status register tgr (a, b, c, d): timer general registers (a, b, c, d) figure 10-2 block diagram of h8s/2227 series tpu
293 10.1.3 pin configuration table 10-2 summarizes the tpu pins. table 10-2 tpu pins channel name symbol i/o function all clock input a tclka input external clock a input pin (channel 1 and 5 phase counting mode a phase input) clock input b tclkb input external clock b input pin (channel 1 and 5 phase counting mode b phase input) clock input c tclkc input external clock c input pin (channel 2 and 4 phase counting mode a phase input) clock input d tclkd input external clock d input pin (channel 2 and 4 phase counting mode b phase input) 0 input capture/out compare match a0 tioca0 i/o tgr0a input capture input/output compare output/pwm output pin input capture/out compare match b0 tiocb0 i/o tgr0b input capture input/output compare output/pwm output pin input capture/out compare match c0 tiocc0 i/o tgr0c input capture input/output compare output/pwm output pin input capture/out compare match d0 tiocd0 i/o tgr0d input capture input/output compare output/pwm output pin 1 input capture/out compare match a1 tioca1 i/o tgr1a input capture input/output compare output/pwm output pin input capture/out compare match b1 tiocb1 i/o tgr1b input capture input/output compare output/pwm output pin 2 input capture/out compare match a2 tioca2 i/o tgr2a input capture input/output compare output/pwm output pin input capture/out compare match b2 tiocb2 i/o tgr2b input capture input/output compare output/pwm output pin
294 table 10-2 tpu pins (cont) channel name symbol i/o function 3 * input capture/out compare match a3 tioca3 i/o tgr3a input capture input/output compare output/pwm output pin input capture/out compare match b3 tiocb3 i/o tgr3b input capture input/output compare output/pwm output pin input capture/out compare match c3 tiocc3 i/o tgr3c input capture input/output compare output/pwm output pin input capture/out compare match d3 tiocd3 i/o tgr3d input capture input/output compare output/pwm output pin 4 * input capture/out compare match a4 tioca4 i/o tgr4a input capture input/output compare output/pwm output pin input capture/out compare match b4 tiocb4 i/o tgr4b input capture input/output compare output/pwm output pin 5 * input capture/out compare match a5 tioca5 i/o tgr5a input capture input/output compare output/pwm output pin input capture/out compare match b5 tiocb5 i/o tgr5b input capture input/output compare output/pwm output pin note: * applies to the h8s/2237 series only.
295 10.1.4 register configuration table 10-3 summarizes the tpu registers. table 10-3 tpu registers channel name abbreviation r/w initial value address * 1 0 timer control register 0 tcr0 r/w h'00 h'ff10 timer mode register 0 tmdr0 r/w h'c0 h'ff11 timer i/o control register 0h tior0h r/w h'00 h'ff12 timer i/o control register 0l tior0l r/w h'00 h'ff13 timer interrupt enable register 0 tier0 r/w h'40 h'ff14 timer status register 0 tsr0 r/(w) * 2 h'c0 h'ff15 timer counter 0 tcnt0 r/w h'0000 h'ff16 timer general register 0a tgr0a r/w h'ffff h'ff18 timer general register 0b tgr0b r/w h'ffff h'ff1a timer general register 0c tgr0c r/w h'ffff h'ff1c timer general register 0d tgr0d r/w h'ffff h'ff1e 1 timer control register 1 tcr1 r/w h'00 h'ff20 timer mode register 1 tmdr1 r/w h'c0 h'ff21 timer i/o control register 1 tior1 r/w h'00 h'ff22 timer interrupt enable register 1 tier1 r/w h'40 h'ff24 timer status register 1 tsr1 r/(w) * 2 h'c0 h'ff25 timer counter 1 tcnt1 r/w h'0000 h'ff26 timer general register 1a tgr1a r/w h'ffff h'ff28 timer general register 1b tgr1b r/w h'ffff h'ff2a 2 timer control register 2 tcr2 r/w h'00 h'ff30 timer mode register 2 tmdr2 r/w h'c0 h'ff31 timer i/o control register 2 tior2 r/w h'00 h'ff32 timer interrupt enable register 2 tier2 r/w h'40 h'ff34 timer status register 2 tsr2 r/(w) * 2 h'c0 h'ff35 timer counter 2 tcnt2 r/w h'0000 h'ff36 timer general register 2a tgr2a r/w h'ffff h'ff38 timer general register 2b tgr2b r/w h'ffff h'ff3a
296 table 10-3 tpu registers (cont) channel name abbreviation r/w initial value address * 1 3 * 3 timer control register 3 tcr3 r/w h'00 h'fe80 timer mode register 3 tmdr3 r/w h'c0 h'fe81 timer i/o control register 3h tior3h r/w h'00 h'fe82 timer i/o control register 3l tior3l r/w h'00 h'fe83 timer interrupt enable register 3 tier3 r/w h'40 h'fe84 timer status register 3 tsr3 r/(w) * 2 h'c0 h'fe85 timer counter 3 tcnt3 r/w h'0000 h'fe86 timer general register 3a tgr3a r/w h'ffff h'fe88 timer general register 3b tgr3b r/w h'ffff h'fe8a timer general register 3c tgr3c r/w h'ffff h'fe8c timer general register 3d tgr3d r/w h'ffff h'fe8e 4 * 3 timer control register 4 tcr4 r/w h'00 h'fe90 timer mode register 4 tmdr4 r/w h'c0 h'fe91 timer i/o control register 4 tior4 r/w h'00 h'fe92 timer interrupt enable register 4 tier4 r/w h'40 h'fe94 timer status register 4 tsr4 r/(w) * 2 h'c0 h'fe95 timer counter 4 tcnt4 r/w h'0000 h'fe96 timer general register 4a tgr4a r/w h'ffff h'fe98 timer general register 4b tgr4b r/w h'ffff h'fe9a 5 * 3 timer control register 5 tcr5 r/w h'00 h'fea0 timer mode register 5 tmdr5 r/w h'c0 h'fea1 timer i/o control register 5 tior5 r/w h'00 h'fea2 timer interrupt enable register 5 tier5 r/w h'40 h'fea4 timer status register 5 tsr5 r/(w) * 2 h'c0 h'fea5 timer counter 5 tcnt5 r/w h'0000 h'fea6 timer general register 5a tgr5a r/w h'ffff h'fea8 timer general register 5b tgr5b r/w h'ffff h'feaa all timer start register tstr r/w h'00 h'ffc0 timer synchro register tsyr r/w h'00 h'ffc1 module stop control register a mstpcra r/w h'3f h'fde8 notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing. 3. applies to the h8s/2237 series only.
297 10.2 register descriptions 10.2.1 timer control register (tcr) 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value r/w : : : channel 0: tcr0 channel 3: tcr3 * 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w channel 1: tcr1 channel 2: tcr2 channel 4: tcr4 * channel 5: tcr5 * bit initial value r/w : : : note: * applies to the h8s/2237 series only. the tcr registers are 8-bit registers that control the tcnt channels. the tpu has six tcr registers, one for each of channels 0 to 5. the tcr registers are initialized to h'00 by a reset, and in hardware standby mode.
298 bits 7, 6, 5?ounter clear 2, 1, and 0 (cclr2, cclr1, cclr0): these bits select the tcnt counter clearing source. bit 7 bit 6 bit 5 channel cclr2 cclr1 cclr0 description 0, 3 0 0 0 tcnt clearing disabled (initial value) 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 1 0 0 tcnt clearing disabled 1 tcnt cleared by tgrc compare match/input capture * 2 1 0 tcnt cleared by tgrd compare match/input capture * 2 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 bit 7 bit 6 bit 5 channel reserved * 3 cclr1 cclr0 description 1, 2, 4, 5 0 0 0 tcnt clearing disabled (initial value) 1 tcnt cleared by tgra compare match/input capture 1 0 tcnt cleared by tgrb compare match/input capture 1 tcnt cleared by counter clearing for another channel performing synchronous clearing/ synchronous operation * 1 notes: 1. synchronous operation setting is performed by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 3. bit 7 is reserved in channels 1, 2, 4, and 5. it is always read as 0 and cannot be modified.
299 bits 4 and 3?lock edge 1 and 0 (ckeg1, ckeg0): these bits select the input clock edge. when the input clock is counted using both edges, the input clock period is halved (e.g. ?4 both edges = ?2 rising edge). if phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority. bit 4 bit 3 ckeg1 ckeg0 description 0 0 count at rising edge (initial value) 1 count at falling edge 1 count at both edges note: internal clock edge selection is valid when the input clock is ?4 or slower. this setting is ignored if the input clock is ?1, or when overflow/underflow of another channel is selected. bits 2, 1, and 0?ime prescaler 2, 1, and 0 (tpsc2 to tpsc0): these bits select the tcnt counter clock. the clock source can be selected independently for each channel. table 10-4 shows the clock sources that can be set for each channel. table 10-4 tpu clock sources channel internal clock ?1 ?4 ?16 ?64 ?256 ?1024 ?4096 external clock tclka tclkb tclkc tclkd overflow/ underflow on another channel 0 1 2 3 4 5 legend : setting blank : no setting
300 bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 0000 internal clock: counts on ?1 (initial value) 1 internal clock: counts on ?4 1 0 internal clock: counts on ?16 1 internal clock: counts on ?64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 external clock: counts on tclkd pin input bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 1000 internal clock: counts on ?1 (initial value) 1 internal clock: counts on ?4 1 0 internal clock: counts on ?16 1 internal clock: counts on ?64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 internal clock: counts on ?256 1 counts on tcnt2 overflow/underflow (setting prohibited on h8s/2227 series) note: this setting is ignored when channel 1 is in phase counting mode. bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 2000 internal clock: counts on ?1 (initial value) 1 internal clock: counts on ?4 1 0 internal clock: counts on ?16 1 internal clock: counts on ?64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkb pin input 1 0 external clock: counts on tclkc pin input 1 internal clock: counts on ?1024 note: this setting is ignored when channel 2 is in phase counting mode.
301 bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 3 * 0 0 0 internal clock: counts on ?1 (initial value) 1 internal clock: counts on ?4 1 0 internal clock: counts on ?16 1 internal clock: counts on ?64 1 0 0 external clock: counts on tclka pin input 1 internal clock: counts on ?1024 1 0 internal clock: counts on ?256 1 internal clock: counts on ?4096 note: * applies to the h8s/2237 series only. bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 4 * 0 0 0 internal clock: counts on ?1 (initial value) 1 internal clock: counts on ?4 1 0 internal clock: counts on ?16 1 internal clock: counts on ?64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on ?1024 1 counts on tcnt5 overflow/underflow note: * this setting is ignored when channel 4 is in phase counting mode. applies to the h8s/2237 series only. bit 2 bit 1 bit 0 channel tpsc2 tpsc1 tpsc0 description 5 * 0 0 0 internal clock: counts on ?1 (initial value) 1 internal clock: counts on ?4 1 0 internal clock: counts on ?16 1 internal clock: counts on ?64 1 0 0 external clock: counts on tclka pin input 1 external clock: counts on tclkc pin input 1 0 internal clock: counts on ?256 1 external clock: counts on tclkd pin input note: * this setting is ignored when channel 5 is in phase counting mode. applies to the h8s/2237 series only.
302 10.2.2 timer mode register (tmdr) 7 1 6 1 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : channel 0: tmdr0 channel 3: tmdr3 * 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : channel 1: tmdr1 channel 2: tmdr2 channel 4: tmdr4 * channel 5: tmdr5 * note: * applies to the h8s/2237 series only. the tmdr registers are 8-bit readable/writable registers that are used to set the operating mode for each channel. the tpu has six tmdr registers, one for each channel. the tmdr registers are initialized to h'c0 by a reset, and in hardware standby mode. bits 7 and 6?eserved: read-only bits, always read as 1. bit 5?uffer operation b (bfb): specifies whether tgrb is to operate in the normal way, or tgrb and tgrd are to be used together for buffer operation. when tgrd is used as a buffer register, tgrd input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrd, bit 5 is reserved. it is always read as 0 and cannot be modified.
303 bit 5 bfb description 0 tgrb operates normally (initial value) 1 tgrb and tgrd used together for buffer operation bit 4?uffer operation a (bfa): specifies whether tgra is to operate in the normal way, or tgra and tgrc are to be used together for buffer operation. when tgrc is used as a buffer register, tgrc input capture/output compare is not generated. in channels 1, 2, 4, and 5, which have no tgrc, bit 4 is reserved. it is always read as 0 and cannot be modified. bit 4 bfa description 0 tgra operates normally (initial value) 1 tgra and tgrc used together for buffer operation bits 3 to 0?odes 3 to 0 (md3 to md0): these bits are used to set the timer operating mode. bit 3 bit 2 bit 1 bit 0 md3 * 1 md2 * 2 md1 md0 description 0000 normal operation (initial value) 1 reserved 1 0 pwm mode 1 1 pwm mode 2 1 0 0 phase counting mode 1 1 phase counting mode 2 1 0 phase counting mode 3 1 phase counting mode 4 1 *** * : don? care notes: 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2.
304 10.2.3 timer i/o control register (tior) 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : channel 0: tior0h channel 1: tior1 channel 2: tior2 channel 3: tior3h * channel 4: tior4 * channel 5: tior5 * 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w channel 0: tior0l channel 3: tior3l * note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer register. bit initial value r/w : : : * applies to the h8s/2237 series only. the tior registers are 8-bit registers that control the tgr registers. the tpu has eight tior registers, two each for channels 0 and 3, and one each for channels 1, 2, 4, and 5. the tior registers are initialized to h'00 by a reset, and in hardware standby mode. care is required since tior is affected by the tmdr setting. the initial output specified by tior is valid when the counter is stopped (the cst bit in tstr is cleared to 0). note also that, in pwm mode 2, the output at the point at which the counter is cleared to 0 is specified.
305 bits 7 to 4 i/o control b3 to b0 (iob3 to iob0) i/o control d3 to d0 (iod3 to iod0): bits iob3 to iob0 specify the function of tgrb. bits iod3 to iod0 specify the function of tgrd. bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 0 000 1 0 1 0 1 tgr0b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr0b is input capture register capture input source is tiocb0 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 1/count clock input capture at tcnt1 count- up/count-down * 1 * : don? care note: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and ?1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated.
306 bit 7 bit 6 bit 5 bit 4 channel iod3 iod2 iod1 iod0 description 0 000 1 0 1 0 1 tgr0d is output compare register * 2 output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr0d is input capture register * 2 capture input source is tiocd0 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 1/count clock input capture at tcnt1 count-up/count-down * 1 * : don? care notes: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and ?1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
307 bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 1 000 1 0 1 0 1 tgr1b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 0 0 1 0 1 * tgr1b is input capture register capture input source is tiocb1 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is tgr0c compare match/ input capture input capture at generation of tgr0c compare match/input capture * : don? care bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 2 000 1 0 1 0 1 tgr2b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 * 0 1 0 1 * tgr2b is input capture register capture input source is tiocb2 pin input capture at rising edge input capture at falling edge input capture at both edges * : don? care
308 bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 3 * 2 000 1 0 1 0 1 tgr3b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr3b is input capture register capture input source is tiocb3 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * 1 * : don? care note: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and ?1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated. 2. applies to the h8s/2237 series only.
309 bit 7 bit 6 bit 5 bit 4 channel iod3 iod2 iod1 iod0 description 3 * 3 000 1 0 1 0 1 tgr3d is output compare register * 2 output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr3d is input capture register * 2 capture input source is tiocd3 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * 1 * : don? care notes: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and ?1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr3 is set to 1 and tgr3d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 3. applies to the h8s/2237 series only.
310 bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 4 * 1 000 1 0 1 0 1 tgr4b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr4b is input capture register capture input source is tiocb4 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is tgr3c compare match/ input capture input capture at generation of tgr3c compare match/ input capture * : don? care note: 1. applies to the h8s/2237 series only. bit 7 bit 6 bit 5 bit 4 channel iob3 iob2 iob1 iob0 description 5 * 1 000 1 0 1 0 1 tgr5b is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 * 0 1 0 1 * tgr5b is input capture register capture input source is tiocb5 pin input capture at rising edge input capture at falling edge input capture at both edges * : don? care note: 1. applies to the h8s/2237 series only.
311 bits 3 to 0 i/o control a3 to a0 (ioa3 to ioa0) i/o control c3 to c0 (ioc3 to ioc0): ioa3 to ioa0 specify the function of tgra. ioc3 to ioc0 specify the function of tgrc. bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 0 000 1 0 1 0 1 tgr0a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr0a is input capture register capture input source is tioca0 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 1/ count clock input capture at tcnt1 count-up/count-down * : don? care
312 bit 3 bit 2 bit 1 bit 0 channel ioc3 ioc2 ioc1 ioc0 description 0 000 1 0 1 0 1 tgr0c is output compare register * 1 output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr0c is input capture register * 1 capture input source is tiocc0 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 1/count clock input capture at tcnt1 count-up/count-down * : don? care note: 1. when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer register, this setting is invalid and input capture/output compare is not generated.
313 bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 1 000 1 0 1 0 1 tgr1a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr1a is input capture register capture input source is tioca1 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is tgr0a compare match/ input capture input capture at generation of channel 0/tgr0a compare match/input capture * : don? care bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 2 000 1 0 1 0 1 tgr2a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 * 0 1 0 1 * tgr2a is input capture register capture input source is tioca2 pin input capture at rising edge input capture at falling edge input capture at both edges * : don? care
314 bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 3 * 1 000 1 0 1 0 1 tgr3a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr3a is input capture register capture input source is tioca3 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * : don? care note: 1. applies to the h8s/2237 series only.
315 bit 3 bit 2 bit 1 bit 0 channel ioc3 ioc2 ioc1 ioc0 description 3 * 2 000 1 0 1 0 1 tgr3c is output compare register * 1 output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr3c is input capture register * 1 capture input source is tiocc3 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is channel 4/count clock input capture at tcnt4 count-up/count-down * : don? care notes: 1. when the bfa bit in tmdr3 is set to 1 and tgr3c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. 2. applies to the h8s/2237 series only.
316 bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 4 * 1 000 1 0 1 0 1 tgr4a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 100 1 0 1 * tgr4a is input capture register capture input source is tioca4 pin input capture at rising edge input capture at falling edge input capture at both edges 1 ** capture input source is tgr3a compare match/ input capture input capture at generation of tgr3a compare match/input capture * : don? care note: 1. applies to the h8s/2237 series only. bit 3 bit 2 bit 1 bit 0 channel ioa3 ioa2 ioa1 ioa0 description 5 * 1 000 1 0 1 0 1 tgr5a is output compare register output disabled initial output is 0 output (initial value) 0 output at compare match 1 output at compare match toggle output at compare match 1 0 0 output disabled 1 initial output is 1 0 output at compare match 10 output 1 output at compare match 1 toggle output at compare match 1 * 0 1 0 1 * tgr5a is input capture register capture input source is tioca5 pin input capture at rising edge input capture at falling edge input capture at both edges * : don? care note: 1. applies to the h8s/2237 series only.
317 10.2.4 timer interrupt enable register (tier) 7 ttge 0 r/w 6 1 5 0 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w bit initial value r/w : : : channel 0: tier0 channel 3: tier3 * 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w channel 1: tier1 channel 2: tier2 channel 4: tier4 * channel 5: tier5 * bit initial value r/w : : : note: * applies to the h8s/2237 series only. the tier registers are 8-bit registers that control enabling or disabling of interrupt requests for each channel. the tpu has six tier registers, one for each channel. the tier registers are initialized to h'40 by a reset, and in hardware standby mode.
318 bit 7?/d conversion start request enable (ttge): enables or disables generation of a/d conversion start requests by tgra input capture/compare match. bit 7 ttge description 0 a/d conversion start request generation disabled (initial value) 1 a/d conversion start request generation enabled bit 6?eserved: read-only bit, always read as 1. bit 5?nderflow interrupt enable (tcieu): enables or disables interrupt requests (tciu) by the tcfu flag when the tcfu flag in tsr is set to 1 in channels 1, 2, 4, and 5. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 tcieu description 0 interrupt requests (tciu) by tcfu disabled (initial value) 1 interrupt requests (tciu) by tcfu enabled bit 4?verflow interrupt enable (tciev): enables or disables interrupt requests (tciv) by the tcfv flag when the tcfv flag in tsr is set to 1. bit 4 tciev description 0 interrupt requests (tciv) by tcfv disabled (initial value) 1 interrupt requests (tciv) by tcfv enabled bit 3?gr interrupt enable d (tgied): enables or disables interrupt requests (tgid) by the tgfd bit when the tgfd bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. bit 3 tgied description 0 interrupt requests (tgid) by tgfd bit disabled (initial value) 1 interrupt requests (tgid) by tgfd bit enabled
319 bit 2?gr interrupt enable c (tgiec): enables or disables interrupt requests (tgic) by the tgfc bit when the tgfc bit in tsr is set to 1 in channels 0 and 3. in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. bit 2 tgiec description 0 interrupt requests (tgic) by tgfc bit disabled (initial value) 1 interrupt requests (tgic) by tgfc bit enabled bit 1?gr interrupt enable b (tgieb): enables or disables interrupt requests (tgib) by the tgfb bit when the tgfb bit in tsr is set to 1. bit 1 tgieb description 0 interrupt requests (tgib) by tgfb bit disabled (initial value) 1 interrupt requests (tgib) by tgfb bit enabled bit 0?gr interrupt enable a (tgiea): enables or disables interrupt requests (tgia) by the tgfa bit when the tgfa bit in tsr is set to 1. bit 0 tgiea description 0 interrupt requests (tgia) by tgfa bit disabled (initial value) 1 interrupt requests (tgia) by tgfa bit enabled
320 10.2.5 timer status register (tsr) 7 1 6 1 5 0 4 tcfv 0 r/(w) * 2 3 tgfd 0 r/(w) * 2 0 tgfa 0 r/(w) * 2 2 tgfc 0 r/(w) * 2 1 tgfb 0 r/(w) * 2 bit initial value r/w : : : channel 0: tsr0 channel 3: tsr3 * 1 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 2 4 tcfv 0 r/(w) * 2 3 0 0 tgfa 0 r/(w) * 2 2 0 1 tgfb 0 r/(w) * 2 channel 1: tsr1 channel 2: tsr2 channel 4: tsr4 * 1 channel 5: tsr5 * 1 bit initial value r/w notes: 1. applies to the h8s/2237 series only. 2. can only be written with 0 for flag clearing. : : : the tsr registers are 8-bit registers that indicate the status of each channel. the tpu has six tsr registers, one for each channel. the tsr registers are initialized to h'c0 by a reset, and in hardware standby mode. bit 7?ount direction flag (tcfd): status flag that shows the direction in which tcnt counts in channels 1, 2, 4, and 5. in channels 0 and 3, bit 7 is reserved. it is always read as 1 and cannot be modified. bit 7 tcfd description 0 tcnt counts down 1 tcnt counts up (initial value)
321 bit 6?eserved: read-only bit, always read as 1 and cannot be modified. bit 5?nderflow flag (tcfu): status flag that indicates that tcnt underflow has occurred when channels 1, 2, 4, and 5 are set to phase counting mode. in channels 0 and 3, bit 5 is reserved. it is always read as 0 and cannot be modified. bit 5 tcfu description 0 [clearing condition] (initial value) when 0 is written to tcfu after reading tcfu = 1 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) bit 4?verflow flag (tcfv): status flag that indicates that tcnt overflow has occurred. bit 4 tcfv description 0 [clearing condition] (initial value) when 0 is written to tcfv after reading tcfv = 1 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) bit 3?nput capture/output compare flag d (tgfd): status flag that indicates the occurrence of tgrd input capture or compare match in channels 0 and 3. in channels 1, 2, 4, and 5, bit 3 is reserved. it is always read as 0 and cannot be modified. bit 3 tgfd description 0 [clearing conditions] (initial value) when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfd after reading tgfd = 1 1 [setting conditions] when tcnt = tgrd while tgrd is functioning as output compare register when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register bit 2?nput capture/output compare flag c (tgfc): status flag that indicates the occurrence of tgrc input capture or compare match in channels 0 and 3.
322 in channels 1, 2, 4, and 5, bit 2 is reserved. it is always read as 0 and cannot be modified. bit 2 tgfc description 0 [clearing conditions] (initial value) when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfc after reading tgfc = 1 1 [setting conditions] when tcnt = tgrc while tgrc is functioning as output compare register when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register bit 1?nput capture/output compare flag b (tgfb): status flag that indicates the occurrence of tgrb input capture or compare match. bit 1 tgfb description 0 [clearing conditions] (initial value) when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfb after reading tgfb = 1 1 [setting conditions] when tcnt = tgrb while tgrb is functioning as output compare register when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register bit 0?nput capture/output compare flag a (tgfa): status flag that indicates the occurrence of tgra input capture or compare match. bit 0 tgfa description 0 [clearing conditions] (initial value) when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 when 0 is written to tgfa after reading tgfa = 1 1 [setting conditions] when tcnt = tgra while tgra is functioning as output compare register when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register
323 10.2.6 timer counter (tcnt) 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value r/w : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w channel 0: tcnt0 (up-counter) channel 1: tcnt1 (up/down-counter * 1 ) channel 2: tcnt2 (up/down-counter * 1 ) channel 3: tcnt3 (up-counter) * 2 channel 4: tcnt4 (up/down-counter * 1 ) * 2 channel 5: tcnt5 (up/down-counter * 1 ) * 2 notes : 1. 2. these counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. in other cases they function as up-counters. applies to the h8s/2237 series onl y . the tcnt registers are 16-bit counters. the tpu has six tcnt counters, one for each channel. the tcnt counters are initialized to h'0000 by a reset, and in hardware standby mode. the tcnt counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit.
324 10.2.7 timer general register (tgr) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value r/w : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w the tgr registers are 16-bit registers with a dual function as output compare and input capture registers. the tpu has 16 tgr registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5. tgrc and tgrd for channels 0 and 3 can also be designated for operation as buffer registers*. the tgr registers are initialized to h'ffff by a reset, and in hardware standby mode. the tgr registers cannot be accessed in 8-bit units; they must always be accessed as a 16-bit unit. note: * tgr buffer register combinations are tgra?grc and tgrb?grd.
325 10.2.8 timer start register (tstr) 7 0 6 0 5 cst5 0 r/w 4 cst4 0 r/w 3 cst3 0 r/w 0 cst0 0 r/w 2 cst2 0 r/w 1 cst1 0 r/w bit initial value r/w : : : tstr is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. tstr is initialized to h'00 by a reset, and in hardware standby mode. tcnt counter operation must be halted before setting the operating mode in tmdr, or setting the tcnt count clock in tcr. bits 7 and 6?eserved: should always be written with 0. bits 5 to 0?ounter start 5 to 0 (cst5 to cst0): these bits select operation or stoppage for tcnt. bit n cstn description 0 tcntn count operation is stopped (initial value) 1 tcntn performs count operation n = 5 to 0 note: if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value.
326 10.2.9 timer synchro register (tsyr) 7 0 6 0 5 sync5 0 r/w 4 sync4 0 r/w 3 sync3 0 r/w 0 sync0 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w bit initial value r/w : : : tsyr is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 tcnt counters. a channel performs synchronous operation when the corresponding bit in tsyr is set to 1. tsyr is initialized to h'00 by a reset, and in hardware standby mode. bits 7 and 6?eserved: should always be written with 0. bits 5 to 0?imer synchro 5 to 0 (sync5 to sync0): these bits select whether operation is independent of or synchronized with other channels. when synchronous operation is selected, synchronous presetting of multiple channels* 1 , and synchronous clearing through counter clearing on another channel* 2 are possible. bit n syncn description 0 tcntn operates independently (tcnt presetting/clearing is unrelated to other channels) (initial value) 1 tcntn performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible n = 5 to 0 notes: 1. to set synchronous operation, the sync bits for at least two channels must be set to 1. 2. to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr.
327 10.2.10 module stop control register a (mstpcra) 7 mstpa7 0 r/w bit initial value r/w : : : 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w 0 mstpa0 1 r/w mstpcra is a 16-bit readable/writable register that performs module stop mode control. when the mstpa5 bit in mstpcr is set to 1, tpu operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 20.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 5?odule stop (mstpa5): specifies the tpu module stop mode. bit 5 mstpa5 description 0 tpu module stop mode cleared 1 tpu module stop mode set (initial value)
328 10.3 interface to bus master 10.3.1 16-bit registers tcnt and tgr are 16-bit registers. as the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. these registers cannot be read or written to in 8-bit units; 16-bit access must always be used. an example of 16-bit register access operation is shown in figure 10-3. bus interface h internal data bus l bus master module data bus tcnth tcntl figure 10-3 16-bit register access operation [bus master ? tcnt (16 bits)] 10.3.2 8-bit registers registers other than tcnt and tgr are 8-bit. as the data bus to the cpu is 16 bits wide, these registers can be read and written to in 16-bit units. they can also be read and written to in 8-bit units. examples of 8-bit register access operation are shown in figures 10-4, 10-5, and 10-6. bus interface h internal data bus l module data bus tcr bus master figure 10-4 8-bit register access operation [bus master ? tcr (upper 8 bits)]
329 bus interface h internal data bus l module data bus tmdr bus master figure 10-5 8-bit register access operation [bus master ? tmdr (lower 8 bits)] bus interface h internal data bus l module data bus tcr tmdr bus master figure 10-6 8-bit register access operation [bus master ? tcr and tmdr (16 bits)]
330 10.4 operation 10.4.1 overview operation in each mode is outlined below. normal operation: each channel has a tcnt and tgr register. tcnt performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. each tgr can be used as an input capture register or output compare register. synchronous operation: when synchronous operation is designated for a channel, tcnt for that channel performs synchronous presetting. that is, when tcnt for a channel designated for synchronous operation is rewritten, the tcnt counters for the other channels are also rewritten at the same time. synchronous clearing of the tcnt counters is also possible by setting the timer synchronization bits in tsyr for channels designated for synchronous operation. buffer operation when tgr is an output compare register when a compare match occurs, the value in the buffer register for the relevant channel is transferred to tgr. when tgr is an input capture register when input capture occurs, the value in tcnt is transfer to tgr and the value previously held in tgr is transferred to the buffer register. cascaded operation (h8s/2237 series only): the channel 1 counter (tcnt1), channel 2 counter (tcnt2), channel 4 counter (tcnt4), and channel 5 counter (tcnt5) can be connected together to operate as a 32-bit counter. pwm mode: in this mode, a pwm waveform is output. the output level can be set by means of tior. a pwm waveform with a duty of between 0% and 100% can be output, according to the setting of each tgr register. phase counting mode: in this mode, tcnt is incremented or decremented by detecting the phases of two clocks input from the external clock input pins in channels 1, 2, 4, and 5. when phase counting mode is set, the corresponding tclk pin functions as the clock pin, and tcnt performs up- or down-counting. this can be used for two-phase encoder pulse input.
331 10.4.2 basic functions counter operation: when one of bits cst0 to cst5 is set to 1 in tstr, the tcnt counter for the corresponding channel starts counting. tcnt can operate as a free-running counter, periodic counter, and so on. example of count operation setting procedure figure 10-7 shows an example of the count operation setting procedure. select counter clock operation selection select counter clearing source periodic counter set period start count operation [1] [2] [4] [3] [5] free-running counter start count operation [5] [1] [2] [3] [4] [5] select output compare register select the counter clock with bits tpsc2 to tpsc0 in tcr. at the same time, select the input clock edge with bits ckeg1 and ckeg0 in tcr. for periodic counter operation, select the tgr to be used as the tcnt clearing source with bits cclr2 to cclr0 in tcr. designate the tgr selected in [2] as an output compare register by means of tior. set the periodic counter cycle in the tgr selected in [2]. set the cst bit in tstr to 1 to start the counter operation. figure 10-7 example of counter operation setting procedure
332 free-running count operation and periodic count operation immediately after a reset, the tpu? tcnt counters are all designated as free-running counters. when the relevant bit in tstr is set to 1 the corresponding tcnt counter starts up- count operation as a free-running counter. when tcnt overflows (from h'ffff to h'0000), the tcfv bit in tsr is set to 1. if the value of the corresponding tciev bit in tier is 1 at this point, the tpu requests an interrupt. after overflow, tcnt starts counting up again from h'0000. figure 10-8 illustrates free-running counter operation. tcnt value h'ffff h'0000 cst bit tcfv time figure 10-8 free-running counter operation when compare match is selected as the tcnt clearing source, the tcnt counter for the relevant channel performs periodic count operation. the tgr register for setting the period is designated as an output compare register, and counter clearing by compare match is selected by means of bits cclr2 to cclr0 in tcr. after the settings have been made, tcnt starts up-count operation as periodic counter when the corresponding bit in tstr is set to 1. when the count value matches the value in tgr, the tgf bit in tsr is set to 1 and tcnt is cleared to h'0000. if the value of the corresponding tgie bit in tier is 1 at this point, the tpu requests an interrupt. after a compare match, tcnt starts counting up again from h'0000.
333 figure 10-9 illustrates periodic counter operation. tcnt value tgr h'0000 cst bit tgf time counter cleared by tgr compare match flag cleared by software or dtc activation figure 10-9 periodic counter operation waveform output by compare match: the tpu can perform 0, 1, or toggle output from the corresponding output pin using compare match. example of setting procedure for waveform output by compare match figure 10-10 shows an example of the setting procedure for waveform output by compare match. select waveform output mode output selection set output timing start count operation [1] [2] [3] [1] select initial value 0 output or 1 output, and compare match output value 0 output, 1 output, or toggle output, by means of tior. the set initial value is output at the tioc pin until the first compare match occurs. [2] set the timing for compare match generation in tgr. [3] set the cst bit in tstr to 1 to start the count operation. figure 10-10 example of setting procedure for waveform output by compare match
334 examples of waveform output operation figure 10-11 shows an example of 0 output/1 output. in this example tcnt has been designated as a free-running counter, and settings have been made so that 1 is output by compare match a, and 0 is output by compare match b. when the set level and the pin level coincide, the pin level does not change. tcnt value h'ffff h'0000 tioca tiocb time tgra tgrb no change no change no change no change 1 output 0 output figure 10-11 example of 0 output/1 output operation figure 10-12 shows an example of toggle output. in this example tcnt has been designated as a periodic counter (with counter clearing performed by compare match b), and settings have been made so that output is toggled by both compare match a and compare match b. tcnt value h'ffff h'0000 tiocb tioca time tgrb tgra toggle output toggle output counter cleared by tgrb compare match figure 10-12 example of toggle output operation
335 input capture function: the tcnt value can be transferred to tgr on detection of the tioc pin input edge. rising edge, falling edge, or both edges can be selected as the detected edge. for channels 0, 1, 3, and 4, it is also possible to specify another channel? counter input clock or compare match signal as the input capture source. note: when another channel? counter input clock is used as the input capture input for channels 0 and 3, ?1 should not be selected as the counter input clock used for input capture input. input capture will not be generated if ?1 is selected. example of input capture operation setting procedure figure 10-13 shows an example of the input capture operation setting procedure. select input capture input input selection start count [1] [2] [1] designate tgr as an input capture register by means of tior, and select rising edge, falling edge, or both edges as the input capture source and input signal edge. [2] set the cst bit in tstr to 1 to start the count operation. figure 10-13 example of input capture operation setting procedure
336 example of input capture operation figure 10-14 shows an example of input capture operation. in this example both rising and falling edges have been selected as the tioca pin input capture input edge, falling edge has been selected as the tiocb pin input capture input edge, and counter clearing by tgrb input capture has been designated for tcnt. tcnt value h'0180 h'0000 tioca tgra time h'0010 h'0005 counter cleared by tiocb input (falling edge) h'0160 h'0005 h'0160 h'0010 tgrb h'0180 tiocb figure 10-14 example of input capture operation
337 10.4.3 synchronous operation in synchronous operation, the values in a number of tcnt counters can be rewritten simultaneously (synchronous presetting). also, a number of tcnt counters can be cleared simultaneously by making the appropriate setting in tcr (synchronous clearing). synchronous operation enables tgr to be incremented with respect to a single time base. channels 0 to 5 can all be designated for synchronous operation. example of synchronous operation setting procedure: figure 10-15 shows an example of the synchronous operation setting procedure. set synchronous operation synchronous operation selection set tcnt synchronous presetting [1] [2] synchronous clearing select counter clearing source [3] start count [5] set synchronous counter clearing [4] start count [5] clearing sourcegeneration channel? no yes [1] [2] [3] [4] [5] set to 1 the sync bits in tsyr corresponding to the channels to be designated for synchronous operation. when the tcnt counter of any of the channels designated for synchronous operation is written to, the same value is simultaneously written to the other tcnt counters. use bits cclr2 to cclr0 in tcr to specify tcnt clearing by input capture/output compare, etc. use bits cclr2 to cclr0 in tcr to designate synchronous clearing for the counter clearing source. set to 1 the cst bits in tstr for the relevant channels, to start the count operation. figure 10-15 example of synchronous operation setting procedure
338 example of synchronous operation: figure 10-16 shows an example of synchronous operation. in this example, synchronous operation and pwm mode 1 have been designated for channels 0 to 2, tgr0b compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. three-phase pwm waveforms are output from pins tioc0a, tioc1a, and tioc2a. at this time, synchronous presetting, and synchronous clearing by tgr0b compare match, is performed for channel 0 to 2 tcnt counters, and the data set in tgr0b is used as the pwm cycle. for details of pwm modes, see section 10.4.6, pwm modes. tcnt0 to tcnt2 values h'0000 tioc0a tioc1a time tgr0b synchronous clearing by tgr0b compare match tgr2a tgr1a tgr2b tgr0a tgr1b tioc2a figure 10-16 example of synchronous operation
339 10.4.4 buffer operation buffer operation, provided for channels 0 and 3, enables tgrc and tgrd to be used as buffer registers. buffer operation differs depending on whether tgr has been designated as an input capture register or as a compare match register. table 10-5 shows the register combinations used in buffer operation. table 10-5 register combinations in buffer operation channel timer general register buffer register 0 tgr0a tgr0c tgr0b tgr0d 3 tgr3a tgr3c tgr3b tgr3d when tgr is an output compare register when a compare match occurs, the value in the buffer register for the corresponding channel is transferred to the timer general register. this operation is illustrated in figure 10-17. buffer register timer general register tcnt comparator compare match signal figure 10-17 compare match buffer operation
340 when tgr is an input capture register when input capture occurs, the value in tcnt is transferred to tgr and the value previously held in the timer general register is transferred to the buffer register. this operation is illustrated in figure 10-18. buffer register timer general register tcnt input capture signal figure 10-18 input capture buffer operation example of buffer operation setting procedure: figure 10-19 shows an example of the buffer operation setting procedure. select tgr function buffer operation set buffer operation start count [1] [2] [3] [1] designate tgr as an input capture register or output compare register by means of tior. [2] designate tgr for buffer operation with bits bfa and bfb in tmdr. [3] set the cst bit in tstr to 1 to start the count operation. figure 10-19 example of buffer operation setting procedure
341 examples of buffer operation when tgr is an output compare register figure 10-20 shows an operation example in which pwm mode 1 has been designated for channel 0, and buffer operation has been designated for tgra and tgrc. the settings used in this example are tcnt clearing by compare match b, 1 output at compare match a, and 0 output at compare match b. as buffer operation has been set, when compare match a occurs the output changes and the value in buffer register tgrc is simultaneously transferred to timer general register tgra. this operation is repeated each time compare match a occurs. for details of pwm modes, see section 10.4.6, pwm modes. tcnt value tgr0b h'0000 tgr0c time tgr0a h'0200 h'0520 tioca h'0200 h'0450 h'0520 h'0450 tgr0a h'0450 h'0200 transfer figure 10-20 example of buffer operation (1)
342 when tgr is an input capture register figure 10-21 shows an operation example in which tgra has been designated as an input capture register, and buffer operation has been designated for tgra and tgrc. counter clearing by tgra input capture has been set for tcnt, and both rising and falling edges have been selected as the tioca pin input capture input edge. as buffer operation has been set, when the tcnt value is stored in tgra upon occurrence of input capture a, the value previously stored in tgra is simultaneously transferred to tgrc. tcnt value h'09fb h'0000 tgrc time h'0532 tioca tgra h'0f07 h'0532 h'0f07 h'0532 h'0f07 h'09fb figure 10-21 example of buffer operation (2)
343 10.4.5 cascaded operation (h8s/2237 series only) in cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. this function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of tcnt2 (tcnt5) as set in bits tpsc2 to tpsc0 in tcr. underflow occurs only when the lower 16-bit tcnt is in phase-counting mode. table 10-6 shows the register combinations used in cascaded operation. note: when phase counting mode is set for channel 1 or 4, the counter clock setting is invalid and the counter operates independently in phase counting mode. table 10-6 cascaded combinations combination upper 16 bits lower 16 bits channels 1 and 2 tcnt1 tcnt2 channels 4 and 5 tcnt4 tcnt5 example of cascaded operation setting procedure: figure 10-22 shows an example of the setting procedure for cascaded operation. set cascading cascaded operation start count [1] [2] [1] set bits tpsc2 to tpsc0 in the channel 1 (channel 4) tcr to b'111 to select tcnt2 (tcnt5) overflow/underflow counting. [2] set the cst bit in tstr for the upper and lower channel to 1 to start the count operation. figure 10-22 cascaded operation setting procedure
344 examples of cascaded operation: figure 10-23 illustrates the operation when counting upon tcnt2 overflow/underflow has been set for tcnt1, tgr1a and tgr2a have been designated as input capture registers, and tioc pin rising edge has been selected. when a rising edge is input to the tioca1 and tioca2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to tgr1a, and the lower 16 bits to tgr2a. tcnt2 clock tcnt2 h'ffff h'0000 h'0001 tioca1, tioca2 tgr1a h'03a2 tgr2a h'0000 tcnt1 clock tcnt1 h'03a1 h'03a2 figure 10-23 example of cascaded operation (1) figure 10-24 illustrates the operation when counting upon tcnt2 overflow/underflow has been set for tcnt1, and phase counting mode has been designated for channel 2. tcnt1 is incremented by tcnt2 overflow and decremented by tcnt2 underflow. tclka tcnt2 fffd tcnt1 0001 tclkb fffe ffff 0000 0001 0002 0001 0000 ffff 0000 0000 figure 10-24 example of cascaded operation (2)
345 10.4.6 pwm modes in pwm mode, pwm waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each tgr. designating tgr compare match as the counter clearing source enables the period to be set in that register. all channels can be designated for pwm mode independently. synchronous operation is also possible. there are two pwm modes, as described below. pwm mode 1 pwm output is generated from the tioca and tiocc pins by pairing tgra with tgrb and tgrc with tgrd. the output specified by bits ioa3 to ioa0 and ioc3 to ioc0 in tior is output from the tioca and tiocc pins at compare matches a and c, and the output specified by bits iob3 to iob0 and iod3 to iod0 in tior is output at compare matches b and d. the initial output value is the value set in tgra or tgrc. if the set values of paired tgrs are identical, the output value does not change when a compare match occurs. in pwm mode 1, a maximum 8-phase pwm output is possible. pwm mode 2 pwm output is generated using one tgr as the cycle register and the others as duty registers. the output specified in tior is performed by means of compare matches. upon counter clearing by a synchronization register compare match, the output value of each pin is the initial value set in tior. if the set values of the cycle and duty registers are identical, the output value does not change when a compare match occurs. in pwm mode 2, a maximum 15-phase pwm output is possible by combined use with synchronous operation. the correspondence between pwm output pins and registers is shown in table 10-7.
346 table 10-7 pwm output registers and output pins output pins channel registers pwm mode 1 pwm mode 2 0 tgr0a tioca0 tioca0 tgr0b tiocb0 tgr0c tiocc0 tiocc0 tgr0d tiocd0 1 tgr1a tioca1 tioca1 tgr1b tiocb1 2 tgr2a tioca2 tioca2 tgr2b tiocb2 3 tgr3a tioca3 tioca3 tgr3b tiocb3 tgr3c tiocc3 tiocc3 tgr3d tiocd3 4 tgr4a tioca4 tioca4 tgr4b tiocb4 5 tgr5a tioca5 tioca5 tgr5b tiocb5 note: in pwm mode 2, pwm output is not possible for the tgr register in which the period is set.
347 example of pwm mode setting procedure: figure 10-25 shows an example of the pwm mode setting procedure. select counter clock pwm mode select counter clearing source select waveform output level [1] [2] [3] set tgr [4] set pwm mode [5] start count [6] [1] select the counter clock with bits tpsc2 to tpsc0 in tcr. at the same time, select the input clock edge with bits ckeg1 and ckeg0 in tcr. [2] use bits cclr2 to cclr0 in tcr to select the tgr to be used as the tcnt clearing source. [3] use tior to designate the tgr as an output compare register, and select the initial value and output value. [4] set the cycle in the tgr selected in [2], and set the duty in the other the tgr. [5] select the pwm mode with bits md3 to md0 in tmdr. [6] set the cst bit in tstr to 1 to start the count operation. figure 10-25 example of pwm mode setting procedure examples of pwm mode operation: figure 10-26 shows an example of pwm mode 1 operation. in this example, tgra compare match is set as the tcnt clearing source, 0 is set for the tgra initial output value and output value, and 1 is set as the tgrb output value. in this case, the value set in tgra is used as the period, and the values set in tgrb registers as the duty.
348 tcnt value tgra h'0000 tioca time tgrb counter cleared by tgra compare match figure 10-26 example of pwm mode operation (1) figure 10-27 shows an example of pwm mode 2 operation. in this example, synchronous operation is designated for channels 0 and 1, tgr1b compare match is set as the tcnt clearing source, and 0 is set for the initial output value and 1 for the output value of the other tgr registers (tgr0a to tgr0d, tgr1a), to output a 5-phase pwm waveform. in this case, the value set in tgr1b is used as the cycle, and the values set in the other tgrs as the duty. tcnt value tgr1b h'0000 tioca0 counter cleared by tgr1b compare match tgr1a tgr0d tgr0c tgr0b tgr0a tiocb0 tiocc0 tiocd0 tioca1 time figure 10-27 example of pwm mode operation (2)
349 figure 10-28 shows examples of pwm waveform output with 0% duty and 100% duty in pwm mode. tcnt value tgra h'0000 tioca time tgrb 0% duty tgrb rewritten tgrb rewritten tgrb rewritten tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously tcnt value tgra h'0000 tioca time tgrb 100% duty tgrb rewritten tgrb rewritten tgrb rewritten output does not change when cycle register and duty register compare matches occur simultaneously 0% duty figure 10-28 example of pwm mode operation (3)
350 10.4.7 phase counting mode in phase counting mode, the phase difference between two external clock inputs is detected and tcnt is incremented/decremented accordingly. this mode can be set for channels 1, 2, 4, and 5. when phase counting mode is set, an external clock is selected as the counter input clock and tcnt operates as an up/down-counter regardless of the setting of bits tpsc2 to tpsc0 and bits ckeg1 and ckeg0 in tcr. however, the functions of bits cclr1 and cclr0 in tcr, and of tior, tier, and tgr are valid, and input capture/compare match and interrupt functions can be used. when overflow occurs while tcnt is counting up, the tcfv flag in tsr is set; when underflow occurs while tcnt is counting down, the tcfu flag is set. the tcfd bit in tsr is the count direction flag. reading the tcfd flag provides an indication of whether tcnt is counting up or down. table 10-8 shows the correspondence between external clock pins and channels. table 10-8 phase counting mode clock input pins external clock pins channels a-phase b-phase when channel 1 or 5 is set to phase counting mode tclka tclkb when channel 2 or 4 is set to phase counting mode tclkc tclkd example of phase counting mode setting procedure: figure 10-29 shows an example of the phase counting mode setting procedure. select phase counting mode phase counting mode start count [1] [2] [1] select phase counting mode with bits md3 to md0 in tmdr. [2] set the cst bit in tstr to 1 to start the count operation. figure 10-29 example of phase counting mode setting procedure
351 examples of phase counting mode operation: in phase counting mode, tcnt counts up or down according to the phase difference between two external clocks. there are four modes, according to the count conditions. phase counting mode 1 figure 10-30 shows an example of phase counting mode 1 operation, and table 10-9 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 10-30 example of phase counting mode 1 operation table 10-9 up/down-count conditions in phase counting mode 1 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level high level high level down-count low level high level low level legend : rising edge : falling edge
352 phase counting mode 2 figure 10-31 shows an example of phase counting mode 2 operation, and table 10-10 summarizes the tcnt up/down-count conditions. tcnt value time down-count up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) figure 10-31 example of phase counting mode 2 operation table 10-10 up/down-count conditions in phase counting mode 2 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level don? care low level don? care low level don? care high level up-count high level don? care low level don? care high level don? care low level down-count legend : rising edge : falling edge
353 phase counting mode 3 figure 10-32 shows an example of phase counting mode 3 operation, and table 10-11 summarizes the tcnt up/down-count conditions. tcnt value time up-count tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) down-count figure 10-32 example of phase counting mode 3 operation table 10-11 up/down-count conditions in phase counting mode 3 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level don? care low level don? care low level don? care high level up-count high level down-count low level don? care high level don? care low level don? care legend : rising edge : falling edge
354 phase counting mode 4 figure 10-33 shows an example of phase counting mode 4 operation, and table 10-12 summarizes the tcnt up/down-count conditions. time tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) up-count down-count tcnt value figure 10-33 example of phase counting mode 4 operation table 10-12 up/down-count conditions in phase counting mode 4 tclka (channels 1 and 5) tclkc (channels 2 and 4) tclkb (channels 1 and 5) tclkd (channels 2 and 4) operation high level up-count low level low level don? care high level high level down-count low level high level don? care low level legend : rising edge : falling edge
355 phase counting mode application example: figure 10-34 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. channel 1 is set to phase counting mode 1, and the encoder pulse a-phase and b-phase are input to tclka and tclkb. channel 0 operates with tcnt counter clearing by tgr0c compare match; tgr0a and tgr0c are used for the compare match function, and are set with the speed control period and position control period. tgr0b is used for input capture, with tgr0b and tgr0d operating in buffer mode. the channel 1 counter input clock is designated as the tgr0b input capture source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed. tgr1a and tgr1b for channel 1 are designated for input capture, channel 0 tgr0a and tgr0c compare matches are selected as the input capture source, and store the up/down-counter values for the control periods. this procedure enables accurate position/speed detection to be achieved.
356 tcnt1 tcnt0 channel 1 tgr1a (speed period capture) tgr0a (speed control period) tgr1b (position period capture) tgr0c (position control period) tgr0b (pulse width capture) tgr0d (buffer operation) channel 0 tclka tclkb edge detection circuit + + figure 10-34 phase counting mode application example 10.5 interrupts 10.5.1 interrupt sources and priorities there are three kinds of tpu interrupt source: tgr input capture/compare match, tcnt overflow, and tcnt underflow. each interrupt source has its own status flag and enable/disabled bit, allowing generation of interrupt request signals to be enabled or disabled individually. when an interrupt request is generated, the corresponding status flag in tsr is set to 1. if the corresponding enable/disable bit in tier is set to 1 at this time, an interrupt is requested. the interrupt request is cleared by clearing the status flag to 0. relative channel priorities can be changed by the interrupt controller, but the priority order within a channel is fixed. for details, see section 5, interrupt controller.
357 table 10-13 lists the tpu interrupt sources. table 10-13 tpu interrupts channel interrupt source description dtc activation priority 0 tgi0a tgr0a input capture/compare match possible high tgi0b tgr0b input capture/compare match possible tgi0c tgr0c input capture/compare match possible tgi0d tgr0d input capture/compare match possible tci0v tcnt0 overflow not possible 1 tgi1a tgr1a input capture/compare match possible tgi1b tgr1b input capture/compare match possible tci1v tcnt1 overflow not possible tci1u tcnt1 underflow not possible 2 tgi2a tgr2a input capture/compare match possible tgi2b tgr2b input capture/compare match possible tci2v tcnt2 overflow not possible tci2u tcnt2 underflow not possible 3 * tgi3a tgr3a input capture/compare match possible tgi3b tgr3b input capture/compare match possible tgi3c tgr3c input capture/compare match possible tgi3d tgr3d input capture/compare match possible tci3v tcnt3 overflow not possible 4 * tgi4a tgr4a input capture/compare match possible tgi4b tgr4b input capture/compare match possible tci4v tcnt4 overflow not possible tci4u tcnt4 underflow not possible 5 * tgi5a tgr5a input capture/compare match possible tgi5b tgr5b input capture/compare match possible tci5v tcnt5 overflow not possible tci5u tcnt5 underflow not possible low note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller. * applies to the h8s/2237 series only.
358 input capture/compare match interrupt: an interrupt is requested if the tgie bit in tier is set to 1 when the tgf flag in tsr is set to 1 by the occurrence of a tgr input capture/compare match on a particular channel. the interrupt request is cleared by clearing the tgf flag to 0. the tpu has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. overflow interrupt: an interrupt is requested if the tciev bit in tier is set to 1 when the tcfv flag in tsr is set to 1 by the occurrence of tcnt overflow on a channel. the interrupt request is cleared by clearing the tcfv flag to 0. the tpu has six overflow interrupts, one for each channel. underflow interrupt: an interrupt is requested if the tcieu bit in tier is set to 1 when the tcfu flag in tsr is set to 1 by the occurrence of tcnt underflow on a channel. the interrupt request is cleared by clearing the tcfu flag to 0. the tpu has four overflow interrupts, one each for channels 1, 2, 4, and 5. 10.5.2 dtc activation dtc activation: the dtc can be activated by the tgr input capture/compare match interrupt for a channel. for details, see section 8, data transfer controller (dtc). a total of 16 tpu input capture/compare match interrupts can be used as dtc activation sources, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5. 10.5.3 a/d converter activation the a/d converter can be activated by the tgra input capture/compare match for a channel. if the ttge bit in tier is set to 1 when the tgfa flag in tsr is set to 1 by the occurrence of a tgra input capture/compare match on a particular channel, a request to start a/d conversion is sent to the a/d converter. if the tpu conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started. in the tpu, a total of six tgra input capture/compare match interrupts can be used as a/d converter conversion start sources, one for each channel.
359 10.6 operation timing 10.6.1 input/output timing tcnt count timing: figure 10-35 shows tcnt count timing in internal clock operation, and figure 10-36 shows tcnt count timing in external clock operation. tcnt tcnt input clock internal clock n? n n+1 n+2 falling edge rising edge figure 10-35 count timing in internal clock operation tcnt tcnt input clock external clock n? n n+1 n+2 rising edge falling edge falling edge figure 10-36 count timing in external clock operation
360 output compare output timing: a compare match signal is generated in the final state in which tcnt and tgr match (the point at which the count value matched by tcnt is updated). when a compare match signal is generated, the output value set in tior is output at the output compare output pin (tioc pin). after a match between tcnt and tgr, the compare match signal is not generated until the tcnt input clock is generated. figure 10-37 shows output compare output timing. tgr tcnt tcnt input clock n n n+1 compare match signal tioc pin figure 10-37 output compare output timing input capture signal timing: figure 10-38 shows input capture signal timing. tcnt input capture input n n+1 n+2 n n+2 tgr input capture signal figure 10-38 input capture input signal timing
361 timing for counter clearing by compare match/input capture: figure 10-39 shows the timing when counter clearing by compare match occurrence is specified, and figure 10-40 shows the timing when counter clearing by input capture occurrence is specified. tcnt counter clear signal compare match signal tgr n n h'0000 figure 10-39 counter clear timing (compare match) tcnt counter clear signal input capture signal tgr n h'0000 n figure 10-40 counter clear timing (input capture)
362 buffer operation timing: figures 10-41 and 10-42 show the timing in buffer operation. tgra, tgrb compare match signal tcnt tgrc, tgrd nn n n n+1 figure 10-41 buffer operation timing (compare match) tgra, tgrb tcnt input capture signal tgrc, tgrd n n n n+1 n n n+1 figure 10-42 buffer operation timing (input capture)
363 10.6.2 interrupt signal timing tgf flag setting timing in case of compare match: figure 10-43 shows the timing for setting of the tgf flag in tsr by compare match occurrence, and tgi interrupt request signal timing. tgr tcnt tcnt input clock n n n+1 compare match signal tgf flag tgi interrupt figure 10-43 tgi interrupt timing (compare match)
364 tgf flag setting timing in case of input capture: figure 10-44 shows the timing for setting of the tgf flag in tsr by input capture occurrence, and tgi interrupt request signal timing. tgr tcnt input capture signal n n tgf flag tgi interrupt figure 10-44 tgi interrupt timing (input capture)
365 tcfv flag/tcfu flag setting timing: figure 10-45 shows the timing for setting of the tcfv flag in tsr by overflow occurrence, and tciv interrupt request signal timing. figure 10-46 shows the timing for setting of the tcfu flag in tsr by underflow occurrence, and tciu interrupt request signal timing. overflow signal tcnt (overflow) tcnt input clock h'ffff h'0000 tcfv flag tciv interrupt figure 10-45 tciv interrupt setting timing underflow signal tcnt (underflow) tcnt input clock h'0000 h'ffff tcfu flag tciu interrupt figure 10-46 tciu interrupt setting timing
366 status flag clearing timing: after a status flag is read as 1 by the cpu, it is cleared by writing 0 to it. when the dtc is activated, the flag is cleared automatically. figure 10-47 shows the timing for status flag clearing by the cpu, and figure 10-48 shows the timing for status flag clearing by the dtc. status flag write signal address ? tsr address interrupt request signal tsr write cycle t1 t2 figure 10-47 timing for status flag clearing by cpu interrupt request signal status flag address source address dtc read cycle t1 t2 destination address t1 t2 dtc write cycle figure 10-48 timing for status flag clearing by dtc activation
367 10.7 usage notes note that the kinds of operation and contention described below occur during tpu operation. input clock restrictions: the input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. the tpu will not operate properly with a narrower pulse width. in phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.5 states, and the pulse width must be at least 2.5 states. figure 10-49 shows the input clock conditions in phase counting mode. overlap phase differ- ence phase differ- ence overlap tclka (tclkc) tclkb (tclkd) pulse width pulse width pulse width pulse width notes: phase difference and overlap pulse width : 1.5 states or more : 2.5 states or more figure 10-49 phase difference, overlap, and pulse width in phase counting mode caution on period setting: when counter clearing by compare match is set, tcnt is cleared in the final state in which it matches the tgr value (the point at which the count value matched by tcnt is updated). consequently, the actual counter frequency is given by the following formula: f = (n + 1) where f : counter frequency : operating frequency n : tgr set value
368 contention between tcnt write and clear operations: if the counter clear signal is generated in the t2 state of a tcnt write cycle, tcnt clearing takes precedence and the tcnt write is not performed. figure 10-50 shows the timing in this case. counter clear signal write signal address tcnt address tcnt tcnt write cycle t1 t2 n h'0000 figure 10-50 contention between tcnt write and clear operations
369 contention between tcnt write and increment operations: if incrementing occurs in the t2 state of a tcnt write cycle, the tcnt write takes precedence and tcnt is not incremented. figure 10-51 shows the timing in this case. tcnt input clock write signal address tcnt address tcnt tcnt write cycle t1 t2 n m tcnt write data figure 10-51 contention between tcnt write and increment operations
370 contention between tgr write and compare match: if a compare match occurs in the t2 state of a tgr write cycle, the tgr write takes precedence and the compare match signal is inhibited. a compare match does not occur even if the same value as before is written. figure 10-52 shows the timing in this case. compare match signal write signal address tgr address tcnt tgr write cycle t1 t2 n m tgr write data tgr n n+1 inhibited figure 10-52 contention between tgr write and compare match
371 contention between buffer register write and compare match: if a compare match occurs in the t2 state of a tgr write cycle, the data transferred to tgr by the buffer operation will be the data prior to the write. figure 10-53 shows the timing in this case. compare match signal write signal address buffer register address buffer register tgr write cycle t1 t2 n tgr n m buffer register write data figure 10-53 contention between buffer register write and compare match
372 contention between tgr read and input capture: if the input capture signal is generated in the t1 state of a tgr read cycle, the data that is read will be the data after input capture transfer. figure 10-54 shows the timing in this case. input capture signal read signal address tgr address tgr tgr read cycle t1 t2 m internal data bus x m figure 10-54 contention between tgr read and input capture
373 contention between tgr write and input capture: if the input capture signal is generated in the t2 state of a tgr write cycle, the input capture operation takes precedence and the write to tgr is not performed. figure 10-55 shows the timing in this case. input capture signal write signal address tcnt tgr write cycle t1 t2 m tgr m tgr address figure 10-55 contention between tgr write and input capture
374 contention between buffer register write and input capture: if the input capture signal is generated in the t2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. figure 10-56 shows the timing in this case. input capture signal write signal address ? tcnt buffer register write cycle t1 t2 n tgr n m m buffer register buffer register address figure 10-56 contention between buffer register write and input capture
375 contention between overflow/underflow and counter clearing: if overflow/underflow and counter clearing occur simultaneously, the tcfv/tcfu flag in tsr is not set and tcnt clearing takes precedence. figure 10-57 shows the operation timing when a tgr compare match is specified as the clearing source, and h'ffff is set in tgr. counter clear signal tcnt input clock ? tcnt tgf disabled tcfv h'ffff h'0000 figure 10-57 contention between overflow and counter clearing
376 contention between tcnt write and overflow/underflow: if there is an up-count or down- count in the t2 state of a tcnt write cycle, and overflow/underflow occurs, the tcnt write takes precedence and the tcfv/tcfu flag in tsr is not set . figure 10-58 shows the operation timing when there is contention between tcnt write and overflow. write signal address tcnt address tcnt tcnt write cycle t1 t2 h'ffff m tcnt write data tcfv flag disabled figure 10-58 contention between tcnt write and overflow multiplexing of i/o pins: in the h8s/2237 series and h8s/2227 series, the tclka input pin is multiplexed with the tiocc0 i/o pin, the tclkb input pin with the tiocd0 i/o pin, the tclkc input pin with the tiocb1 i/o pin, and the tclkd input pin with the tiocb2 i/o pin. when an external clock is input, compare match output should not be performed from a multiplexed pin. interrupts and module stop mode: if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or dtc activation source. interrupts should therefore be disabled before entering module stop mode.
377 section 11 8-bit timers (tmr) 11.1 overview the h8s/2237 series and h8s/2227 series include an 8-bit timer module with two channels (tmr0 and tmr1). each channel has an 8-bit counter (tcnt) and two time constant registers (tcora and tcorb) that are constantly compared with the tcnt value to detect compare match events. the 8-bit timer module can thus be used for a variety of functions, including pulse output with an arbitrary duty cycle. 11.1.1 features the features of the 8-bit timer module are listed below. selection of four clock sources ? the counters can be driven by one of three internal clock signals (?8, ?64, or ?8192) or an external clock input (enabling use as an external event counter). selection of three ways to clear the counters ? the counters can be cleared on compare match a or b, or by an external reset signal. timer output control by a combination of two compare match signals ? the timer output signal in each channel is controlled by a combination of two independent compare match signals, enabling the timer to generate output waveforms with an arbitrary duty cycle or pwm output. provision for cascading of two channels ? operation as a 16-bit timer is possible, using channel 0 for the upper 8 bits and channel 1 for the lower 8 bits (16-bit count mode). ? channel 1 can be used to count channel 0 compare matches (compare match count mode). three independent interrupts ? compare match a and b and overflow interrupts can be requested independently. a/d converter conversion start trigger can be generated ? channel 0 compare match a signal can be used as an a/d converter conversion start trigger. module stop mode can be set ? as the initial setting, 8-bit timer operation is halted. register access is enabled by exiting module stop mode.
378 11.1.2 block diagram figure 11-1 shows a block diagram of the 8-bit timer module. external clock source internal clock sources ?8 ?64 ?8192 clock 1 clock 0 compare match a1 compare match a0 clear 1 cmia0 cmib0 ovi0 cmia1 cmib1 ovi1 interrupt signals tmo0 tmri01 internal bus tcora0 comparator a0 comparator b0 tcorb0 tcsr0 tcr0 tcora1 comparator a1 tcnt1 comparator b1 tcorb1 tcsr1 tcr1 tmci01 tcnt0 overflow 1 overflow 0 compare match b1 compare match b0 tmo1 a/d conversion start request signal clock select control logic clear 0 figure 11-1 block diagram of 8-bit timer
379 11.1.3 pin configuration table 11-1 summarizes the input and output pins of the 8-bit timer. table 11-1 input and output pins of 8-bit timer channel name symbol i/o function 0 timer output pin 0 tmo0 output outputs at compare match 1 timer output pin 1 tmo1 output outputs at compare match all timer clock input pin 01 tmci01 input inputs external clock for counter timer reset input pin 01 tmri01 input inputs external reset to counter 11.1.4 register configuration table 11-2 summarizes the registers of the 8-bit timer module. table 11-2 8-bit timer registers channel name abbreviation r/w initial value address * 1 0 timer control register 0 tcr0 r/w h'00 h'ff68 timer control/status register 0 tcsr0 r/(w) * 2 h'00 h'ff6a time constant register a0 tcora0 r/w h'ff h'ff6c time constant register b0 tcorb0 r/w h'ff h'ff6e timer counter 0 tcnt0 r/w h'00 h'ff70 1 timer control register 1 tcr1 r/w h'00 h'ff69 timer control/status register 1 tcsr1 r/(w) * 2 h'10 h'ff6b time constant register a1 tcora1 r/w h'ff h'ff6d time constant register b1 tcorb1 r/w h'ff h'ff6f timer counter 1 tcnt1 r/w h'00 h'ff71 all module stop control register a mstpcra r/w h'3f h'ffe8 notes: 1. lower 16 bits of the address 2. only 0 can be written to bits 7 to 5, to clear these flags. each pair of registers for channel 0 and channel 1 is a 16-bit register with the upper 8 bits for channel 0 and the lower 8 bits for channel 1, so they can be accessed together by word transfer instruction.
380 11.2 register descriptions 11.2.1 timer counters 0 and 1 (tcnt0, tcnt1) 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w tcnt0 tcnt1 bit initial value r/w : : : tcnt0 and tcnt1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source. this clock source is selected by clock select bits cks2 to cks0 of tcr. the cpu can read or write to tcnt0 and tcnt1 at all times. tcnt0 and tcnt1 comprise a single 16-bit register, so they can be accessed together by word transfer instruction. tcnt0 and tcnt1 can be cleared by an external reset input or by a compare match signal. which signal is to be used for clearing is selected by clock clear bits cclr1 and cclr0 of tcr. when a timer counter overflows from h'ff to h'00, ovf in tcsr is set to 1. tcnt0 and tcnt1 are each initialized to h'00 by a reset and in hardware standby mode. 11.2.2 time constant registers a0 and a1 (tcora0, tcora1) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 tcora1 bit initial value r/w : : : tcora0 and tcora1 are 8-bit readable/writable registers. tcora0 and tcora1 comprise a single 16-bit register so they can be accessed together by word transfer instruction. tcora is continually compared with the value in tcnt. when a match is detected, the corresponding cmfa flag of tcsr is set. note, however, that comparison is disabled during the t2 state of a tcor write cycle. the timer output can be freely controlled by these compare match signals and the settings of bits os1 and os0 of tcsr. tcora0 and tcora1 are each initialized to h'ff by a reset and in hardware standby mode.
381 11.2.3 time constant registers b0 and b1 (tcorb0, tcorb1) 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb0 tcorb1 bit initial value r/w : : : tcorb0 and tcorb1 are 8-bit readable/writable registers. tcorb0 and tcorb1 comprise a single 16-bit register so they can be accessed together by word transfer instruction. tcorb is continually compared with the value in tcnt. when a match is detected, the corresponding cmfb flag of tcsr is set. note, however, that comparison is disabled during the t2 state of a tcor write cycle. the timer output can be freely controlled by these compare match signals and the settings of output select bits os3 and os2 of tcsr. tcorb0 and tcorb1 are each initialized to h'ff by a reset and in hardware standby mode. 11.2.4 timer control registers 0 and 1 (tcr0, tcr1) 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value r/w : : : tcr0 and tcr1 are 8-bit readable/writable registers that select the input clock source and the time at which tcnt is cleared, and enable interrupts. tcr0 and tcr1 are each initialized to h'00 by a reset and in hardware standby mode. for details of this timing, see section 11.3, operation.
382 bit 7?ompare match interrupt enable b (cmieb): selects whether cmfb interrupt requests (cmib) are enabled or disabled when the cmfb flag of tcsr is set to 1. bit 7 cmieb description 0 cmfb interrupt requests (cmib) are disabled (initial value) 1 cmfb interrupt requests (cmib) are enabled bit 6?ompare match interrupt enable a (cmiea): selects whether cmfa interrupt requests (cmia) are enabled or disabled when the cmfa flag of tcsr is set to 1. bit 6 cmiea description 0 cmfa interrupt requests (cmia) are disabled (initial value) 1 cmfa interrupt requests (cmia) are enabled bit 5?imer overflow interrupt enable (ovie): selects whether ovf interrupt requests (ovi) are enabled or disabled when the ovf flag of tcsr is set to 1. bit 5 ovie description 0 ovf interrupt requests (ovi) are disabled (initial value) 1 ovf interrupt requests (ovi) are enabled bits 4 and 3?ounter clear 1 and 0 (cclr1 and cclr0): these bits select the method by which tcnt is cleared: by compare match a or b, or by an external reset input. bit 4 bit 3 cclr1 cclr0 description 0 0 clear is disabled (initial value) 1 clear by compare match a 1 0 clear by compare match b 1 clear by rising edge of external reset input
383 bits 2 to 0?lock select 2 to 0 (cks2 to cks0): these bits select whether the clock input to tcnt is an internal or external clock. three internal clocks can be selected, all divided from the system clock (?: ?8, ?64, and ?8192. the falling edge of the selected internal clock triggers the count. when use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. some functions differ between channel 0 and channel 1. bit 2 bit 1 bit 0 cks2 cks1 cks0 description 0 0 0 clock input disabled (initial value) 1 internal clock, counted at falling edge of ?8 1 0 internal clock, counted at falling edge of ?64 1 internal clock, counted at falling edge of ?8192 1 0 0 for channel 0: count at tcnt1 overflow signal * for channel 1: count at tcnt0 compare match a * 1 external clock, counted at rising edge 1 0 external clock, counted at falling edge 1 external clock, counted at both rising and falling edges note: * if the count input of channel 0 is the tcnt1 overflow signal and that of channel 1 is the tcnt0 compare match signal, no incrementing clock is generated. do not use this setting.
384 11.2.5 timer control/status registers 0 and 1 (tcsr0, tcsr1) 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w only 0 can be written to bits 7 to 5, to clear these flags. bit initial value r/w : : : note: * 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 1 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value r/w : : : tcsr0 tcsr1 tcsr0 and tcsr1 are 8-bit registers that display compare match and overflow statuses, and control compare match output. tcsr0 is initialized to h'00, and tcsr1 to h'10, by a reset and in hardware standby mode. bit 7?ompare match flag b (cmfb): status flag indicating whether the values of tcnt and tcorb match. bit 7 cmfb description 0 [clearing conditions] (initial value) cleared by reading cmfb when cmfb = 1, then writing 0 to cmfb when dtc is activated by cmib interrupt while disel bit of mrb in dtc is 0 1 [setting condition] set when tcnt matches tcorb bit 6?ompare match flag a (cmfa): status flag indicating whether the values of tcnt and tcora match.
385 bit 6 cmfa description 0 [clearing conditions] (initial value) cleared by reading cmfa when cmfa = 1, then writing 0 to cmfa when dtc is activated by cmia interrupt while disel bit of mrb in dtc is 0 1 [setting condition] set when tcnt matches tcora bit 5?imer overflow flag (ovf): status flag indicating that tcnt has overflowed (changed from h'ff to h'00). bit 5 ovf description 0 [clearing condition] (initial value) cleared by reading ovf when ovf = 1, then writing 0 to ovf 1 [setting condition] set when tcnt overflows from h'ff to h'00 bit 4?/d trigger enable (adte) (tcsr0 only): selects enabling or disabling of a/d converter start requests by compare-match a. in tcsr1, this bit is reserved: it is always read as 1 and cannot be modified. bit 4 adte description 0 a/d converter start requests by compare match a are disabled (initial value) 1 a/d converter start requests by compare match a are enabled bits 3 to 0?utput select 3 to 0 (os3 to os0): these bits specify how the timer output level is to be changed by a compare match of tcor and tcnt. bits os3 and os2 select the effect of compare match b on the output level, bits os1 and os0 select the effect of compare match a on the output level, and both of them can be controlled independently. note, however, that priorities are set such that: toggle output > 1 output > 0 output. if compare matches occur simultaneously, the output changes according to the compare match with the higher priority. timer output is disabled when bits os3 to os0 are all 0.
386 after a reset, the timer output is 0 until the first compare match event occurs. bit 3 bit 2 os3 os2 description 0 0 no change when compare match b occurs (initial value) 1 0 is output when compare match b occurs 1 0 1 is output when compare match b occurs 1 output is inverted when compare match b occurs (toggle output) bit 1 bit 0 os1 os0 description 0 0 no change when compare match a occurs (initial value) 1 0 is output when compare match a occurs 1 0 1 is output when compare match a occurs 1 output is inverted when compare match a occurs (toggle output)
387 11.2.6 module stop control register a (mstpcra) 7 mstpa7 0 r/w bit initial value r/w : : : 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w 0 mstpa0 1 r/w mstpcra is an 8-bit readable/writable register that performs module stop mode control. when the mstpa4 bit in mstpcr is set to 1, the 8-bit timer operation stops at the end of the bus cycle and a transition is made to module stop mode. for details, see section 20.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 4?odule stop (mstpa4): specifies the tmr0 and tmr1 module stop mode. bit 4 mstpa4 description 0 tmr0, tmr1 module stop mode cleared 1 tmr0, tmr1 module stop mode set (initial value)
388 11.3 operation 11.3.1 tcnt incrementation timing tcnt is incremented by input clock pulses (either internal or external). internal clock: three different internal clock signals (?8, ?64, or ?8192) divided from the system clock (? can be selected, by setting bits cks2 to cks0 in tcr. figure 11-2 shows the count timing. internal clock clock input to tcnt tcnt n? n n+1 figure 11-2 count timing for internal clock input external clock: three incrementation methods can be selected by setting bits cks2 to cks0 in tcr: at the rising edge, the falling edge, and both rising and falling edges. note that the external clock pulse width must be at least 1.5 states for incrementation at a single edge, and at least 2.5 states for incrementation at both edges. the counter will not increment correctly if the pulse width is less than these values. figure 11-3 shows the timing of incrementation at both edges of an external clock signal.
389 external clock input clock input to tcnt tcnt n? n n+1 figure 11-3 count timing for external clock input 11.3.2 compare match timing setting of compare match flags a and b (cmfa, cmfb): the cmfa and cmfb flags in tcsr are set to 1 by a compare match signal generated when the tcor and tcnt values match. the compare match signal is generated at the last state in which the match is true, just before the timer counter is updated. therefore, when tcor and tcnt match, the compare match signal is not generated until the next incrementation clock input. figure 11-4 shows this timing. tcnt n n+1 tcor n compare match signal cmf figure 11-4 timing of cmf setting
390 timer output timing: when compare match a or b occurs, the timer output changes a specified by bits os3 to os0 in tcsr. depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. figure 11-5 shows the timing when the output is set to toggle at compare match a. compare match a signal timer output pin figure 11-5 timing of timer output timing of compare match clear: the timer counter is cleared when compare match a or b occurs, depending on the setting of the cclr1 and cclr0 bits in tcr. figure 11-6 shows the timing of this operation. n h'00 compare match signal tcnt figure 11-6 timing of compare match clear
391 11.3.3 timing of external reset on tcnt tcnt is cleared at the rising edge of an external reset input, depending on the settings of the cclr1 and cclr0 bits in tcr. the clear pulse width must be at least 1.5 states. figure 11-7 shows the timing of this operation. clear signal external reset input pin tcnt n h'00 n? figure 11-7 timing of external reset 11.3.4 timing of overflow flag (ovf) setting the ovf in tcsr is set to 1 when the timer count overflows (changes from h'ff to h'00). figure 11-8 shows the timing of this operation. ovf overflow signal tcnt h'ff h'00 figure 11-8 timing of ovf setting
392 11.3.5 operation with cascaded connection if bits cks2 to cks0 in either tcr0 or tcr1 are set to b'100, the 8-bit timers of the two channels are cascaded. with this configuration, a single 16-bit timer could be used (16-bit timer mode) or compare matches of the 8-bit timer channel 0 could be counted by the timer of channel 1 (compare match counter mode). in this case, the timer operates as below. 16-bit counter mode: when bits cks2 to cks0 in tcr0 are set to b'100, the timer functions as a single 16-bit timer with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits. setting of compare match flags ? the cmf flag in tcsr0 is set to 1 when a 16-bit compare match event occurs. ? the cmf flag in tcsr1 is set to 1 when a lower 8-bit compare match event occurs. counter clear specification ? if the cclr1 and cclr0 bits in tcr0 have been set for counter clear at compare match, the 16-bit counter (tcnt0 and tcnt1 together) is cleared when a 16-bit compare match event occurs. the 16-bit counter (tcnt0 and tcnt1 together) is cleared even if counter clear by the tmri01 pin has also been set. ? the settings of the cclr1 and cclr0 bits in tcr1 are ignored. the lower 8 bits cannot be cleared independently. pin output ? control of output from the tmo0 pin by bits os3 to os0 in tcsr0 is in accordance with the 16-bit compare match conditions. ? control of output from the tmo1 pin by bits os3 to os0 in tcsr1 is in accordance with the lower 8-bit compare match conditions. compare match counter mode: when bits cks2 to cks0 in tcr1 are b'100, tcnt1 counts compare match a? for channel 0. channels 0 and 1 are controlled independently. conditions such as setting of the cmf flag, generation of interrupts, output from the tmo pin, and counter clear are in accordance with the settings for each channel. note on usage: if the 16-bit counter mode and compare match counter mode are set simultaneously, the input clock pulses for tcnt0 and tcnt1 are not generated and thus the counters will stop operating. software should therefore avoid using both these modes.
393 11.4 interrupts 11.4.1 interrupt sources and dtc activation there are three 8-bit timer interrupt sources: cmia, cmib, and ovi. their relative priorities are shown in table 11-3. each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in tcr, and independent interrupt requests are sent for each to the interrupt controller. it is also possible to activate the dtc by means of cmia and cmib interrupts. table 11-3 8-bit timer interrupt sources channel interrupt source description dtc activation priority 0 cmia0 interrupt by cmfa possible high cmib0 interrupt by cmfb possible ovi0 interrupt by ovf not possible 1 cmia1 interrupt by cmfa possible cmib1 interrupt by cmfb possible ovi1 interrupt by ovf not possible low note: this table shows the initial state immediately after a reset. the relative channel priorities can be changed by the interrupt controller. 11.4.2 a/d converter activation the a/d converter can be activated only by channel 0 compare match a. if the adte bit in tcsr0 is set to 1 when the cmfa flag is set to 1 by the occurrence of channel 0 compare match a, a request to start a/d conversion is sent to the a/d converter. if the 8-bit timer conversion start trigger has been selected on the a/d converter side at this time, a/d conversion is started.
394 11.5 sample application in the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 11-9. the control bits are set as follows: [1] in tcr, bit cclr1 is cleared to 0 and bit cclr0 is set to 1 so that the timer counter is cleared when its value matches the constant in tcora. [2] in tcsr, bits os3 to os0 are set to b'0110, causing the output to change to 1 at a tcora compare match and to 0 at a tcorb compare match. with these settings, the 8-bit timer provides output of pulses at a rate determined by tcora with a pulse width determined by tcorb. no software intervention is required. tcnt h'ff counter clear tcora tcorb h'00 tmo figure 11-9 example of pulse output
395 11.6 usage notes application programmers should note that the following kinds of contention can occur in the 8-bit timer. 11.6.1 contention between tcnt write and clear if a timer counter clock pulse is generated during the t2 state of a tcnt write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. figure 11-10 shows this operation. address tcnt address internal write signal counter clear signal tcnt n h'00 t1 t2 tcnt write cycle by cpu figure 11-10 contention between tcnt write and clear
396 11.6.2 contention between tcnt write and increment if a timer counter clock pulse is generated during the t2 state of a tcnt write cycle, the write takes priority and the counter is not incremented. figure 11-11 shows this operation. address tcnt address internal write signal tcnt input clock tcnt nm t1 t2 tcnt write cycle by cpu counter write data figure 11-11 contention between tcnt write and increment
397 11.6.3 contention between tcor write and compare match during the t2 state of a tcor write cycle, the tcor write has priority and the compare match signal is disabled even if a compare match event occurs. figure 11-12 shows this operation. address tcor address internal write signal tcnt tcor nm t1 t2 tcor write cycle by cpu tcor write data n n+1 compare match signal disabled figure 11-12 contention between tcor write and compare match
398 11.6.4 contention between compare matches a and b if compare match events a and b occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match a and compare match b, as shown in table 11-4. table 11-4 timer output priorities output setting priority toggle output high 1 output 0 output no change low 11.6.5 switching of internal clocks and tcnt operation tcnt may increment erroneously when the internal clock is switched over. table 11-5 shows the relationship between the timing at which the internal clock is switched (by writing to the cks1 and cks0 bits) and the tcnt operation. when the tcnt clock is generated from an internal clock, the falling edge of the internal clock pulse is detected. if clock switching causes a change from high to low level, as shown in case 3 in table 11-5, a tcnt clock pulse is generated on the assumption that the switchover is a falling edge. this increments tcnt. the erroneous incrementation can also happen when switching between internal and external clocks.
399 table 11-5 switching of internal clock and tcnt operation no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 1 switching from low to low * 1 clock before switchover clock after switchover tcnt clock tcnt cks bit write n n+1 2 switching from low to high * 2 clock before switchover clock after switchover tcnt clock tcnt cks bit write n n+1 n+2 3 switching from high to low * 3 clock before switchover clock after switchover tcnt clock tcnt cks bit write n n+1 n+2 * 4
400 table 11-5 switching of internal clock and tcnt operation (cont) no. timing of switchover by means of cks1 and cks0 bits tcnt clock operation 4 switching from high to high clock before switchover clock after switchover tcnt clock tcnt cks bit write n n+1 n+2 notes: 1. includes switching from low to stop, and from stop to low. 2. includes switching from stop to high. 3. includes switching from high to stop. 4. generated on the assumption that the switchover is a falling edge; tcnt is incremented. 11.6.6 interrupts and module stop mode if module stop mode is entered when an interrupt has been requested, it will not be possible to clear the cpu interrupt source or dtc activation source. interrupts should therefore be disabled before entering module stop mode.
401 section 12 watchdog timer (wdt) 12.1 overview the h8s/2237 series and h8s/2227 series have an on-chip watchdog timer/watch timer with two channels (wdt0 and wdt1). the watchdog timer can generate an internal reset signal if a system crash prevents the cpu from writing to the counter, allowing it to overflow. when this watchdog function is not needed, the wdt can be used as an interval timer. in interval timer mode, an interval timer interrupt is generated each time the counter overflows. 12.1.1 features wdt features are listed below. switchable between watchdog timer mode and interval timer mode internal reset or internal interrupt generated when watchdog timer mode ? wdt0 choice of whether or not an internal reset (power-on reset or manual reset selectable) is effected when the counter overflows ? wdt1 choice of internal power-on reset or nmi interrupt generation when the counter overflows interrupt generation in interval timer mode ? an interval timer interrupt is generated when the counter overflows choice of 8 (wdt0) or 16 (wdt1) counter input clocks ? maximum wdt interval: system clock period 131072 256 ? subclock can be selected for the wdt1 input counter maximum interval when the subclock is selected: subclock period 256 256 selected clock can be output from the buzz output pin (wdt1)
402 12.1.2 block diagram figures 12.1 (a) and (b) show block diagrams of wdt0 and wdt1. overflow wovi0 (interrupt request signal) internal reset signal * tcnt rstcsr tcsr ?2 ?64 ?128 ?512 ?2048 ?8192 ?32768 ?131072 clock clock select internal clock bus interface module bus internal bus wdt legend: tcsr: timer control/status register tcnt: timer counter rstcsr: reset control/status register note: * the internal reset signal can be generated by means of a register setting. either a power-on reset or a manual reset can be selected. interrupt control reset control figure 12.1 (a) block diagram of wdt0
403 overflow tcnt tcsr ?2 ?64 ?128 ?512 ?2048 ?8192 ?32768 ?131072 clock clock select interrupt control reset control internal clock source bus interface module bus internal bus wdt wovi1 (interrupt request signal) internal reset signal * buzz internal nmi (interrupt request signal) legend: tcsr: timer control/status register tcnt: timer counter note: * the internal reset signal can be generated by means of a register setting. the generated reset is a power-on reset. sub /2 sub /4 sub /8 sub /16 sub /32 sub /64 sub /128 sub /256 figure 12.1 (b) block diagram of wdt1 12.1.3 pin configuration table 12.1 describes the wdt input pin. table 12.1 wdt pin name symbol i/o function buzzer output buzz output outputs clock selected by watchdog timer (wdt1)
404 12.1.4 register configuration the wdt has five registers, as summarized in table 12.2. these registers control clock selection, wdt mode switching, the reset signal, etc. table 12.2 wdt registers address * 1 channel name abbreviation r/w initial value write * 2 read 0 timer control/status register 0 tcsr0 r/(w) * 3 h'00 h'ff74 h'ff74 timer counter 0 tcnt0 r/w h'00 h'ff74 h'ff75 reset control/status register rstcsr0 r/(w) * 3 h'1f h'ff76 h'ff77 1 timer control/status register 1 tcsr1 r/(w) * 3 h'00 h'ffa2 h'ffa2 timer counter 1 tcnt1 r/w h'00 h'ffa2 h'ffa3 common pin function control register pfcr r/w h'0d/h'00 * 4 h'fdeb h'fdeb notes: 1. lower 16 bits of the address. 2. for details of write operations, see section 12.2.5, notes on register access. 3. only 0 can be written in bit 7, to clear the flag. 4. initialized to h'0d in modes 4 and 5, and to h'00 in modes 6 and 7.
405 12.2 register descriptions 12.2.1 timer counter (tcnt) 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value read/write tcnt is an 8-bit readable/writable* up-counter. when the tme bit is set to 1 in tcsr, tcnt starts counting pulses generated from the internal clock source selected by bits cks2 to cks0 in tcsr. when the count overflows (changes from h'ff to h'00), the ovf flag in tcsr is set to 1. tcnt is initialized to h'00 by a reset, in hardware standby mode, or when the tme bit is cleared to 0. it is not initialized in software standby mode. note: * tcnt is write-protected by a password to prevent accidental overwriting. for details see section 12.2.5, notes on register access. 12.2.2 timer control/status register (tcsr) tcsr0 7 ovf 0 r/(w) * 6 wt/it 0 r/w 5 tme 0 r/w 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write note: * only 0 can be written, to clear the flag.
406 tcsr1 bit initial value read/write note: * only 0 can be written, to clear the flag. 7 ovf 0 r/(w) * 6 wt/it 0 r/w 5 tme 0 r/w 4 pss 0 r/w 3 rst/nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w tcsr is an 8-bit readable/writable* register. its functions include selecting the clock source to be input to tcnt, and the timer mode. tcr is initialized to h'18 (h'00) by a reset and in hardware standby mode. it is not initialized in software standby mode. note: * tcsr is write-protected by a password to prevent accidental overwriting. for details see section 12.2.5, notes on register access. bit 7?verflow flag (ovf): a status flag that indicates that tcnt has overflowed from h'ff to h'00. bit 7 ovf description 0 [clearing conditions] write 0 in the tme bit (only applies to wdt1) read tcsr when ovf = 1, then write 0 in ovfa (initial value) 1 [setting condition] when tcnt overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset.
407 bit 6?imer mode select (wt/ it ): selects whether the wdt is used as a watchdog timer or interval timer. if wdt0 is used in watchdog timer mode, it can generate a reset when tcnt overflows. if wdt0 is used in interval timer mode, it generates a wovi interrupt request to the cpu when tcnt overflows. when tcnt overflows, wdt1 generates a power-on reset or nmi interrupt request if used in watchdog timer mode, and a wovi interrupt request if used in interval timer mode. wdt0 mode selection wdt0 tcsr wt/ it description 0 interval timer mode: interval timer interrupt (wovi) request is sent to cpu when tcnt overflows (initial value) 1 watchdog timer mode: internal reset can be selected when tcnt overflows * note: * for details of the case where tcnt overflows in watchdog timer mode, see section 12.2.3, reset control/status register (rstcsr). wdt1 mode selection wdt1 tcsr wt/ it description 0 interval timer mode: interval timer interrupt (wovi) request is sent to cpu when tcnt overflows (initial value) 1 watchdog timer mode: power-on reset or nmi interrupt request is sent to cpu when tcnt overflows bit 5?imer enable (tme): selects whether tcnt runs or is halted. bit 5 tme description 0 tcnt is initialized to h'00 and count operation is halted (initial value) 1 tcnt counts wdt0 tcsr bit 4?eserved: this bit cannot be modified and is always read as 1.
408 wdt1 tcsr bit 4?rescaler select (pss): selects the input clock source for tcnt in wdt1. for details, see the description of the cks2 to cks0 bits below. wdt1 tcsr bit 4 pss description 0 tcnt counts ?based prescaler (psm) divided clock pulses (initial value) 1 tcnt counts ?ub-based prescaler (pss) divided clock pulses wdt0 tcsr bit 3?eserved: this bit cannot be modified and is always read as 1. wdt1 tcsr bit 3?ower-on reset or nmi (rst/ nmi ): specifies whether a power-on reset or nmi interrupt is requested on tcnt overflow in watchdog timer mode. bit 3 rst/ nmi description 0 an nmi interrupt is requested (initial value) 1 a power-on reset is requested bits 2 to 0?lock select 2 to 0 (cks2 to cks0): these bits select an internal clock source, obtained by dividing the system clock (?, or subclock (?ub) for input to tcnt. wdt0 input clock selection bit 2 bit 1 bit 0 description cks2 cks1 cks0 clock overflow period * (when ?= 10 mhz) 0 0 0 ?2 (initial value) 51.2 m s 1 ?64 1.6 ms 1 0 ?128 3.2 ms 1 ?512 13.2 ms 1 0 0 ?2048 52.4 ms 1 ?8192 209.8 ms 1 0 ?32768 838.8 ms 1 ?131072 3.368 s note: * the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs.
409 wdt1 input clock selection bit 4 bit 2 bit 1 bit 0 description pss cks2 cks1 cks0 clock overflow period * (when ?= 10 mhz and sub = 32.768 khz) 0000 ?2 (initial value) 51.2 m s 1 ?64 1.6 ms 1 0 ?128 3.2 ms 1 ?512 13.2 ms 1 0 0 ?2048 52.4 ms 1 ?8192 209.8 ms 1 0 ?32768 838.8 ms 1 ?131072 3.36 s 1000 ?ub/2 15.6 ms 1 ?ub/4 31.3 ms 1 0 ?ub/8 62.5 ms 1 ?ub/16 125 ms 1 0 0 ?ub/32 250 ms 1 ?ub/64 500 ms 1 0 ?ub/128 1 s 1 ?ub/256 2 s note: * the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs.
410 12.2.3 reset control/status register (rstcsr) (wdt0 only) 7 wovf 0 r/(w) * 6 rste 0 r/w 5 rsts 0 r/w 4 1 3 1 0 1 2 1 1 1 bit initial value read/write note: * only 0 can be written, to clear the flag. rstcsr is an 8-bit readable/writable* register that controls the generation of the internal reset signal when tcnt overflows, and selects the type of internal reset signal. rstcsr is initialized to h'1f by a reset signal from the res pin, but not by the internal reset signal caused by a wdt overflow. note: * rstcsr is write-protected by a password to prevent accidental overwriting. for details see section 12.2.5, notes on register access. bit 7?atchdog overflow flag (wovf): indicates that tcnt has overflowed (from h'ff to h'00) during watchdog timer operation. this bit is not set in interval timer mode. bit 7 wovf description 0 [clearing condition] (initial value) cleared by reading tcsr when wovf = 1, then writing 0 to wovf 1 [setting condition] when tcnt overflows (from h?f to h?0) in watchdog timer mode bit 6?eset enable (rste): specifies whether or not an internal reset signal is generated if tcnt overflows in watchdog timer mode. bit 6 rste description 0 no internal reset when tcnt overflows * (initial value) 1 internal reset is generated when tcnt overflows note: * the chip is not reset internally, but tcnt and tcsr in wdt0 are reset.
411 bit 5?eset select (rsts): selects the type of internal reset generated if tcnt overflows in watchdog timer mode. for details of the types of resets, see section 4, exception handling. bit 5 rsts description 0 power-on reset (initial value) 1 manual reset bits 4 to 0?eserved: these bits cannot be modified and are always read as 1.
412 12.2.4 pin function control register (pfcr) 7 0 0 r/w 6 0 0 r/w 5 buzze 0 0 r/w 4 0 0 r/w 3 ae3 1 0 r/w 0 ae0 1 0 r/w 2 ae2 1 0 r/w 1 ae1 0 0 r/w bit modes 4 and 5 initial value modes 6 and 7 initial value read/write pfcr is an 8-bit readable/writable register that performs address output control in external expanded mode. only bit 5 is described here. for details of the other bits, see section 7.2.6, pin function control register (pfcr). bit 5?uzz output enable (buzze): enables or disables buzz output from the pf1 pin. the wdt1 input clock selected with bits pss and cks2 to cks0 is output as the buzz signal. bit 5 buzze description 0 functions as pf1 i/o pin (initial value) 1 functions as buzz output pin
413 12.2.5 notes on register access the watchdog timer? tcnt, tcsr, and rstcsr registers differ from other registers in being more difficult to write to. the procedures for writing to and reading these registers are given below. writing to tcnt and tcsr: these registers must be written to by a word transfer instruction. they cannot be written to with byte transfer instructions. figure 12.2 shows the format of data written to tcnt and tcsr. tcnt and tcsr both have the same write address. for a write to tcnt, the upper byte of the written word must contain h'5a and the lower byte must contain the write data. for a write to tcsr, the upper byte of the written word must contain h'a5 and the lower byte must contain the write data. this transfers the write data from the lower byte to tcnt or tcsr. tcnt write tcsr write address: h'ff74 address: h'ff74 h'5a write data 15 8 7 0 h'a5 write data 15 8 7 0 figure 12.2 format of data written to tcnt and tcsr (example of wdt0) writing to rstcsr: rstcsr must be written to by a word transfer to address h'ffbe. it cannot be written to with byte instructions. figure 12-3 shows the format of data written to rstcsr. the method of writing 0 to the wovf bit differs from that for writing to the rste and rsts bits. to write 0 to the wovf bit, the upper byte of the written word must contain h'a5 and the lower byte must contain h'00. this clears the wovf bit to 0, but has no effect on the rste and rsts bits. to write to the rste and rsts bits, the upper byte must contain h'5a and the lower byte must contain the write data. this writes the values in bits 6 and 5 of the lower byte into the rste and rsts bits, but has no effect on the wovf bit.
414 h'a5 h'00 15 8 7 0 h'5a write data 15 8 7 0 writing 0 to wovf bit writing to rste and rsts bits address: h'ffbe address: h'ffbe figure 12-3 format of data written to rstcsr (example of wdt0) reading tcnt, tcsr, and rstcsr (example of wdt0): these registers are read in the same way as other registers. the read addresses are h'ff74 for tcsr, h'ff75 for tcnt, and h'ff77 for rstcsr.
415 12.3 operation 12.3.1 watchdog timer operation to use the wdt as a watchdog timer, set the wt/ it and tme bits in tcsr to 1. software must prevent tcnt overflows by rewriting the tcnt value (normally by writing h'00) before overflow occurs. this ensures that tcnt does not overflow while the system is operating normally. in this way, tcnt will not overflow while the system is operating normally, but if tcnt is not rewritten and overflows because of a system crash or other error, in the case of wdt0, if the rste bit in rstcsr is set to 1 beforehand, a signal is generated that effects an internal chip reset. either a power-on reset or a manual reset can be selected with the rsts bit in rstcsr. the internal reset signal is output for 518 states. this is illustrated in figure 12-4 (a). if a reset caused by an input signal from the res pin and a reset caused by wdt overflow occur simultaneously, the res pin reset has priority, and the wovf bit in rstcsr is cleared to 0. in the case of wdt1, the chip is reset, or an nmi interrupt request is generated, for 516 system clock periods (516? (515 or 516 clock periods when the clock source is ?ub (pss = 1)). this is illustrated in figure 12-4. an nmi interrupt request from the watchdog timer and an interrupt request from the nmi pin are handled via the same vector. simultaneous handling of a watchdog timer nmi interrupt request and an nmi pin interrupt request must therefore be avoided.
416 tcnt value h'00 time h'ff wt/it = 1 tme = 1 h'00 written to tcnt wt/it = 1 tme = 1 h'00 written to tcnt 518 states (wdt0) 515/516 states (wdt1) internal reset signal * 1 overflow internal reset generated wovf = 1 wt/it: timer mode select bit tme: timer enable bit note: 1. with wdt0, the internal reset signal is generated only when the rste bit is set to 1. with wdt1, an internal reset or nmi interrupt is generated. figure 12-4 operation in watchdog timer mode
417 12.3.2 interval timer operation to use the wdt as an interval timer, clear the wt/ it bit in tcsr to 0 and set the tme bit to 1. an interval timer interrupt (wovi) is generated each time tcnt overflows, provided that the wdt is operating as an interval timer, as shown in figure 12.5. this function can be used to generate interrupt requests at regular intervals. tcnt count h'00 time h'ff wt/it = 0 tme = 1 wovi overflow overflow overflow overflow legend: wovi: interval timer interrupt re q uest g eneration wovi wovi wovi figure 12.5 operation in interval timer mode
418 12.3.3 timing of setting of overflow flag (ovf) the ovf flag is set to 1 if tcnt overflows during interval timer operation. at the same time, an interval timer interrupt (wovi) is requested. this timing is shown in figure 12.6. if nmi request generation is selected in watchdog timer mode, when tcnt overflows the ovf bit in tcsr is set to 1 and at the same time an nmi interrupt is requested. ? ? ? tcnt h'ff h'00 overflow signal (internal signal) ovf figure 12.6 timing of ovf setting 12.3.4 timing of setting of watchdog timer overflow flag (wovf) with wdt0, the wovf bit in rstcsr is set to 1 if tcnt overflows in watchdog timer mode. if tcnt overflows while the rste bit in rstcsr is set to 1, an internal reset signal is generated for the entire chip. this timing is illustrated in figure 12-7.
419 tcnt h'ff h'00 overflow signal (internal signal) internal reset signal wovf 518 states (wdt0) 515/516 states (wdt1) figure 12-7 timing of wovf setting 12.4 interrupts during interval timer mode operation, an overflow generates an interval timer interrupt (wovi). the interval timer interrupt is requested whenever the ovf flag is set to 1 in tcsr. ovf must be cleared to 0 in the interrupt handling routine. when nmi interrupt request generation is selected in watchdog timer mode, an overflow generates an nmi interrupt request.
420 12.5 usage notes 12.5.1 contention between timer counter (tcnt) write and increment if a timer counter clock pulse is generated during the t2 state of a tcnt write cycle, the write takes priority and the timer counter is not incremented. figure 12.8 shows this operation. address internal write signal tcnt input clock tcnt nm t 1 t 2 tcnt write cycle counter write data figure 12.8 contention between tcnt write and increment 12.5.2 changing value of pss and cks2 to cks0 if bits pss and cks2 to cks0 in tcsr are written to while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before changing the value of bits pss and cks2 to cks0. 12.5.3 switching between watchdog timer mode and interval timer mode if the mode is switched from watchdog timer to interval timer, or vice versa, while the wdt is operating, errors could occur in the incrementation. software must stop the watchdog timer (by clearing the tme bit to 0) before switching the mode.
421 12.5.4 internal reset in watchdog timer mode if the rste bit is cleared to 0 in watchdog timer mode, the chip will not be reset internally if tcnt overflows, but tcnt0 and tcsr0 in wdt0 will be reset. tcnt, tcsr, and rstcr cannot be written to for a 132-state interval after overflow occurs, and a read of the wovf flag is not recognized during this time. it is therefore necessary to wait for 132 states after overflow occurs before writing 0 to the wovf flag to clear it.
422
423 section 13 serial communication interface (sci) 13.1 overview the h8s/2237 series and h8s/2227 series are equipped with mutually independent serial communication interface (sci) channels. the sci can handle both asynchronous and clocked synchronous serial communication. a function is also provided for serial communication between processors (multiprocessor communication function). 13.1.1 features sci features are listed below. ? on-chip channels h8s/2237 series: 4 on-chip channels (channels 0, 1, 2, 3) h8s/2227 series: 3 on-chip channels (channels 0, 1, 3) ? choice of asynchronous or clocked synchronous serial communication mode asynchronous mode ? serial data communication executed using asynchronous system in which synchronization is achieved character by character serial data communication can be carried out with standard asynchronous communication chips such as a universal asynchronous receiver/transmitter (uart) or asynchronous communication interface adapter (acia) ? a multiprocessor communication function is provided that enables serial data communication with a number of processors ? choice of 12 serial data transfer formats data length : 7 or 8 bits stop bit length : 1 or 2 bits parity : even, odd, or none multiprocessor bit : 1 or 0 ? receive error detection : parity, overrun, and framing errors ? break detection : break can be detected by reading the rxd pin level directly in case of a framing error clocked synchronous mode ? serial data communication synchronized with a clock serial data communication can be carried out with other chips that have a synchronous communication function
424 ? one serial data transfer format data length : 8 bits ? receive error detection : overrun errors detected ? full-duplex communication capability ? the transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously ? double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data ? choice of lsb-first or msb-first transfer ? can be selected regardless of the communication mode* (except in the case of asynchronous mode 7-bit data) note: * descriptions in this section refer to lsb-first transfer. ? on-chip baud rate generator allows any bit rate to be selected ? choice of serial clock source: internal clock from baud rate generator or external clock from sck pin ? four interrupt sources ? four interrupt sources ?transmit-data-empty, transmit-end, receive-data-full, and receive error ?that can issue requests independently ? the transmit-data-empty interrupt and receive data full interrupts can activate the data transfer controller (dtc) to execute data transfer ? module stop mode can be set ? as the initial setting, sci operation is halted. register access is enabled by exiting module stop mode.
425 13.1.2 block diagram figure 13-1 shows a block diagram of the sci. bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock external clock ?4 ?16 ?64 txi tei rxi eri smr legend rsr rdr tsr tdr smr scr ssr scmr brr : receive shift register : receive data register : transmit shift register : transmit data register : serial mode register : serial control register : serial status register :smart card mode register : bit rate register figure 13-1 block diagram of sci
426 13.1.3 pin configuration table 13-1 shows the serial pins for each sci channel. table 13-1 sci pins channel pin name symbol i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output 2 * serial clock pin 2 sck2 i/o sci2 clock input/output receive data pin 2 rxd2 input sci2 receive data input transmit data pin 2 txd2 output sci2 transmit data output 3 serial clock pin 3 sck3 i/o sci3 clock input/output receive data pin 3 rxd3 input sci3 receive data input transmit data pin 3 txd3 output sci3 transmit data output notes: pin names sck, rxd, and txd are used in the text for all channels, omitting the channel designation. * applies to the h8s/2237 series only.
427 13.1.4 register configuration the sci has the internal registers shown in table 13-2. these registers are used to specify asynchronous mode or clocked synchronous mode, the data format , and the bit rate, and to control transmitter/receiver. table 13-2 sci registers channel name abbreviation r/w initial value address * 1 0 serial mode register 0 smr0 r/w h'00 h'ff78 bit rate register 0 brr0 r/w h'ff h'ff79 serial control register 0 scr0 r/w h'00 h'ff7a transmit data register 0 tdr0 r/w h'ff h'ff7b serial status register 0 ssr0 r/(w) * 2 h'84 h'ff7c receive data register 0 rdr0 r h'00 h'ff7d smart card mode register 0 scmr0 r/w h'f2 h'ff7e 1 serial mode register 1 smr1 r/w h'00 h'ff80 bit rate register 1 brr1 r/w h'ff h'ff81 serial control register 1 scr1 r/w h'00 h'ff82 transmit data register 1 tdr1 r/w h'ff h'ff83 serial status register 1 ssr1 r/(w) * 2 h'84 h'ff84 receive data register 1 rdr1 r h'00 h'ff85 smart card mode register 1 scmr1 r/w h'f2 h'ff86 2 * 3 serial mode register 2 smr2 r/w h'00 h'ff88 bit rate register 2 brr2 r/w h'ff h'ff89 serial control register 2 scr2 r/w h'00 h'ff8a transmit data register 2 tdr2 r/w h'ff h'ff8b serial status register 2 ssr2 r/(w) * 2 h'84 h'ff8c receive data register 2 rdr2 r h'00 h'ff8d smart card mode register 2 scmr2 r/w h'f2 h'ff8e
428 table 13-2 sci registers (cont) channel name abbreviation r/w initial value address * 1 3 serial mode register 3 smr3 r/w h'00 h'fdd0 bit rate register 3 brr3 r/w h'ff h'fdd1 serial control register 3 scr3 r/w h'00 h'fdd2 transmit data register 3 tdr3 r/w h'ff h'fdd3 serial status register 3 ssr3 r/(w) * 2 h'84 h'fdd4 receive data register 3 rdr3 r h'00 h'fdd5 smart card mode register 3 scmr3 r/w h'f2 h'fdd6 all module stop control register b mstpcrb r/w h'ff h'fde9 module stop control register c mstpcrc r/w h'ff h'fdea notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing. 3. applies to the h8s/2237 series only.
429 13.2 register descriptions 13.2.1 receive shift register (rsr) 7 6 5 4 3 0 2 1 bit r/w : : rsr is a register used to receive serial data. the sci sets serial data input from the rxd pin in rsr in the order received, starting with the lsb (bit 0), and converts it to parallel data. when one byte of data has been received, it is transferred to rdr automatically. rsr cannot be directly read or written to by the cpu. 13.2.2 receive data register (rdr) 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : rdr is a register that stores received serial data. when the sci has received one byte of serial data, it transfers the received serial data from rsr to rdr where it is stored, and completes the receive operation. after this, rsr is receive-enabled. since rsr and rdr function as a double buffer in this way, enables continuous receive operations to be performed. rdr is a read-only register, and cannot be written to by the cpu. rdr is initialized to h'00 by a reset, in standby mode, watch mode, subactive mode, and subsleep mode or module stop mode.
430 13.2.3 transmit shift register (tsr) 7 6 5 4 3 0 2 1 bit r/w : : tsr is a register used to transmit serial data. to perform serial data transmission, the sci first transfers transmit data from tdr to tsr, then sends the data to the txd pin starting with the lsb (bit 0). when transmission of one byte is completed, the next transmit data is transferred from tdr to tsr, and transmission started, automatically. however, data transfer from tdr to tsr is not performed if the tdre bit in ssr is set to 1. tsr cannot be directly read or written to by the cpu. 13.2.4 transmit data register (tdr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : tdr is an 8-bit register that stores data for serial transmission. when the sci detects that tsr is empty, it transfers the transmit data written in tdr to tsr and starts serial transmission. continuous serial transmission can be carried out by writing the next transmit data to tdr during serial transmission of the data in tsr. tdr can be read or written to by the cpu at all times. tdr is initialized to h'ff by a reset, in standby mode, watch mode, subactive mode, and subsleep mode or module stop mode.
431 13.2.5 serial mode register (smr) 7 c/ a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/ e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value r/w : : : smr is an 8-bit register used to set the sci? serial transfer format and select the baud rate generator clock source. smr can be read or written to by the cpu at all times. smr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. bit 7?ommunication mode (c/ a ): selects asynchronous mode or clocked synchronous mode as the sci operating mode. bit 7 c/ a description 0 asynchronous mode (initial value) 1 clocked synchronous mode bit 6?haracter length (chr): selects 7 or 8 bits as the data length in asynchronous mode. in clocked synchronous mode, a fixed data length of 8 bits is used regardless of the chr setting. bit 6 chr description 0 8-bit data (initial value) 1 7-bit data * note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted, and it is not possible to choose between lsb-first or msb-first transfer.
432 bit 5?arity enable (pe): in asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. in clocked synchronous mode with a multiprocessor format, parity bit addition and checking is not performed, regardless of the pe bit setting. bit 5 pe description 0 parity bit addition and checking disabled (initial value) 1 parity bit addition and checking enabled * note: * when the pe bit is set to 1, the parity (even or odd) specified by the o/ e bit is added to transmit data before transmission. in reception, the parity bit is checked for the parity (even or odd) specified by the o/ e bit. bit 4?arity mode (o/ e ): selects either even or odd parity for use in parity addition and checking. the o/ e bit setting is only valid when the pe bit is set to 1, enabling parity bit addition and checking, in asynchronous mode. the o/ e bit setting is invalid in clocked synchronous mode, when parity addition and checking is disabled in asynchronous mode, and when a multiprocessor format is used. bit 4 o/ e description 0 even parity * 1 (initial value) 1 odd parity * 2 notes: 1. when even parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is even. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is even. 2. when odd parity is set, parity bit addition is performed in transmission so that the total number of 1 bits in the transmit character plus the parity bit is odd. in reception, a check is performed to see if the total number of 1 bits in the receive character plus the parity bit is odd.
433 bit 3?top bit length (stop): selects 1 or 2 bits as the stop bit length in asynchronous mode. the stop bits setting is only valid in asynchronous mode. if clocked synchronous mode is set the stop bit setting is invalid since stop bits are not added. bit 3 stop description 0 1 stop bit: in transmission, a single 1 bit (stop bit) is added to the end of a transmit character before it is sent. (initial value) 1 2 stop bits: in transmission, two 1 bits (stop bits) are added to the end of a transmit character before it is sent. in reception, only the first stop bit is checked, regardless of the stop bit setting. if the second stop bit is 1, it is treated as a stop bit; if it is 0, it is treated as the start bit of the next transmit character. bit 2?ultiprocessor mode (mp): selects multiprocessor format. when multiprocessor format is selected, the pe bit and o/ e bit parity settings are invalid. the mp bit setting is only valid in asynchronous mode; it is invalid in clocked synchronous mode. for details of the multiprocessor communication function, see section 13.3.3, multiprocessor communication function. bit 2 mp description 0 multiprocessor function disabled (initial value) 1 multiprocessor format selected
434 bits 1 and 0?lock select 1 and 0 (cks1, cks0): these bits select the clock source for the baud rate generator. the clock source can be selected from ? ?4, ?16, and ?64, according to the setting of bits cks1 and cks0. for the relation between the clock source, the bit rate register setting, and the baud rate, see section 13.2.8, bit rate register. bit 1 bit 0 cks1 cks0 description 0 0 clock (initial value) 1 ?4 clock 1 0 ?16 clock 1 ?64 clock 13.2.6 serial control register (scr) 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : scr is a register that performs enabling or disabling of sci transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. scr can be read or written to by the cpu at all times. scr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. bit 7?ransmit interrupt enable (tie): enables or disables transmit data empty interrupt (txi) request generation when serial transmit data is transferred from tdr to tsr and the tdre flag in ssr is set to 1. bit 7 tie description 0 transmit data empty interrupt (txi) requests disabled * (initial value) 1 transmit data empty interrupt (txi) requests enabled note: * txi interrupt request cancellation can be performed by reading 1 from the tdre flag, then clearing it to 0, or clearing the tie bit to 0.
435 bit 6?eceive interrupt enable (rie): enables or disables receive data full interrupt (rxi) request and receive error interrupt (eri) request generation when serial receive data is transferred from rsr to rdr and the rdrf flag in ssr is set to 1. bit 6 rie description 0 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled * (initial value) 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled note: * rxi and eri interrupt request cancellation can be performed by reading 1 from the rdrf flag, or the fer, per, or orer flag, then clearing the flag to 0, or clearing the rie bit to 0. bit 5?ransmit enable (te): enables or disables the start of serial transmission by the sci. bit 5 te description 0 transmission disabled * 1 (initial value) 1 transmission enabled * 2 notes: 1. the tdre flag in ssr is fixed at 1. 2. in this state, serial transmission is started when transmit data is written to tdr and the tdre flag in ssr is cleared to 0. smr setting must be performed to decide the transfer format before setting the te bit to 1. bit 4?eceive enable (re): enables or disables the start of serial reception by the sci. bit 4 re description 0 reception disabled * 1 (initial value) 1 reception enabled * 2 notes: 1. clearing the re bit to 0 does not affect the rdrf, fer, per, and orer flags, which retain their states. 2. serial reception is started in this state when a start bit is detected in asynchronous mode or serial clock input is detected in clocked synchronous mode. smr setting must be performed to decide the transfer format before setting the re bit to 1.
436 bit 3?ultiprocessor interrupt enable (mpie): enables or disables multiprocessor interrupts. the mpie bit setting is only valid in asynchronous mode when the mp bit in smr is set to 1. the mpie bit setting is invalid in clocked synchronous mode or when the mp bit is cleared to 0. bit 3 mpie description 0 multiprocessor interrupts disabled (normal reception performed) (initial value) [clearing conditions] ? when the mpie bit is cleared to 0 ? when mpb= 1 data is received 1 multiprocessor interrupts enabled * receive interrupt (rxi) requests, receive error interrupt (eri) requests, and setting of the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. note: * when receive data including mpb = 0 is received, receive data transfer from rsr to rdr, receive error detection, and setting of the rdrf, fer, and orer flags in ssr , is not performed. when receive data including mpb = 1 is received, the mpb bit in ssr is set to 1, the mpie bit is cleared to 0 automatically, and generation of rxi and eri interrupts (when the tie and rie bits in scr are set to 1) and fer and orer flag setting is enabled. bit 2?ransmit end interrupt enable (teie): enables or disables transmit end interrupt (tei) request generation when there is no valid transmit data in tdr in msb data transmission. bit 2 teie description 0 transmit end interrupt (tei) request disabled * (initial value) 1 transmit end interrupt (tei) request enabled * note: * tei cancellation can be performed by reading 1 from the tdre flag in ssr, then clearing it to 0 and clearing the tend flag to 0, or clearing the teie bit to 0.
437 bits 1 and 0?lock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. the combination of the cke1 and cke0 bits determines whether the sck pin functions as an i/o port, the serial clock output pin, or the serial clock input pin. the setting of the cke0 bit, however, is only valid for internal clock operation (cke1 = 0) in asynchronous mode. the cke0 bit setting is invalid in clocked synchronous mode, and in the case of external clock operation (cke1 = 1). note that the sci? operating mode must be decided using smr after setting the cke1 and cke0 bits. for details of clock source selection, see table 13.9 in section 13.3, operation. bit 1 bit 0 cke1 cke0 description 0 0 asynchronous mode internal clock/sck pin functions as i/o port * 1 clocked synchronous mode internal clock/sck pin functions as serial clock output 1 asynchronous mode internal clock/sck pin functions as clock output * 2 clocked synchronous mode internal clock/sck pin functions as serial clock output 1 0 asynchronous mode external clock/sck pin functions as clock input * 3 clocked synchronous mode external clock/sck pin functions as serial clock input 1 asynchronous mode external clock/sck pin functions as clock input * 3 clocked synchronous mode external clock/sck pin functions as serial clock input notes: 1. initial value 2. outputs a clock of the same frequency as the bit rate. 3. inputs a clock with a frequency 16 times the bit rate.
438 13.2.7 serial status register (ssr) 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : note: only 0 can be written, to clear the flag. ssr is an 8-bit register containing status flags that indicate the operating status of the sci, and multiprocessor bits. ssr can be read or written to by the cpu at all times. however, 1 cannot be written to flags tdre, rdrf, orer, per, and fer. also note that in order to clear these flags they must be read as 1 beforehand. the tend flag and mpb flag are read-only flags and cannot be modified. ssr is initialized to h'84 by a reset, in standby mode, watch mode, subactive mode, and subsleep mode or module stop mode. bit 7?ransmit data register empty (tdre): indicates that data has been transferred from tdr to tsr and the next serial data can be written to tdr. bit 7 tdre description 0 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] (initial value) ? when the te bit in scr is 0 ? when data is transferred from tdr to tsr and data can be written to tdr
439 bit 6?eceive data register full (rdrf): indicates that the received data is stored in rdr. bit 6 rdrf description 0 [clearing conditions] (initial value) ? when 0 is written to rdrf after reading rdrf = 1 ? when the dtc is activated by an rxi interrupt and reads data from rdr 1 [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr note: rdr and the rdrf flag are not affected and retain their previous values when an error is detected during reception or when the re bit in scr is cleared to 0. if reception of the next data is completed while the rdrf flag is still set to 1, an overrun error will occur and the receive data will be lost. bit 5?verrun error (orer): indicates that an overrun error occurred during reception, causing abnormal termination. bit 5 orer description 0 [clearing condition] (initial value) * 1 when 0 is written to orer after reading orer = 1 1 [setting condition] when the next serial reception is completed while rdrf = 1 notes: 1. the orer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. the receive data prior to the overrun error is retained in rdr, and the data received subsequently is lost. also, subsequent serial reception cannot be continued while the orer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either.
440 bit 4?raming error (fer): indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. bit 4 fer description 0 [clearing condition] (initial value) * 1 ? when 0 is written to fer after reading fer = 1 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 * 2 notes: 1. the fer flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. in 2-stop-bit mode, only the first stop bit is checked for a value of 0; the second stop bit is not checked. if a framing error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the fer flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either. bit 3?arity error (per): indicates that a parity error occurred during reception using parity addition in asynchronous mode, causing abnormal termination. bit 3 per description 0 [clearing condition] (initial value) * 1 when 0 is written to per after reading per = 1 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/ e bit in smr * 2 notes: 1. the per flag is not affected and retains its previous state when the re bit in scr is cleared to 0. 2. if a parity error occurs, the receive data is transferred to rdr but the rdrf flag is not set. also, subsequent serial reception cannot be continued while the per flag is set to 1. in clocked synchronous mode, serial transmission cannot be continued, either.
441 bit 2?ransmit end (tend): indicates that there is no valid data in tdr when the last bit of the transmit character is sent, and transmission has been ended. the tend flag is read-only and cannot be modified. bit 2 tend description 0 [clearing conditions] ? when 0 is written to tdre after reading tdre = 1 ? when the dtc is activated by a txi interrupt and writes data to tdr 1 [setting conditions] (initial value) ? when the te bit in scr is 0 ? when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character bit 1?ultiprocessor bit (mpb): when reception is performed using multiprocessor format in asynchronous mode, mpb stores the multiprocessor bit in the receive data. mpb is a read-only bit, and cannot be modified. bit 1 mpb description 0 [clearing condition] (initial value) * when data with a 0 multiprocessor bit is received 1 [setting condition] when data with a 1 multiprocessor bit is received note: * retains its previous state when the re bit in scr is cleared to 0 with multiprocessor format. bit 0?ultiprocessor bit transfer (mpbt): when transmission is performed using multiprocessor format in asynchronous mode, mpbt stores the multiprocessor bit to be added to the transmit data. the mpbt bit setting is invalid when multiprocessor format is not used, when not transmitting, and in clocked synchronous mode. bit 0 mpbt description 0 data with a 0 multiprocessor bit is transmitted (initial value) 1 data with a 1 multiprocessor bit is transmitted
442 13.2.8 bit rate register (brr) 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : brr is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits cks1 and cks0 in smr. brr can be read or written to by the cpu at all times. brr is initialized to h'ff by a reset and in hardware standby mode. it retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. as baud rate generator control is performed independently for each channel, different values can be set for each channel. table 13-3 shows sample brr settings in asynchronous mode, and table 13-4 shows sample brr settings in clocked synchronous mode.
443 table 13-3 brr settings for various bit rates (asynchronous mode) ?= 2 mhz ?= 2.097152 mhz ?= 2.4576 mhz ?= 3 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 1 141 0.03 1 148 ?.04 1 174 ?.26 1 212 0.03 150 1 103 0.16 1 108 0.21 1 127 0.00 1 155 0.16 300 0 207 0.16 0 217 0.21 0 255 0.00 1 77 0.16 600 0 103 0.16 0 108 0.21 0 127 0.00 0 155 0.16 1200 0 51 0.16 0 54 ?.70 0 63 0.00 0 77 0.16 2400 0 25 0.16 0 26 1.14 0 31 0.00 0 38 0.16 4800 0 12 0.16 0 13 ?.48 0 15 0.00 0 19 ?.34 9600 0 6 ?.48 0 7 0.00 0 9 ?.34 19200 0 3 0.00 0 4 ?.34 31250 0 1 0.00 0 2 0.00 38400 0 1 0.00 ?= 3.6864 mhz ?= 4 mhz ?= 4.9152 mhz ?= 5 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 ?.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.00 0 51 0.16 0 63 0.00 0 64 0.16 4800 0 23 0.00 0 25 0.16 0 31 0.00 0 32 ?.36 9600 0 11 0.00 0 12 0.16 0 15 0.00 0 15 1.73 19200 0 5 0.00 0 7 0.00 0 7 1.73 31250 0 3 0.00 0 4 ?.70 0 4 0.00 38400 0 2 0.00 0 3 0.00 0 3 1.73
444 table 13-3 brr settings for various bit rates (asynchronous mode) (cont) ?= 6 mhz ?= 6.144 mhz ?= 7.3728 mhz ?= 8 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 106 ?.44 2 108 0.08 2 130 ?.07 2 141 0.03 150 2 77 0.16 2 79 0.00 2 95 0.00 2 103 0.16 300 1 155 0.16 1 159 0.00 1 191 0.00 1 207 0.16 600 1 77 0.16 1 79 0.00 1 95 0.00 1 103 0.16 1200 0 155 0.16 0 159 0.00 0 191 0.00 0 207 0.16 2400 0 77 0.16 0 79 0.00 0 95 0.00 0 103 0.16 4800 0 38 0.16 0 39 0.00 0 47 0.00 0 51 0.16 9600 0 19 ?.34 0 19 0.00 0 23 0.00 0 25 0.16 19200 0 9 ?.34 0 9 0.00 0 11 0.00 0 12 0.16 31250 0 5 0.00 0 5 2.40 0 7 0.00 38400 0 4 ?.34 0 4 0.00 0 5 0.00 ?= 9.8304 mhz ?= 10 mhz ?= 12 mhz ?= 12.288 mhz bit rate (bit/s) n n error (%) n n error (%) n n error (%) n n error (%) 110 2 174 ?.26 2 177 ?.25 2 212 0.03 2 217 0.08 150 2 127 0.00 2 129 0.16 2 155 0.16 2 159 0.00 300 1 255 0.00 2 64 0.16 2 77 0.16 2 79 0.00 600 1 127 0.00 1 129 0.16 1 155 0.16 1 159 0.00 1200 0 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 2400 0 127 0.00 0 129 0.16 0 155 0.16 0 159 0.00 4800 0 63 0.00 0 64 0.16 0 77 0.16 0 79 0.00 9600 0 31 0.00 0 32 ?.36 0 38 0.16 0 39 0.00 19200 0 15 0.00 0 15 1.73 0 19 ?.34 0 19 0.00 31250 0 9 ?.70 0 9 0.00 0 11 0.00 0 11 2.40 38400 0 7 0.00 0 7 1.73 0 9 ?.34 0 9 0.00
445 table 13-4 brr settings for various bit rates (clocked synchronous mode) bit rate ?= 2 mhz ?= 4 mhz ?= 6 mhz ?= 8 mhz ?= 10 mhz (bit/s) n n n n n n n n n n 110 3 70 250 2 124 2 249 3 124 500 1 249 2 124 2 249 1 k 1 124 1 249 2 124 2.5 k 0 199 1 99 1 149 1 199 1 249 5 k 0 99 0 199 1 74 1 99 1 124 10 k 0 49 0 99 0 149 0 199 0 249 25 k 0 19 0 39 0 59 0 79 0 99 50 k 09019029039049 100 k 0409014019024 250 k 0103050709 500 k 0 0 * 01020304 1 m 0 0 * 01 2.5 m 00 * 5 m note: as far as possible, the setting should be made so that the error is no more than 1%. legend blank : cannot be set. : can be set, but there will be a degree of error. * : continuous transfer is not possible.
446 the brr setting is found from the following formulas. asynchronous mode: n = 64 2 2n? b 10 6 ?1 clocked synchronous mode: n = 8 2 2n? b 10 6 ?1 where b: bit rate (bit/s) n: brr setting for baud rate generator (0 n 255) ? operating frequency (mhz) n: baud rate generator input clock (n = 0 to 3) (see the table below for the relation between n and the clock.) smr setting n clock cks1 cks0 0 0 0 1 ?4 0 1 2 ?16 1 0 3 ?64 1 1 the bit rate error in asynchronous mode is found from the following formula: error (%) = { ? ? 10 6 (n + 1) b 64 2 2n? ?1 } 100
447 table 13-5 shows the maximum bit rate for each frequency in asynchronous mode. tables 13-6 and 13-7 show the maximum bit rates with external clock input. table 13-5 maximum bit rate for each frequency (asynchronous mode) ?(mhz) maximum bit rate (bit/s) n n 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.3728 230400 0 0 8 250000 0 0 9.8304 307200 0 0 10 312500 0 0 12 375000 0 0 12.288 384000 0 0
448 table 13-6 maximum bit rate with external clock input (asynchronous mode) ?(mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.0720 192000 table 13-7 maximum bit rate with external clock input (clocked synchronous mode) ?(mhz) external input clock (mhz) maximum bit rate (bit/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0
449 13.2.9 smart card mode register (scmr) 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 bit initial value r/w : : : scmr selects lsb-first or msb-first by means of bit sdir. except in the case of asynchronous mode 7-bit data, lsb-first or msb-first can be selected regardless of the serial communication mode. the descriptions in this chapter refer to lsb-first transfer. for details of the other bits in scmr, see 14.2.1, smart card mode register (scmr). scmr is initialized to h'00 by a reset and in hardware standby mode. it retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. bits 7 to 4?eserved: read-only bits, always read as 1. bit 3?mart card data transfer direction (sdir): selects the serial/parallel conversion format. this bit is valid when 8-bit data is used as the transmit/receive format. bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first
450 bit 2?mart card data invert (sinv): specifies inversion of the data logic level. the sinv bit does not affect the logic level of the parity bit(s): parity bit inversion requires inversion of the o/ e bit in smr. bit 2 sinv description 0 tdr contents are transmitted without modification (initial value) receive data is stored in rdr without modification 1 tdr contents are inverted before being transmitted receive data is stored in rdr in inverted form bit 1?eserved: read-only bit, always read as 1. bit 0?mart card interface mode select (smif): when the smart card interface operates as a normal sci, 0 should be written in this bit. 13.2.10 module stop control registers b and c (mstpcrb, mstpcrc) 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 0 mstpb0 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w bit initial value r/w : : : mstpcrb 7 mstpc7 1 r/w 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 0 mstpc0 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w bit initial value r/w : : : mstpcrc mstpcrb and mstpcrc are 8-bit readable/writable registers that perform module stop mode control. when one of bits mstpb7 to mstpb5 or mstpc7 is set to 1, sci0, sci1, sci2, or sci3, respectively, stops operation at the end of the bus cycle, and enters module stop mode. for details, see section 20.5, module stop mode. mstpcrb and mstpcrc are each initialized to h'ff by a reset and in hardware standby mode. they are not initialized in software standby mode.
451 module stop control register b (mstpcrb) bit 7?odule stop (mstpb7): specifies the sci0 module stop mode. bit 7 mstpb7 description 0 sci0 module stop mode is cleared 1 sci0 module stop mode is set (initial value) bit 6?odule stop (mstpb6): specifies the sci1 module stop mode. bit 6 mstpb6 description 0 sci1 module stop mode is cleared 1 sci1 module stop mode is set (initial value) bit 5 (h8s/2237 series)?odule stop (mstpb5): specifies the sci2 module stop mode. bit 5 mstpb5 description 0 sci2 module stop mode is cleared 1 sci2 module stop mode is set (initial value) bit 5 (h8s/2227 series)?eserved: this bit cannot be modified and is always read as 1. module stop control register c (mstpcrc) bit 7?odule stop (mstpc7): specifies the sci3 module stop mode. bit 7 mstpc7 description 0 sci3 module stop mode is cleared 1 sci3 module stop mode is set (initial value)
452 13.3 operation 13.3.1 overview the sci can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and clocked synchronous mode in which synchronization is achieved with clock pulses. selection of asynchronous or clocked synchronous mode and the transmission format is made using smr as shown in table 13-8. the sci clock is determined by a combination of the c/ a bit in smr and the cke1 and cke0 bits in scr, as shown in table 13-9. asynchronous mode ? data length: choice of 7 or 8 bits ? choice of parity addition, multiprocessor bit addition, and addition of 1 or 2 stop bits (the combination of these parameters determines the transfer format and character length) ? detection of framing, parity, and overrun errors, and breaks, during reception ? choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a clock with the same frequency as the bit rate can be output ? when external clock is selected: a clock with a frequency of 16 times the bit rate must be input (the on-chip baud rate generator is not used) clocked synchronous mode ? transfer format: fixed 8-bit data ? detection of overrun errors during reception ? choice of internal or external clock as sci clock source ? when internal clock is selected: the sci operates on the baud rate generator clock and a serial clock is output off-chip ? when external clock is selected: the on-chip baud rate generator is not used, and the sci operates on the input serial clock
453 table 13-8 smr settings and serial transfer format selection smr settings sci transfer format bit 7 bit 6 bit 2 bit 5 bit 3 data parity stop bit c/ a chr mp pe stop mode length bit length 00000 asynchronous 8-bit data no no 1 bit 1 mode 2 bits 1 0 yes 1 bit 1 2 bits 1 0 0 7-bit data no 1 bit 1 2 bits 1 0 yes 1 bit 1 2 bits 0 1 0 8-bit data yes no 1 bit 1 2 bits 1 0 7-bit data 1 bit 1 2 bits 1 clocked synchronous mode 8-bit data no none table 13-9 smr and scr settings and sci clock source selection smr scr setting sci transmit/receive clock bit 7 bit 1 bit 0 clock c/ a cke1 cke0 mode source sck pin function 0 0 0 asynchronous internal sci does not use sck pin 1 mode outputs clock with same frequency as bit rate 1 0 external inputs clock with frequency of 16 times 1 the bit rate 1 0 0 internal outputs serial clock 1 1 0 external inputs serial clock 1 multi processor bit asynchronous mode (multi- processor format) clocked synchronous mode
454 13.3.2 operation in asynchronous mode in asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and stop bits indicating the end of communication. serial communication is thus carried out with synchronization established on a character-by-character basis. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 13-2 shows the general format for asynchronous serial communication. in asynchronous serial communication, the transmission line is usually held in the mark state (high level). the sci monitors the transmission line, and when it goes to the space state (low level), recognizes a start bit and starts serial communication. one serial communication character consists of a start bit (low level), followed by data (in lsb- first order), a parity bit (high or low level), and finally stop bits (high level). in asynchronous mode, the sci performs synchronization at the falling edge of the start bit in reception. the sci samples the data on the 8th pulse of a clock with a frequency of 16 times the length of one bit, so that the transfer data is latched at the center of each bit. lsb start bit msb idle state (mark state) stop bit 0 transmit/receive data d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 1 1 serial data parity bit 1 bit 1 or 2 bits 7 or 8 bits 1 bit, or none one unit of transfer data (character or frame) figure 13-2 data format in asynchronous communication (example with 8-bit data, parity, two stop bits)
455 data transfer format: table 13-10 shows the data transfer formats that can be used in asynchronous mode. any of 12 transfer formats can be selected according to the smr setting. table 13-10 serial transfer formats (asynchronous mode) pe 0 0 1 1 0 0 1 1 s 8-bit data stop s 7-bit data stop s 8-bit data stop stop s 8-bit data p stop s 7-bit data stop p s 8-bit data mpb stop s 8-bit data mpb stop stop s 7-bit data stop mpb s 7-bit data stop mpb stop s 7-bit data stop stop chr 0 0 0 0 1 1 1 1 0 0 1 1 mp 0 0 0 0 0 0 0 0 1 1 1 1 stop 0 1 0 1 0 1 0 1 0 1 0 1 smr settings 123456789101112 serial transfer format and frame length stop s 8-bit data p stop s 7-bit data stop p stop legend s : start bit stop : stop bit p : parity bit mpb : multiprocessor bit
456 clock: either an internal clock generated by the on-chip baud rate generator or an external clock input at the sck pin can be selected as the sci? serial clock, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. for details of sci clock source selection, see table 13-9. when an external clock is input at the sck pin, the clock frequency should be 16 times the bit rate used. when the sci is operated on an internal clock, the clock can be output from the sck pin. the frequency of the clock output in this case is equal to the bit rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as shown in figure 13-3. 0 1 frame d0 d1 d2 d3 d4 d5 d6 d7 0/1 1 1 figure 13-3 relation between output clock and transfer data phase (asynchronous mode) data transfer operations: ? sci initialization (asynchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. when an external clock is used the clock should not be stopped during operation, including initialization, since operation is uncertain.
457 figure 13-4 shows a sample sci initialization flowchart. wait start initialization set data transfer format in smr and scmr [1] set cke1 and cke0 bits in scr (te, re bits 0) no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie, teie, and mpie bits [4] 1-bit interval elapsed? [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, and bits te and re, to 0. when the clock is selected in asynchronous mode, it is output immediately after scr settings are made. [2] set the data transfer format in smr and scmr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie, teie, and mpie bits. setting the te and re bits enables the txd and rxd pins to be used. figure 13-4 sample sci initialization flowchart
458 ? serial data transmission (asynchronous mode) figure 13-5 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 and set ddr to 1 clear te bit in scr to 0 tdre=1 all data transmitted? tend= 1 break output? [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, a frame of 1s is output, and transmission is enabled. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request, and date is written to tdr. [4] break output at the end of serial transmission: to output a break in serial transmission, set ddr for the port corresponding to the txd pin to 1, clear dr to 0, then clear the te bit in scr to 0. figure 13-5 sample serial transmission flowchart
459 in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. [a] start bit: one 0-bit is output. [b] transmit data: 8-bit or 7-bit data is output in lsb-first order. [c] parity bit or multiprocessor bit: one parity bit (even or odd parity), or one multiprocessor bit is output. a format in which neither a parity bit nor a multiprocessor bit is output can also be selected. [d] stop bit(s): one or two 1-bits (stop bits) are output. [e] mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, the data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the ?ark state?is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated.
460 figure 13-6 shows an example of the operation for transmission in asynchronous mode. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit parity bit stop bit start bit data parity bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 13-6 example of operation in transmission in asynchronous mode (example with 8-bit data, parity, one stop bit)
461 ? serial data reception (asynchronous mode) figure 13-7 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 read orer, per, and fer flags in ssr error processing (continued on next page) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes per fer orer= 1 rdrf= 1 all data received? sci initialization: the rxd pin is automatically designated as the receive data input pin. receive error processing and break detection: if a receive error occurs, read the orer, per, and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer, per, and fer flags are all cleared to 0. reception cannot be resumed if any of these flags are set to 1. in the case of a framing error, a break can be detected by reading the value of the input port corresponding to the rxd pin. sci status check and receive data read : read ssr and check that rdrf = 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial reception continuation procedure: to continue serial reception, before the stop bit for the current frame is received, read the rdrf flag, read rdr, and clear the rdrf flag to 0. the rdrf flag is cleared automatically when dtc is activated by an rxi interrupt and the rdr value is read. [1] [2] [3] [4] [5] figure 13-7 sample serial reception data flowchart
462 [3] error processing parity error processing no yes clear orer, per, and fer flags in ssr to 0 no yes no yes framing error processing no yes overrun error processing orer= 1 fer= 1 break? per= 1 clear re bit in scr to 0 figure 13-7 sample serial reception data flowchart (cont)
463 in serial reception, the sci operates as described below. [1] the sci monitors the transmission line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] the received data is stored in rsr in lsb-to-msb order. [3] the parity bit and stop bit are received. after receiving these bits, the sci carries out the following checks. [a] parity check: the sci checks whether the number of 1 bits in the receive data agrees with the parity (even or odd) set in the o/ e bit in smr. [b] stop bit check: the sci checks whether the stop bit is 1. if there are two stop bits, only the first is checked. [c] status check: the sci checks whether the rdrf flag is 0, indicating that the receive data can be transferred from rsr to rdr. if all the above checks are passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error* is detected in the error check, the operation is as shown in table 13-11. note: * subsequent receive operations cannot be performed when a receive error has occurred. also note that the rdrf flag is not set to 1 in reception, and so the error flags must be cleared to 0. [4] if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive data full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer, per, or fer flag changes to 1, a receive error interrupt (eri) request is generated.
464 table 13-11 receive errors and conditions for occurrence receive error abbreviation occurrence condition data transfer overrun error orer when the next data reception is completed while the rdrf flag in ssr is set to 1 receive data is not transferred from rsr to rdr. framing error fer when the stop bit is 0 receive data is transferred from rsr to rdr. parity error per when the received data differs from the parity (even or odd) set in smr receive data is transferred from rsr to rdr. figure 13-8 shows an example of the operation for reception in asynchronous mode. rdrf fer 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 0 1 1 data start bit parity bit stop bit start bit data parity bit stop bit rxi interrupt request generated eri interrupt request generated by framing error idle state (mark state) rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine figure 13-8 example of sci operation in reception (example with 8-bit data, parity, one stop bit)
465 13.3.3 multiprocessor communication function the multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. use of this function enables data transfer to be performed among a number of processors sharing transmission lines. when multiprocessor communication is carried out, each receiving station is addressed by a unique id code. the serial communication cycle consists of two component cycles: an id transmission cycle which specifies the receiving station , and a data transmission cycle. the multiprocessor bit is used to differentiate between the id transmission cycle and the data transmission cycle. the transmitting station first sends the id of the receiving station with which it wants to perform serial communication as data with a 1 multiprocessor bit added. it then sends transmit data as data with a 0 multiprocessor bit added. the receiving station skips the data until data with a 1 multiprocessor bit is sent. when data with a 1 multiprocessor bit is received, the receiving station compares that data with its own id. the station whose id matches then receives the data sent next. stations whose id does not match continue to skip the data until data with a 1 multiprocessor bit is again received. in this way, data communication is carried out among a number of processors. figure 13-9 shows an example of inter-processor communication using the multiprocessor format. data transfer format: there are four data transfer formats. when the multiprocessor format is specified, the parity bit specification is invalid. for details, see table 13-10. clock: see the section on asynchronous mode.
466 transmitting station receiving station a (id= 01) receiving station b (id= 02) receiving station c (id= 03) receiving station d (id= 04) serial transmission line serial data id transmission cycle= receiving station specification data transmission cycle= data transmission to receiving station specified by id (mpb= 1) (mpb= 0) h'01 h'aa legend mpb: multiprocessor bit figure 13-9 example of inter-processor communication using multiprocessor format (transmission of data h'aa to receiving station a) data transfer operations: ? multiprocessor serial data transmission figure 13-10 shows a sample flowchart for multiprocessor serial data transmission. the following procedure should be used for multiprocessor serial data transmission.
467 no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and set mpbt bit in ssr no yes no yes read tend flag in ssr [3] no yes [4] clear dr to 0 and set ddr to 1 clear te bit in scr to 0 tdre= 1 all data transmitted? tend= 1 break output? clear tdre flag to 0 sci initialization: the txd pin is automatically designated as the transmit data output pin. after the te bit is set to 1, a frame of 1s is output, and transmission is enabled. sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr. set the mpbt bit in ssr to 0 or 1. finally, clear the tdre flag to 0. serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request, and data is written to tdr. break output at the end of serial transmission: to output a break in serial transmission, set the port ddr to 1, clear dr to 0, then clear the te bit in scr to 0. [1] [2] [3] [4] figure 13-10 sample multiprocessor serial transmission flowchart
468 in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty interrupt (txi) is generated. the serial transmit data is sent from the txd pin in the following order. [a] start bit: one 0-bit is output. [b] transmit data: 8-bit or 7-bit data is output in lsb-first order. [c] multiprocessor bit one multiprocessor bit (mpbt value) is output. [d] stop bit(s): one or two 1-bits (stop bits) are output. [e] mark state: 1 is output continuously until the start bit that starts the next transmission is sent. [3] the sci checks the tdre flag at the timing for sending the stop bit. if the tdre flag is cleared to 0, data is transferred from tdr to tsr, the stop bit is sent, and then serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the stop bit is sent, and then the mark state is entered in which 1 is output continuously. if the teie bit in scr is set to 1 at this time, a transmission end interrupt (tei) request is generated.
469 figure 13-11 shows an example of sci operation for transmission using the multiprocessor format. tdre tend 0 1 frame d0 d1 d7 0/1 1 0 d0 d1 d7 0/1 1 1 1 data start bit multi- proce- ssor bit stop bit start bit data multi- proces- sor bit stop bit txi interrupt request generated data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated idle state (mark state) txi interrupt request generated figure 13-11 example of sci operation in transmission (example with 8-bit data, multiprocessor bit, one stop bit) ? multiprocessor serial data reception figure 13-12 shows a sample flowchart for multiprocessor serial reception. the following procedure should be used for multiprocessor serial data reception.
470 yes [1] no initialization start reception no yes [4] clear re bit in scr to 0 error processing (continued on next page) [5] no yes fer orer= 1 rdrf= 1 all data received? read mpie bit in scr [2] read orer and fer flags in ssr read rdrf flag in ssr [3] read receive data in rdr no yes this station? id? read orer and fer flags in ssr yes no read rdrf flag in ssr no yes fer orer= 1 read receive data in rdr rdrf= 1 sci initialization: the rxd pin is automatically designated as the receive data input pin. id reception cycle: set the mpie bit in scr to 1. sci status check, id reception and comparison: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and compare it with this station? id. if the data is not this station? id, set the mpie bit to 1 again, and clear the rdrf flag to 0. if the data is this station? id, clear the rdrf flag to 0. sci status check and data reception: read ssr and check that the rdrf flag is set to 1, then read the data in rdr. receive error processing and break detection: if a receive error occurs, read the orer and fer flags in ssr to identify the error. after performing the appropriate error processing, ensure that the orer and fer flags are all cleared to 0. reception cannot be resumed if either of these flags is set to 1. in the case of a framing error, a break can be detected by reading the rxd pin value. [1] [2] [3] [4] [5] figure 13-12 sample multiprocessor serial reception flowchart
471 error processing yes no clear orer, per, and fer flags in ssr to 0 no yes no yes framing error processing overrun error processing orer= 1 fer= 1 break? clear re bit in scr to 0 [5] figure 13-12 sample multiprocessor serial reception flowchart (cont)
472 figure 13-13 shows an example of sci operation for multiprocessor format reception. mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id1) start bit mpb stop bit start bit data (data1) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine if not this station? id, mpie bit is set to 1 again rxi interrupt request is not generated, and rdr retains its state id1 (a) data does not match station? id mpie rdr value 0 d0 d1 d7 1 1 0 d0 d1 d7 0 1 1 1 data (id2) start bit mpb stop bit start bit data (data2) mpb stop bit rxi interrupt request (multiprocessor interrupt) generated mpie = 0 idle state (mark state) rdrf rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine matches this station? id, so reception continues, and data is received in rxi interrupt service routine mpie bit set to 1 again id2 (b) data matches station? id data2 id1 figure 13-13 example of sci operation in reception (example with 8-bit data, multiprocessor bit, one stop bit)
473 13.3.4 operation in clocked synchronous mode in clocked synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. inside the sci, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock. both the transmitter and the receiver also have a double-buffered structure, so that data can be read or written during transmission or reception, enabling continuous data transfer. figure 13-14 shows the general format for clocked synchronous serial communication. don? care don? care one unit of transfer data (character or frame) bit 0 serial data serial clock bit 1 bit 3 bit 4 bit 5 lsb msb bit 2 bit 6 bit 7 * note: * high except in continuous transfer * figure 13-14 data format in synchronous communication in clocked synchronous serial communication, data on the transmission line is output from one falling edge of the serial clock to the next. data confirmation is guaranteed at the rising edge of the serial clock. in clocked serial communication, one character consists of data output starting with the lsb and ending with the msb. after the msb is output, the transmission line holds the msb state. in clocked synchronous mode, the sci receives data in synchronization with the rising edge of the serial clock. data transfer format: a fixed 8-bit data format is used. no parity or multiprocessor bits are added. clock: either an internal clock generated by the on-chip baud rate generator or an external serial clock input at the sck pin can be selected, according to the setting of the c/ a bit in smr and the cke1 and cke0 bits in scr. for details of sci clock source selection, see table 13-9. when the sci is operated on an internal clock, the serial clock is output from the sck pin.
474 eight serial clock pulses are output in the transfer of one character, and when no transfer is performed the clock is fixed high. when only receive operations are performed, however, the serial clock is output until an overrun error occurs or the re bit is cleared to 0. if you want to perform receive operations in units of one character, you should select an external clock as the clock source. data transfer operations: ? sci initialization (clocked synchronous mode) before transmitting and receiving data, you should first clear the te and re bits in scr to 0, then initialize the sci as described below. when the operating mode, transfer format, etc., is changed, the te and re bits must be cleared to 0 before making the change using the following procedure. when the te bit is cleared to 0, the tdre flag is set to 1 and tsr is initialized. note that clearing the re bit to 0 does not change the contents of the rdrf, per, fer, and orer flags, or the contents of rdr. figure 13-15 shows a sample sci initialization flowchart. wait note: in simultaneous transmit and receive operations, the te and re bits should both be cleared to 0 or set to 1 simultaneously. start initialization set data transfer format in smr and scmr no yes set value in brr clear te and re bits in scr to 0 [2] [3] set te and re bits in scr to 1, and set rie, tie, teie, and mpie bits [4] 1-bit interval elapsed? [1] [1] set the clock selection in scr. be sure to clear bits rie, tie, teie, and mpie, te and re, to 0. [2] set the data transfer format in smr and scmr. [3] write a value corresponding to the bit rate to brr. not necessary if an external clock is used. [4] wait at least one bit interval, then set the te bit or re bit in scr to 1. also set the rie, tie, teie, and mpie bits. setting the te and re bits enables the txd and rxd pins to be used. set cke1 and cke0 bits in scr (te, re bits 0) figure 13-15 sample sci initialization flowchart
475 ? serial data transmission (clocked synchronous mode) figure 13-16 shows a sample flowchart for serial transmission. the following procedure should be used for serial data transmission. no [1] yes initialization start transmission read tdre flag in ssr [2] write transmit data to tdr and clear tdre flag in ssr to 0 no yes no yes read tend flag in ssr [3] clear te bit in scr to 0 tdre= 1 all data transmitted? tend= 1 [1] sci initialization: the txd pin is automatically designated as the transmit data output pin. [2] sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. [3] serial transmission continuation procedure: to continue serial transmission, be sure to read 1 from the tdre flag to confirm that writing is possible, then write data to tdr, and then clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request and data is written to tdr. figure 13-16 sample serial transmission flowchart
476 in serial transmission, the sci operates as described below. [1] the sci monitors the tdre flag in ssr, and if is 0, recognizes that data has been written to tdr, and transfers the data from tdr to tsr. [2] after transferring data from tdr to tsr, the sci sets the tdre flag to 1 and starts transmission. if the tie bit in scr is set to 1 at this time, a transmit data empty interrupt (txi) is generated. when clock output mode has been set, the sci outputs 8 serial clock pulses. when use of an external clock has been specified, data is output synchronized with the input clock. the serial transmit data is sent from the txd pin starting with the lsb (bit 0) and ending with the msb (bit 7). [3] the sci checks the tdre flag at the timing for sending the msb (bit 7). if the tdre flag is cleared to 0, data is transferred from tdr to tsr, and serial transmission of the next frame is started. if the tdre flag is set to 1, the tend flag in ssr is set to 1, the msb (bit 7) is sent, and the txd pin maintains its state. if the teie bit in scr is set to 1 at this time, a tei interrupt request is generated. [4] after completion of serial transmission, the sck pin is fixed. figure 13-17 shows an example of sci operation in transmission. transfer direction bit 0 serial data serial clock 1 frame tdre tend bit 1 bit 7 bit 0 bit 1 bit 7 bit 6 data written to tdr and tdre flag cleared to 0 in txi interrupt service routine tei interrupt request generated txi interrupt request generated txi interrupt request generated figure 13-17 example of sci operation in transmission
477 ? serial data reception (clocked synchronous mode) figure 13-18 shows a sample flowchart for serial reception. the following procedure should be used for serial data reception. when changing the operating mode from asynchronous to clocked synchronous, be sure to check that the orer, per, and fer flags are all cleared to 0. the rdrf flag will not be set if the fer or per flag is set to 1, and neither transmit nor receive operations will be possible.
478 yes [1] no initialization start reception [2] no yes read rdrf flag in ssr [4] [5] clear re bit in scr to 0 error processing (continued below) [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer= 1 rdrf= 1 all data received? read orer flag in ssr [1] [2] [3] [4] [5] sci initialization: the rxd pin is automatically designated as the receive data input pin. receive error processing: if a receive error occurs, read the orer flag in ssr , and after performing the appropriate error processing, clear the orer flag to 0. transfer cannot be resumed if the orer flag is set to 1. sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial reception continuation procedure: to continue serial reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0. the rdrf flag is cleared automatically when the dtc is activated by a receive data full interrupt (rxi) request and the rdr value is read. error processing overrun error processing [3] clear orer flag in ssr to 0 figure 13-18 sample serial reception flowchart
479 in serial reception, the sci operates as described below. [1] the sci performs internal initialization in synchronization with serial clock input or output. [2] the received data is stored in rsr in lsb-to-msb order. after reception, the sci checks whether the rdrf flag is 0 and the receive data can be transferred from rsr to rdr. if this check is passed, the rdrf flag is set to 1, and the receive data is stored in rdr. if a receive error is detected in the error check, the operation is as shown in table 13-11. neither transmit nor receive operations can be performed subsequently when a receive error has been found in the error check. [3] if the rie bit in scr is set to 1 when the rdrf flag changes to 1, a receive data full interrupt (rxi) request is generated. also, if the rie bit in scr is set to 1 when the orer flag changes to 1, a receive error interrupt (eri) request is generated. figure 13-19 shows an example of sci operation in reception. bit 7 serial data serial clock 1 frame rdrf orer bit 0 bit 7 bit 0 bit 1 bit 6 bit 7 rxi interrupt request generated rdr data read and rdrf flag cleared to 0 in rxi interrupt service routine rxi interrupt request generated eri interrupt request generated by overrun error figure 13-19 example of sci operation in reception ? simultaneous serial data transmission and reception (clocked synchronous mode) figure 13-20 shows a sample flowchart for simultaneous serial transmit and receive operations. the following procedure should be used for simultaneous serial data transmit and receive operations.
480 yes [1] no initialization start transmission/reception [5] error processing [3] read receive data in rdr, and clear rdrf flag in ssr to 0 no yes orer= 1 all data received? [2] read tdre flag in ssr no yes tdre= 1 write transmit data to tdr and clear tdre flag in ssr to 0 no yes rdrf= 1 read orer flag in ssr [4] read rdrf flag in ssr clear te and re bits in scr to 0 note: when switching from transmit or receive operation to simultaneous transmit and receive operations, first clear the te bit and re bit to 0, then set both these bits to 1 simultaneously. [1] [2] [3] [4] [5] sci initialization: the txd pin is designated as the transmit data output pin, and the rxd pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. sci status check and transmit data write: read ssr and check that the tdre flag is set to 1, then write transmit data to tdr and clear the tdre flag to 0. transition of the tdre flag from 0 to 1 can also be identified by a txi interrupt. receive error processing: if a receive error occurs, read the orer flag in ssr , and after performing the appropriate error processing, clear the orer flag to 0. transmission/reception cannot be resumed if the orer flag is set to 1. sci status check and receive data read: read ssr and check that the rdrf flag is set to 1, then read the receive data in rdr and clear the rdrf flag to 0. transition of the rdrf flag from 0 to 1 can also be identified by an rxi interrupt. serial transmission/reception continuation procedure: to continue serial transmission/ reception, before the msb (bit 7) of the current frame is received, finish reading the rdrf flag, reading rdr, and clearing the rdrf flag to 0. also, before the msb (bit 7) of the current frame is transmitted, read 1 from the tdre flag to confirm that writing is possible. then write data to tdr and clear the tdre flag to 0. checking and clearing of the tdre flag is automatic when the dtc is activated by a transmit data empty interrupt (txi) request and data is written to tdr. also, the rdrf flag is cleared automatically when the dtc is activated by a receive data full interrupt (rxi) request and the rdr value is read. figure 13-20 sample flowchart of simultaneous serial transmit and receive operations
481 13.4 sci interrupts the sci has four interrupt sources: the transmit-end interrupt (tei) request, receive-error interrupt (eri) request, receive-data-full interrupt (rxi) request, and transmit-data-empty interrupt (txi) request. table 13-12 shows the interrupt sources and their relative priorities. individual interrupt sources can be enabled or disabled with the tie, rie, and teie bits in the scr. each kind of interrupt request is sent to the interrupt controller independently. when the tdre flag in ssr is set to 1, a txi interrupt request is generated. when the tend flag in ssr is set to 1, a tei interrupt request is generated. a txi interrupt can activate the dtc to perform data transfer. the tdre flag is cleared to 0 automatically when data transfer is performed by the dtc. the dtc cannot be activated by a tei interrupt request. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when the orer, per, or fer flag in ssr is set to 1, an eri interrupt request is generated. an rxi interrupt can activate the dtc to perform data transfer. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dtc. the dtc cannot be activated by an eri interrupt request.
482 table 13-12 sci interrupt sources channel interrupt source description dtc activation priority * 1 0 eri interrupt due to receive error (orer, fer, or per) not possible high rxi interrupt due to receive data full state (rdrf) possible txi interrupt due to transmit data empty state (tdre) possible tei interrupt due to transmission end (tend) not possible 1 eri interrupt due to receive error (orer, fer, or per) not possible rxi interrupt due to receive data full state (rdrf) possible txi interrupt due to transmit data empty state (tdre) possible tei interrupt due to transmission end (tend) not possible 2 * 2 eri interrupt due to receive error (orer, fer, or per) not possible rxi interrupt due to receive data full state (rdrf) possible txi interrupt due to transmit data empty state (tdre) possible tei interrupt due to transmission end (tend) not possible 3 eri interrupt due to receive error (orer, fer, or per) not possible rxi interrupt due to receive data full state (rdrf) possible txi interrupt due to transmit data empty state (tdre) possible tei interrupt due to transmittion end (tend) not possible low notes: 1. this table shows the initial state immediately after a reset. relative priorities among channels can be changed by means of the interrupt controller. 2. applies to the h8s/2237 series only. a tei interrupt is requested when the tend flag is set to 1 while the teie bit is set to 1. the tend flag is cleared at the same time as the tdre flag. consequently, if a tei interrupt and a txi interrupt are requested simultaneously, the txi interrupt may have priority for acceptance, with the result that the tdre and tend flags are cleared. note that the tei interrupt will not be accepted in this case.
483 13.5 usage notes the following points should be noted when using the sci. relation between writes to tdr and the tdre flag the tdre flag in ssr is a status flag that indicates that transmit data has been transferred from tdr to tsr. when the sci transfers data from tdr to tsr, the tdre flag is set to 1. data can be written to tdr regardless of the state of the tdre flag. however, if new data is written to tdr when the tdre flag is cleared to 0, the data stored in tdr will be lost since it has not yet been transferred to tsr. it is therefore essential to check that the tdre flag is set to 1 before writing transmit data to tdr. operation when multiple receive errors occur simultaneously if a number of receive errors occur at the same time, the state of the status flags in ssr is as shown in table 13-13. if there is an overrun error, data is not transferred from rsr to rdr, and the receive data is lost. table 13-13 state of ssr status flags and transfer of receive data ssr status flags receive data transfer rdrf orer fer per rsr to rdr receive error status 1100x overrun error 0010 framing error 0001 parity error 1110x overrun error + framing error 1101x overrun error + parity error 0011 framing error + parity error 1111x overrun error + framing error + parity error notes: : receive data is transferred from rsr to rdr. x: receive data is not transferred from rsr to rdr.
484 break detection and processing (asynchronous mode only): when framing error (fer) detection is performed, a break can be detected by reading the rxd pin value directly. in a break, the input from the rxd pin becomes all 0s, and so the fer flag is set, and the parity error flag (per) may also be set. note that, since the sci continues the receive operation after receiving a break, even if the fer flag is cleared to 0, it will be set to 1 again. sending a break (asynchronous mode only): the txd pin has a dual function as an i/o port whose direction (input or output) is determined by dr and ddr. this can be used to send a break. between serial transmission initialization and setting of the te bit to 1, the mark state is replaced by the value of dr (the pin does not function as the txd pin until the te bit is set to 1). consequently, ddr and dr for the port corresponding to the txd pin are first set to 1. to send a break during serial transmission, first clear dr to 0, then clear the te bit to 0. when the te bit is cleared to 0, the transmitter is initialized regardless of the current transmission state, the txd pin becomes an i/o port, and 0 is output from the txd pin. receive error flags and transmit operations (clocked synchronous mode only): transmission cannot be started when a receive error flag (orer, per, or fer) is set to 1, even if the tdre flag is cleared to 0. be sure to clear the receive error flags to 0 before starting transmission. note also that receive error flags cannot be cleared to 0 even if the re bit is cleared to 0. receive data sampling timing and reception margin in asynchronous mode: in asynchronous mode, the sci operates on a basic clock with a frequency of 16 times the transfer rate. in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 8th pulse of the basic clock. this is illustrated in figure 13-21.
485 internal basic clock 16 clocks 8 clocks receive data (rxd) synchronization sampling timing start bit d0 d1 data sampling timing 15 0 7 15 0 07 figure 13-21 receive data sampling timing in asynchronous mode thus the reception margin in asynchronous mode is given by formula (1) below. m = | (0.5 1 2n ) ?(l ?0.5) f | d ?0.5 | n (1 + f) | 100% ... formula (1) where m : reception margin (%) n : ratio of bit rate to clock (n = 16) d : clock duty (d = 0 to 1.0) l : frame length (l = 9 to 12) f : absolute value of clock rate deviation assuming values of f = 0 and d = 0.5 in formula (1), a reception margin of 46.875% is given by formula (2) below. when d = 0.5 and f = 0, m = (0.5 1 2 16 ) 100% = 46.875% ... formula (2) however, this is only the computed value, and a margin of 20% to 30% should be allowed in system design.
486 restrictions on use of dtc ? when an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 ?clock cycles after tdr is updated by the dtc. misoperation may occur if the transmit clock is input within 4 ?clocks after tdr is updated. (figure 13-22) ? when rdr is read by the dtc, be sure to set the activation source to the relevant sci reception end interrupt (rxi). t d0 lsb serial data sck d1 d3 d4 d5 d2 d6 d7 note: when operating on an external clock, set t >4 clocks. tdre figure 13-22 example of clocked synchronous transmission by dtc operation in case of mode transition ? transmission operation should be stopped (by clearing te, tie, and teie to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. tsr, tdr, and ssr are reset. the output pin states in module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode depend on the port settings, and becomes high-level output after the relevant mode is cleared. if a transition is made during transmission, the data being transmitted will be undefined. when transmitting without changing the transmit mode after the relevant mode is cleared, transmission can be started by setting te to 1 again, and performing the following sequence: ssr read -> tdr write -> tdre clearance. to transmit with a different transmit mode after clearing the relevant mode, the procedure must be started again from initialization. figure 13-23 shows a sample flowchart for mode transition during transmission. port pin states are shown in figures 13-24 and 13-25. operation should also be stopped (by clearing te, tie, and teie to 0) before making a transition from transmission by dtc transfer to module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. to perform transmission with the dtc after the relevant mode is cleared, setting te and tie to 1 will set the txi flag and start dtc transmission.
487 ? reception ? receive operation should be stopped (by clearing re to 0) before making a module stop mode, software standby mode, watch mode, subactive mode, or subsleep mode transition. rsr, rdr, and ssr are reset. if a transition is made without stopping operation, the data being received will be invalid. ? to continue receiving without changing the reception mode after the relevant mode is cleared, set re to 1 before starting reception. to receive with a different receive mode, the procedure must be started again from initialization. ? figure 13-26 shows a sample flowchart for mode transition during reception. read tend flag in ssr te= 0 transition to software standby mode, etc. exit from software standby mode, etc. change operating mode? no all data transmitted? tend = 1 yes yes yes no no [1] [3] [2] te= 1 initialization [1] data being transmitted is interrupt- ed. after exiting software standby mode, etc., normal cpu transmis- sion is possible by setting te to 1, reading ssr, writing tdr, and clearing tdre to 0, but note that if the dtc has been activated, the remaining data in dtcram will be transmitted when te and tie are set to 1. [2] if tie and teie are set to 1, clear them to 0 in the same way. [3] includes module stop mode, watch mode, subactive mode, and sub- sleep mode. figure 13-23 sample flowchart for mode transition during transmission
488 sck output pin te bit txd output pin port input/output high output port input/output high output start stop start of transmission end of transmission port input/output sci txd output port sci txd output port transition to software standby exit from software standby figure 13-24 asynchronous transmission using internal clock port input/output last txd bit held high output * port input/output marking output port input/output sci txd output port port note: * initialized by software standby. sck output pin te bit txd output pin sci txd output start of transmission end of transmission transition to software standby exit from software standby figure 13-25 synchronous transmission using internal clock
489 re= 0 transition to software standby mode, etc. read receive data in rdr read rdrf flag in ssr exit from software standby mode, etc. change operating mode? no rdrf= 1 yes yes no [1] [2] re= 1 initialization [1] receive data being received becomes invalid. [2] includes module stop mode, watch mode, subactive mode, and sub- sleep mode. figure 13-26 sample flowchart for mode transition during reception
490 switching from sck pin function to port pin function: ? problem in operation: when switching the sck pin function to the output port function (high- level output) by making the following settings while ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1 (synchronous mode), low-level output occurs for one half-cycle. 1. end of serial data transmission 2. te bit = 0 3. c/ a bit = 0 ... switchover to port output 4. occurrence of low-level output (see figure 13.27) sck/port data te c/a cke1 cke0 bit 7 bit 6 1. end of transmission 4. low-level output 3. c/a= 0 2.te = 0 half-cycle low-level output figure 13.27 operation when switching from sck pin function to port pin function
491 ? sample procedure for avoiding low-level output: as this sample procedure temporarily places the sck pin in the input state, the sck/port pin should be pulled up beforehand with an external circuit. with ddr = 1, dr = 1, c/ a = 1, cke1 = 0, cke0 = 0, and te = 1, make the following settings in the order shown. 1. end of serial data transmission 2. te bit = 0 3. cke1 bit = 1 4. c/ a bit = 0 ... switchover to port output 5. cke1 bit = 0 sck/port data te c/a cke1 cke0 bit 7 bit 6 1. end of transmission 3.cke1= 1 5.cke1= 0 4. c/a= 0 2.te = 0 high-level outputte figure 13.28 operation when switching from sck pin function to port pin function (example of preventing low-level output)
492
493 section 14 smart card interface 14.1 overview sci supports an ic card (smart card) interface conforming to iso/iec 7816-3 (identification card) as a serial communication interface extension function. switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 14.1.1 features features of the smart card interface supported by the h8s/2237 series and h8s/2227 series are as follows. on-chip channels h8s/2237 series: 4 on-chip channels (channels 0, 1, 2, 3) h8s/2227 series: 3 on-chip channels (channels 0, 1, 3) asynchronous mode ? data length: 8 bits ? parity bit generation and checking ? transmission of error signal (parity error) in receive mode ? error signal detection and automatic data retransmission in transmit mode ? direct convention and inverse convention both supported on-chip baud rate generator allows any bit rate to be selected three interrupt sources ? three interrupt sources (transmit data empty, receive data full, and transmit/receive error) that can issue requests independently ? the transmit data empty interrupt and receive data full interrupt can activate the data transfer controller (dtc) to execute data transfer
494 14.1.2 block diagram figure 14-1 shows a block diagram of the smart card interface. bus interface tdr rsr rdr module data bus tsr scmr ssr scr transmission/ reception control brr baud rate generator internal data bus rxd txd sck parity generation parity check clock ?4 ?16 ?64 txi rxi eri smr legend scmr rsr rdr tsr tdr smr scr ssr brr : smart card mode register : receive shift register : receive data register : transmit shift register : transmit data register : serial mode register : serial control register : serial status register : bit rate register figure 14-1 block diagram of smart card interface
495 14.1.3 pin configuration table 14-1 shows the smart card interface pin configuration. table 14-1 smart card interface pins channel pin name symbol i/o function 0 serial clock pin 0 sck0 i/o sci0 clock input/output receive data pin 0 rxd0 input sci0 receive data input transmit data pin 0 txd0 output sci0 transmit data output 1 serial clock pin 1 sck1 i/o sci1 clock input/output receive data pin 1 rxd1 input sci1 receive data input transmit data pin 1 txd1 output sci1 transmit data output 2 * serial clock pin 2 sck2 i/o sci2 clock input/output receive data pin 2 rxd2 input sci2 receive data input transmit data pin 2 txd2 output sci2 transmit data output 3 serial clock pin 3 sck3 i/o sci3 clock input/output receive data pin 3 rxd3 input sci3 receive data input transmit data pin 3 txd3 output sci3 transmit data output note: * applies to the h8s/2237 series only.
496 14.1.4 register configuration table 14-2 shows the registers used by the smart card interface. details of smr, brr, scr, tdr, rdr, and mstpcr are the same as for the normal sci function: see the register descriptions in section 12, serial communication interface. table 14-2 smart card interface registers channel name abbreviation r/w initial value address * 1 0 serial mode register 0 smr0 r/w h'00 h'ff78 bit rate register 0 brr0 r/w h'ff h'ff79 serial control register 0 scr0 r/w h'00 h'ff7a transmit data register 0 tdr0 r/w h'ff h'ff7b serial status register 0 ssr0 r/(w) * 2 h'84 h'ff7c receive data register 0 rdr0 r h'00 h'ff7d smart card mode register 0 scmr0 r/w h'f2 h'ff7e 1 serial mode register 1 smr1 r/w h'00 h'ff80 bit rate register 1 brr1 r/w h'ff h'ff81 serial control register 1 scr1 r/w h'00 h'ff82 transmit data register 1 tdr1 r/w h'ff h'ff83 serial status register 1 ssr1 r/(w) * 2 h'84 h'ff84 receive data register 1 rdr1 r h'00 h'ff85 smart card mode register 1 scmr1 r/w h'f2 h'ff86 2 * 3 serial mode register 2 smr2 r/w h'00 h'ff88 bit rate register 2 brr2 r/w h'ff h'ff89 serial control register 2 scr2 r/w h'00 h'ff8a transmit data register 2 tdr2 r/w h'ff h'ff8b serial status register 2 ssr2 r/(w) * 2 h'84 h'ff8c receive data register 2 rdr2 r h'00 h'ff8d smart card mode register 2 scmr2 r/w h'f2 h'ff8e
497 table 14-2 smart card interface registers (cont) channel name abbreviation r/w initial value address * 1 3 serial mode register 3 smr3 r/w h'00 h'fdd0 bit rate register 3 brr3 r/w h'ff h'fdd1 serial control register 3 scr3 r/w h'00 h'fdd2 transmit data register 3 tdr3 r/w h'ff h'fdd3 serial status register 3 ssr3 r/(w) * 2 h'84 h'fdd4 receive data register 3 rdr3 r h'00 h'fdd5 smart card mode register 3 scmr3 r/w h'f2 h'fdd6 all module stop control register b mstpcrb r/w h'ff h'fde9 module stop control register c mstpcrc r/w h'ff h'fdea notes: 1. lower 16 bits of the address. 2. can only be written with 0 for flag clearing. 3. applies to the h8s/2237 series only.
498 14.2 register descriptions registers added with the smart card interface and bits for which the function changes are described here. 14.2.1 smart card mode register (scmr) bit:7 65 43 21 0 sdir sinv smif initial value : 1 1 1 1 0 0 1 0 r/w : r/w r/w r/w scmr is an 8-bit readable/writable register that selects the smart card interface function. scmr is initialized to h'f2 by a reset and in standby mode. it retains its previous state in module stop mode, software standby mode, watch mode, subactive mode, and subsleep mode. bits 7 to 4?eserved: read-only bits, always read as 1. bit 3?mart card data transfer direction (sdir): selects the serial/parallel conversion format. bit 3 sdir description 0 tdr contents are transmitted lsb-first (initial value) receive data is stored in rdr lsb-first 1 tdr contents are transmitted msb-first receive data is stored in rdr msb-first
499 bit 2?mart card data invert (sinv): specifies inversion of the data logic level. this function is used together with the sdir bit for communication with an inverse convention card. the sinv bit does not affect the logic level of the parity bit. for parity-related setting procedures, see section 14.3.4, register settings. bit 2 sinv description 0 tdr contents are transmitted as they are (initial value) receive data is stored as it is in rdr 1 tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr bit 1?eserved: read-only bit, always read as 1. bit 0?mart card interface mode select (smif): enables or disables the smart card interface function. bit 0 smif description 0 smart card interface function is disabled (initial value) 1 smart card interface function is enabled 14.2.2 serial status register (ssr) bit:7 65 43 21 0 tdre rdrf orer ers per tend mpb mpbt initial value : 1 0 0 0 0 1 0 0 r/w : r/(w) * r/(w) * r/(w) * r/(w) * r/(w) * r r r/w note: * only 0 can be written, to clear these flags. bit 4 of ssr has a different function in smart card interface mode. coupled with this, the setting conditions for bit 2, tend, are also different. bits 7 to 5 operate in the same way as for the normal sci. for details, see section 13.2.7, serial status register (ssr).
500 bit 4?rror signal status (ers): in smart card interface mode, bit 4 indicates the status of the error signal sent back from the receiving end in transmission. framing errors are not detected in smart card interface mode. bit 4 ers description 0 normal reception, with no error signal [clearing condition] (initial value) upon reset, and in standby mode or module stop mode when 0 is written to ers after reading ers = 1 1 error signal sent from receiver indicating detection of parity error [setting condition] when the low level of the error signal is sampled note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its previous state. bits 3 to 0 operate in the same way as for the normal sci. for details, see section 13.2.7, serial status register (ssr). however, the setting conditions for the tend bit, are as shown below.
501 bit 2 tend description 0 transmission is in progress [clearing conditions] (initial value) when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and write data to tdr 1 transmission has ended [setting conditions] upon reset, and in standby mode or module stop mode when the te bit in scr is 0 and the ers bit is also 0 when tdre = 1 and ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 0 when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 when tdre = 1, 1.5 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 when tdre = 1, 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1 note: etu: elementary time unit (time for transfer of 1 bit) 14.2.3 serial mode register (smr) bit:7 65 43 21 0 gm blk pe o/ e bcp1 bcp0 cks1 cks0 initial value : 0 0 0 0 0 0 0 0 set value * :gm 0 1 o/ e 1 0 cks1 cks0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w note: * when the smart card interface is used, be sure to make the 1 setting shown for bit 5. the function of bits 7, 6, 3, and 2 of smr changes in smart card interface mode. bit 7?sm mode (gm): sets the smart card interface function to gsm mode. this bit is cleared to 0 when the normal smart card interface is used. in gsm mode, this bit is set to 1, the timing of setting of the tend flag that indicates transmission completion is advanced and clock output control mode addition is performed. the contents of the clock output control mode addition are specified by bits 1 and 0 of the serial control register (scr).
502 bit 7 gm description 0 normal smart card interface mode operation (initial value) tend flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit clock output on/off control only 1 gsm mode smart card interface mode operation tend flag generation 11.0 etu after beginning of start bit high/low fixing control possible in addition to clock output on/off control (set by scr) note: etu: elementary time unit (time for transfer of 1 bit) bit 6?lock transfer mode (blk): selects block transfer mode. bit 6 blk description 0 normal smart card interface mode operation error signal transmission/detection and automatic data retransmission performed txi interrupt generated by tend flag tend flag set 12.5 etu after start of transmission (11.0 etu in gsm mode) 1 block transfer mode operation error signal transmission/detection and automatic data retransmission not performed txi interrupt generated by tdre flag tend flag set 11.5 etu after start of transmission (11.0 etu in gsm mode) bits 3 and 2?asic clock pulse 1 and 2 (bcp1, bcp0): these bits specify the number of basic clock periods in a 1-bit transfer interval on the smart card interface. bit 3 bit 2 bcp1 bcp0 description 0 1 32 clock periods (initial value) 0 64 clock periods 1 1 372 clock periods 0 256 clock periods bits 5, 4, 1, and 0: operate in the same way as for the normal sci. for details, see section 13.2.5, serial mode register (smr).
503 14.2.4 serial control register (scr) bit:7 65 43 21 0 tie rie te re mpie teie cke1 cke0 initial value : 0 0 0 0 0 0 0 0 r/w : r/w r/w r/w r/w r/w r/w r/w r/w in smart card interface mode, the function of bits 1 and 0 of scr changes when bit 7 of the serial mode register (smr) is set to 1. bits 7 to 2 ?perate in the same way as for the normal sci. for details, see section 13.2.6, serial control register (scr). bits 1 and 0?lock enable 1 and 0 (cke1, cke0): these bits are used to select the sci clock source and enable or disable clock output from the sck pin. in smart card interface mode, in addition to the normal switching between clock output enabling and disabling, the clock output can be specified as to be fixed high or low. scmr smr scr setting smif c/ a , gm cke1 cke0 sck pin function 0 see the sci 1 0 0 0 operates as port i/o pin 1 0 0 1 outputs clock as sck output pin 1 1 0 0 operates as sck output pin, with output fixed low 1 1 0 1 outputs clock as sck output pin 1 1 1 0 operates as sck output pin, with output fixed high 1 1 1 1 outputs clock as sck output pin
504 14.3 operation 14.3.1 overview the main functions of the smart card interface are as follows. one frame consists of 8-bit data plus a parity bit. in transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of one bit), or 1 etu in block transfer mode, is provided between the end of the parity bit and the start of the next frame. if a parity error is detected during reception, a low error signal level is output for a1 etu period 10.5 etu after the start bit (except in block transfer mode). if the error signal is sampled during transmission, the same data is transmitted automatically after the elapse of 2 etu or longer. (except in block transfer mode) only asynchronous communication is supported; there is no clocked synchronous communication function. 14.3.2 pin connections figure 14-2 shows a schematic diagram of smart card interface related pin connections. in communication with an ic card, since both transmission and reception are carried out on a single data transmission line, the txd pin and rxd pin should be connected with the lsi pin. the data transmission line should be pulled up to the v cc power supply with a resistor. when the clock generated on the smart card interface is used by an ic card, the sck pin output is input to the clk pin of the ic card. no connection is needed if the ic card uses an internal clock. lsi port output is used as the reset signal. other pins must normally be connected to the power supply or ground.
505 txd rxd sck rx (port) h8s/2237 and h8s/2227 i/o clk rst v cc connected equipment ic card data line clock line reset line figure 14-2 schematic diagram of smart card interface pin connections note: if an ic card is not connected, and the te and re bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out.
506 14.3.3 data format (1) normal transfer mode figure 14-3 shows the normal smart card interface data format. in reception in this mode, a parity check is carried out on each frame, and if an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. if an error signal is sampled during transmission, the same data is retransmitted. ds d0 d1 d2 d3 d4 d5 d6 d7 dp when there is no parity error transmitting station output ds d0 d1 d2 d3 d4 d5 d6 d7 dp when a parity error occurs transmitting station output de receiving station output : start bit : data bits : parity bit : error signal legend ds d0 to d7 dp de figure 14-3 normal smart card interface data format
507 the operation sequence is as follows. [1] when the data line is not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] the transmitting station starts transfer of one frame of data. the data frame starts with a start bit (ds, low-level), followed by 8 data bits (d0 to d7) and a parity bit (dp). [3] with the smart card interface, the data line then returns to the high-impedance state. the data line is pulled high with a pull-up resistor. [4] the receiving station carries out a parity check. if there is no parity error and the data is received normally, the receiving station waits for reception of the next data. if a parity error occurs, however, the receiving station outputs an error signal (de, low-level) to request retransmission of the data. after outputting the error signal for the prescribed length of time, the receiving station places the signal line in the high-impedance state again. the signal line is pulled high again by a pull-up resistor. [5] if the transmitting station does not receive an error signal, it proceeds to transmit the next data frame. if it does receive an error signal, however, it returns to step [2] and retransmits the erroneous data. (2) block transfer mode the operation sequence in block transfer mode is as follows. [1] when the data line in not in use it is in the high-impedance state, and is fixed high with a pull- up resistor. [2] the transmitting station starts transfer of one frame of data. the data frame starts with a start bit (ds, low-level), followed by 8 data bits (d0 to d7) and a parity bit (dp). [3] with the smart card interface, the data line then returns to the high-impedance state. the data line is pulled high with a pull-up resistor. [4] after reception, a parity error check is carried out, but an error signal is not output even if an error has occurred. when an error occurs reception cannot be continued, so the error flag should be cleared to 0 before the parity bit of the next frame is received. [5] the transmitting station proceeds to transmit the next data frame.
508 14.3.4 register settings table 14-3 shows a bit map of the registers used by the smart card interface. bits indicated as 0 or 1 must be set to the value shown. the setting of other bits is described below. table 14-3 smart card interface register settings bit register bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 smr gm blk 1 o/ e bcp1 bcp0 cks1 cks0 brr brr7 brr6 brr5 brr4 brr3 brr2 brr1 brr0 scr tie rie te re 0 0 cke1 * cke0 tdr tdr7 tdr6 tdr5 tdr4 tdr3 tdr2 tdr1 tdr0 ssr tdre rdrf orer ers per tend 0 0 rdr rdr7 rdr6 rdr5 rdr4 rdr3 rdr2 rdr1 rdr0 scmr sdir sinv smif notes: ?: unused bit. * : the cke1 bit must be cleared to 0 when the gm bit in smr is cleared to 0. smr setting: the gm bit is cleared to 0 in normal smart card interface mode, and set to 1 in gsm mode. the o/ e bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. bits cks1 and cks0 select the clock source of the on-chip baud rate generator. bits bcp1 and bcp0 select the number of basic clock periods in a 1-bit transfer interval. for details, see section 14.3.5, clock. the blk bit is cleared to 0 in normal smart card interface mode, and set to 1 in block transfer mode. brr setting: brr is used to set the bit rate. see section 14.3.5, clock, for the method of calculating the value to be set. scr setting: the function of the tie, rie, te, and re bits is the same as for the normal sci. for details, see section 13, serial communication interface. bits cke1 and cke0 specify the clock output. when the gm bit in smr is cleared to 0, set these bits to b'00 if a clock is not to be output, or to b'01 if a clock is to be output. when the gm bit in smr is set to 1, clock output is performed. the clock output can also be fixed high or low.
509 smart card mode register (scmr) setting: the sdir bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. the sinv bit is cleared to 0 if the ic card is of the direct convention type, and set to 1 if of the inverse convention type. the smif bit is set to 1 in the case of the smart card interface. examples of register settings and the waveform of the start character are shown below for the two types of ic card (direct convention and inverse convention). direct convention (sdir = sinv = o/ e = 0) ds d0 d1 d2 d3 d4 d5 d6 d7 dp azzazzzaaz (z) (z) state with the direct convention type, the logic 1 level corresponds to state z and the logic 0 level to state a, and transfer is performed in lsb-first order. the start character data above is h'3b. the parity bit is 1 since even parity is stipulated for the smart card. inverse convention (sdir = sinv = o/ e = 1) ds d7 d6 d5 d4 d3 d2 d1 d0 dp azzaaaaaaz (z) (z) state with the inverse convention type, the logic 1 level corresponds to state a and the logic 0 level to state z, and transfer is performed in msb-first order. the start character data above is h'3f. the parity bit is 0, corresponding to state z, since even parity is stipulated for the smart card. with the h8s/2237 series and h8s/2227 series, inversion specified by the sinv bit applies only to the data bits, d7 to d0. for parity bit inversion, the o/ e bit in smr is set to odd parity mode (the same applies to both transmission and reception).
510 14.3.5 clock only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock for the smart card interface. the bit rate is set with brr and the cks1, cks0, bcp1 and bcp0 bits in smr. the formula for calculating the bit rate is as shown below. table 14-5 shows some sample bit rates. if clock output is selected by setting cke0 to 1, a clock is output from the sck pin. the clock frequency is determined by the bit rate and the setting of bits bcp1 and bcp0. b = s 2 2n+1 (n + 1) 10 6 where: n = value set in brr (0 n 255) b = bit rate (bit/s) ?= operating frequency (mhz) n = see table 14-4 s = number of internal clocks in 1-bit period, set by bcp1 and bcp0 table 14-4 correspondence between n and cks1, cks0 n cks1 cks0 000 11 210 31 table 14-5 examples of bit rate b (bit/s) for various brr settings (when n = 0 and s = 372) ?(mhz) n 5.00 7.00 7.1424 10.00 10.714 13.00 0 6720 9409 9600 13441 14400 17473 1 3360 4704 4800 6720 7200 8737 2 2240 3136 3200 4480 4800 5824 note: bit rates are rounded to the nearest whole number.
511 the method of calculating the value to be set in the bit rate register (brr) from the operating frequency and bit rate, on the other hand, is shown below. n is an integer, 0 n 255, and the smaller error is specified. n = s 2 2n+1 b 10 6 ?1 table 14-6 examples of brr settings for bit rate b (bit/s) (when n = 0 and s = 372) ?(mhz) 5.00 7.00 7.1424 10.00 10.7136 13.00 bit/s n error n error n error n error n error n error 6720 0 0.00 1 30 1 28.75 1 0.01 1 7.14 2 13.33 9600 0 0.00 1 30 1 25 1 8.99 note: a blank means no setting is available. table 14-7 maximum bit rate at various frequencies (smart card interface mode) (when s = 372) ?(mhz) maximum bit rate (bit/s) n n 5.00 6720 0 0 7.00 9409 0 0 7.1424 9600 0 0 10.00 13441 0 0 10.7136 14400 0 0 13.00 17473 0 0 the bit rate error is given by the following formula: error (%) = ( s 2 2n+1 b (n + 1) 10 6 ?1) 100
512 14.3.6 data transfer operations initialization: before transmitting and receiving data, initialize the sci as described below. initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] clear the te and re bits in scr to 0. [2] clear the error flags ers, per, and orer in ssr to 0. [3] set the gm, blk, o/ e , bcp1, bcp0, cks1, cks0 bits in smr. set the pe bit to 1. [4] set the smif, sdir, and sinv bits in scmr. when the smif bit is set to 1, the txd and rxd pins are both switched from ports to sci pins, and are placed in the high-impedance state. [5] set the value corresponding to the bit rate in brr. [6] set the cke0 bit in scr. clear the tie, rie, te, re, mpie, teie and cke1 bits to 0. if the cke0 bit is set to 1, the clock is output from the sck pin. [7] wait at least one bit interval, then set the tie, rie, te, and re bits in scr. do not set the te bit and re bit at the same time, except for self-diagnosis.
513 serial data transmission (except in block transfer mode): as data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal sci. figure 14-4 shows a flowchart for transmitting, and figure 14-5 shows the relation between a transmit operation and the internal registers. [1] perform smart card interface mode initialization as described above in initialization. [2] check that the ers error flag in ssr is cleared to 0. [3] repeat steps [2] and [3] until it can be confirmed that the tend flag in ssr is set to 1. [4] write the transmit data to tdr, clear the tdre flag to 0, and perform the transmit operation. the tend flag is cleared to 0. [5] when transmitting data continuously, go back to step [2]. [6] to end transmission, clear the te bit to 0. with the above processing, interrupt servicing or data transfer by the dtc is possible. if transmission ends and the tend flag is set to 1 while the tie bit is set to 1 and interrupt requests are enabled, a transmit data empty interrupt (txi) request will be generated. if an error occurs in transmission and the ers flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a transfer error interrupt (eri) request will be generated. the timing for setting the tend flag depends on the value of the gm bit in smr. the tend flag set timing is shown in figure 14-6. if the dtc is activated by a txi request, the number of bytes set in the dtc can be transmitted automatically, including automatic retransmission. for details, see interrupt operation (except block transfer mode) and data transfer operation by dtc below. note: for block transfer mode, see section 13.3.2, operation in asynchronous mode.
514 initialization no yes clear te bit to 0 start transmission start no no no yes yes yes yes no end write data to tdr, and clear tdre flag in ssr to 0 error processing error processing tend=1? all data transmitted? tend=1? ers=0? ers=0? figure 14-4 example of transmission processing flow
515 (1) data write tdr tsr (shift register) data 1 (2) transfer from tdr to tsr data 1 data 1 ; data remains in tdr (3) serial data output note: when the ers flag is set, it should be cleared until transfer of the last bit (d7 in lsb-first transmission, d0 in msb-first transmission) of the next transfer data to be transmitted has been completed. in case of normal transmission: tend flag is set in case of transmit error: ers flag is set steps (2) and (3) above are repeated until the tend flag is set i/o signal line output data 1 data 1 figure 14-5 relation between transmit operation and internal registers ds d0 d1 d2 d3 d4 d5 d6 d7 dp i/o data 12.5etu txi (tend interrupt) 11.0etu de guard time when gm = 1 legend ds : start bit d0 to d7 : data bits dp : parity bit de : error signal when gm = 0 figure 14-6 tend flag generation timing in transmission operation
516 serial data reception: data reception in smart card mode uses the same processing procedure as for the normal sci. figure 14-7 shows an example of the transmission processing flow. [1] perform smart card interface mode initialization as described above in initialization. [2] check that the orer flag and per flag in ssr are cleared to 0. if either is set, perform the appropriate receive error processing, then clear both the orer and the per flag to 0. [3] repeat steps [2] and [3] until it can be confirmed that the rdrf flag is set to 1. [4] read the receive data from rdr. [5] when receiving data continuously, clear the rdrf flag to 0 and go back to step [2]. [6] to end reception, clear the re bit to 0. initialization read rdr and clear rdrf flag in ssr to 0 clear re bit to 0 start reception start error processing no no no yes yes orer = 0 and per = 0 rdrf=1? all data received? yes figure 14-7 example of reception processing flow
517 with the above processing, interrupt servicing or data transfer by the dtc is possible. if reception ends and the rdrf flag is set to 1 while the rie bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (rxi) request will be generated. if an error occurs in reception and either the orer flag or the per flag is set to 1, a transfer error interrupt (eri) request will be generated. if the dtc is activated by an rxi request, the receive data in which the error occurred is skipped, and only the number of bytes of receive data set in the dtc are transferred. for details, see interrupt operation and data transfer operation by dtc below. if a parity error occurs during reception and the per is set to 1, the received data is still transferred to rdr, and therefore this data can be read. note: for block transfer mode, see section 13.3.2, operation in asynchronous mode. mode switching operation: when switching from receive mode to transmit mode, first confirm that the receive operation has been completed, then start from initialization, clearing re bit to 0 and setting te bit to 1. the rdrf flag or the per and orer flags can be used to check that the receive operation has been completed. when switching from transmit mode to receive mode, first confirm that the transmit operation has been completed, then start from initialization, clearing te bit to 0 and setting re bit to 1. the tend flag can be used to check that the transmit operation has been completed. fixing clock output level: when the gm bit in smr is set to 1, the clock output level can be fixed with bits cke1 and cke0 in scr. at this time, the minimum clock pulse width can be made the specified width. figure 14-8 shows the timing for fixing the clock output level. in this example, gm is set to 1, cke1 is cleared to 0, and the cke0 bit is controlled. sck specified pulse width scr write (cke0 = 0) scr write (cke0 = 1) specified pulse width figure 14-8 timing for fixing clock output level interrupt operation (except block transfer mode): there are three interrupt sources in smart card interface mode: transmit data empty interrupt (txi) requests, transfer error interrupt (eri)
518 requests, and receive data full interrupt (rxi) requests. the transmit end interrupt (tei) request is not used in this mode. when the tend flag in ssr is set to 1, a txi interrupt request is generated. when the rdrf flag in ssr is set to 1, an rxi interrupt request is generated. when any of flags orer, per, and ers in ssr is set to 1, an eri interrupt request is generated. the relationship between the operating states and interrupt sources is shown in table 14-8. note: for block transfer mode, see section 13.4, sci interrupts. table 14-8 smart card mode operating states and interrupt sources operating state flag enable bit interrupt source dtc activation transmit mode normal operation tend tie txi possible error ers rie eri not possible receive mode normal operation rdrf rie rxi possible error per, orer rie eri not possible data transfer operation by dtc: in smart card mode, as with the normal sci, transfer can be carried out using the dtc. in a transmit operation, the tdre flag is also set to 1 at the same time as the tend flag in ssr, and a txi interrupt is generated. if the txi request is designated beforehand as a dtc activation source, the dtc will be activated by the txi request, and transfer of the transmit data will be carried out. the tdre and tend flags are automatically cleared to 0 when data transfer is performed by the dtc. in the event of an error, the sci retransmits the same data automatically. during this period, tend remains cleared to 0 and the dtc is not activated. therefore, the sci and dtc will automatically transmit the specified number of bytes, including retransmission in the event of an error. however, the ers flag is not cleared automatically when an error occurs, and so the rie bit should be set to 1 beforehand so that an eri request will be generated in the event of an error, and the ers flag will be cleared. when performing transfer using the dtc, it is essential to set and enable the dtc before carrying out sci setting. for details of the dtc setting procedures, see section 8, data transfer controller (dtc). in a receive operation, an rxi interrupt request is generated when the rdrf flag in ssr is set to 1. if the rxi request is designated beforehand as a dtc activation source, the dtc will be activated by the rxi request, and transfer of the receive data will be carried out. the rdrf flag is cleared to 0 automatically when data transfer is performed by the dtc. if an error occurs, an error flag is set but the rdrf flag is not. consequently, the dtc is not activated, but instead, an eri interrupt request is sent to the cpu. therefore, the error flag should be cleared.
519 note: for block transfer mode, see section 13.4, sci interrupts. 14.3.7 operation in gsm mode switching the mode: when switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. when changing from smart card interface mode to software standby mode [1] set the data register (dr) and data direction register (ddr) corresponding to the sck pin to the value for the fixed output state in software standby mode. [2] write 0 to the te bit and re bit in the serial control register (scr) to halt transmit/receive operation. at the same time, set the cke1 bit to the value for the fixed output state in software standby mode. [3] write 0 to the cke0 bit in scr to halt the clock. [4] wait for one serial clock period. during this interval, clock output is fixed at the specified level, with the duty preserved. [5] make the transition to the software standby state. when returning to smart card interface mode from software standby mode [6] exit the software standby state. [7] write 1 to the cke0 bit in scr and output the clock. signal generation is started with the normal duty. [1] [2] [3] [4] [5] [6] [7] software standby normal operation normal operation figure 14-9 clock halt and restart procedure
520 powering on: to secure the clock duty from power-on, the following switching procedure should be followed. [1] the initial state is port input and high impedance. use a pull-up resistor or pull-down resistor to fix the potential. [2] fix the sck pin to the specified output level with the cke1 bit in scr. [3] set smr and scmr, and switch to smart card mode operation. [4] set the cke0 bit in scr to 1 to start clock output. 14.3.8 operation in block transfer mode operation in block transfer mode is the same as in sci asynchronous mode, except for the following points. for details, see section 13.3.2, operation in asynchronous mode. (1) data format the data format is 8 bits with parity. there is no stop bit, but there is a 2-bit (1-bit or more in reception) error guard time. also, except during transmission (with start bit, data bits, and parity bit), the transmission pins go to the high-impedance state, so the signal lines must be fixed high with a pull-up resistor. (2) transmit/receive clock only an internal clock generated by the on-chip baud rate generator can be used as the transmit/receive clock. the number of basic clock periods in a 1-bit transfer interval can be set to 32, 64, 372, or 256 with bits bcp1 and bcp0. for details, see section 14.3.5, clock. (3) ers (fer) flag as with the normal smart card interface, the ers flag indicates the error signal status, but since error signal transmission and reception is not performed, this flag is always cleared to 0.
521 14.4 usage notes the following points should be noted when using the sci as a smart card interface. receive data sampling timing and reception margin in smart card interface mode: in smart card interface mode, the sci operates on a basic clock with a frequency of 32, 64, 372, or 256 times the transfer rate (as determined by bits bcp1 and bcp0). in reception, the sci samples the falling edge of the start bit using the basic clock, and performs internal synchronization. receive data is latched internally at the rising edge of the 16th, 32nd, 186th, or 128th pulse of the basic clock. figure 14-10 shows the receive data sampling timing when using a clock of 372 times the transfer rate. internal basic clock 372 clocks 186 clocks receive data (rxd) synchro- nization sampling timing d0 d1 data sampling timing 185 371 0 371 185 0 0 start bit figure 14-10 receive data sampling timing in smart card mode (using clock of 372 times the transfer rate)
522 thus the reception margin in asynchronous mode is given by the following formula. formula for reception margin in smart card interface mode m = (0.5 1 2n ) ?(l ?0.5) f d ?0.5 n (1 + f ) 100% where m: reception margin (%) n: ratio of bit rate to clock (n = 32, 64, 372, and 256) d: clock duty (d = 0 to 1.0) l: frame length (l = 10) f: absolute value of clock frequency deviation assuming values of f = 0, d = 0.5 and n = 372 in the above formula, the reception margin formula is as follows. when d = 0.5 and f = 0, m = (0.5 ?1/2 372) 100% = 49.866% retransfer operations (except block transfer mode): retransfer operations are performed by the sci in receive mode and transmit mode as described below. retransfer operation when sci is in receive mode figure 14-11 illustrates the retransfer operation when the sci is in receive mode. [1] if an error is found when the received parity bit is checked, the per bit in ssr is automatically set to 1. if the rie bit in scr is enabled at this time, an eri interrupt request is generated. the per bit in ssr should be kept cleared to 0 until the next parity bit is sampled. [2] the rdrf bit in ssr is not set for a frame in which an error has occurred. [3] if no error is found when the received parity bit is checked, the per bit in ssr is not set to 1. [4] if no error is found when the received parity bit is checked, the receive operation is judged to have been completed normally, and the rdrf flag in ssr is automatically set to 1. if the rie bit in scr is enabled at this time, an rxi interrupt request is generated. if dtc data transfer by an rxi source is enabled, the contents of rdr can be read automatically. when the rdr data is read by the dtc, the rdrf flag is automatically cleared to 0. [5] when a normal frame is received, the pin retains the high-impedance state at the timing for error signal transmission.
523 d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n+1 retransferred frame nth transfer frame rdrf [1] per [2] [3] [4] figure 14-11 retransfer operation in sci receive mode retransfer operation when sci is in transmit mode figure 14-12 illustrates the retransfer operation when the sci is in transmit mode. [6] if an error signal is sent back from the receiving end after transmission of one frame is completed, the ers bit in ssr is set to 1. if the rie bit in scr is enabled at this time, an eri interrupt request is generated. the ers bit in ssr should be kept cleared to 0 until the next parity bit is sampled. [7] the tend bit in ssr is not set for a frame for which an error signal indicating an abnormality is received. [8] if an error signal is not sent back from the receiving end, the ers bit in ssr is not set. [9] if an error signal is not sent back from the receiving end, transmission of one frame, including a retransfer, is judged to have been completed, and the tend bit in ssr is set to 1. if the tie bit in scr is enabled at this time, a txi interrupt request is generated. if data transfer by the dtc by means of the txi source is enabled, the next data can be written to tdr automatically. when data is written to tdr by the dtc, the tdre bit is automatically cleared to 0. d0 d1 d2 d3 d4 d5 d6 d7 dp de ds d0 d1 d2 d3 d4 d5 d6 d7 dp (de) ds d0 d1 d2 d3 d4 ds transfer frame n+1 retransferred frame nth transfer frame tdre tend [6] fer/ers transfer to tsr from tdr [7] [9] [8] transfer to tsr from tdr transfer to tsr from tdr figure 14-12 retransfer operation in sci transmit mode
524
525 section 15 a/d converter 15.1 overview the h8s/2237 series and h8s/2227 series incorporates a successive approximation type 10-bit a/d converter that allows up to eight analog input channels to be selected. 15.1.1 features a/d converter features are listed below 10-bit resolution eight input channels settable analog conversion voltage range ? conversion of analog voltages with the reference voltage pin (v ref ) as the analog reference voltage high-speed conversion ? minimum conversion time: 13.4 m s per channel (at 10 mhz operation) choice of single mode or scan mode ? single mode: single-channel a/d conversion ? scan mode: continuous a/d conversion on 1 to 4 channels four data registers ? conversion results are held in a 16-bit data register for each channel sample and hold function three kinds of conversion start ? choice of software or timer conversion start trigger (tpu or 8-bit timer), or adtrg pin a/d conversion end interrupt generation ? a/d conversion end interrupt (adi) request can be generated at the end of a/d conversion module stop mode can be set ? as the initial setting, a/d converter operation is halted. register access is enabled by exiting module stop mode.
526 15.1.2 block diagram figure 15-1 shows a block diagram of the a/d converter. module data bus control circuit internal data bus 10-bit d/a comparator + sample-and- hold circuit ?2 ?4 ?8 adi interrupt ?16 bus interface a d c s r a d c r a d d r d a d d r c a d d r b a d d r a av cc v ref av ss an0 an1 an2 an3 an4 an5 an6 an7 adtrg conversion start trigger from 8-bit timer or tpu successive approximations register multiplexer adcr adcsr addra addrb addrc addrd : a/d control register : a/d control/status register : a/d data register a : a/d data register b : a/d data register c : a/d data register d figure 15-1 block diagram of a/d converter
527 15.1.3 pin configuration table 15-1 summarizes the input pins used by the a/d converter. the avcc and avss pins are the power supply pins for the analog block in the a/d converter. the vref pin is the a/d conversion reference voltage pin. the eight analog input pins are divided into two groups: group 0 (an0 to an3), and group 1 (an4 to an7). table 15-1 a/d converter pins pin name symbol i/o function analog power supply pin avcc input analog block power supply analog ground pin avss input analog block ground and reference voltage reference voltage pin vref input a/d conversion reference voltage analog input pin 0 an0 input group 0 analog inputs analog input pin 1 an1 input analog input pin 2 an2 input analog input pin 3 an3 input analog input pin 4 an4 input group 1 analog inputs analog input pin 5 an5 input analog input pin 6 an6 input analog input pin 7 an7 input a/d external trigger input pin adtrg input external trigger input for starting a/d conversion
528 15.1.4 register configuration table 15-2 summarizes the registers of the a/d converter. table 15-2 a/d converter registers name abbreviation r/w initial value address * 1 a/d data register ah addrah r h'00 h'ff90 a/d data register al addral r h'00 h'ff91 a/d data register bh addrbh r h'00 h'ff92 a/d data register bl addrbl r h'00 h'ff93 a/d data register ch addrch r h'00 h'ff94 a/d data register cl addrcl r h'00 h'ff95 a/d data register dh addrdh r h'00 h'ff96 a/d data register dl addrdl r h'00 h'ff97 a/d control/status register adcsr r/(w) * 2 h'00 h'ff98 a/d control register adcr r/w h'33 h'ff99 module stop control register a mstpcra r/w h'3f h'fde8 notes: 1. lower 16 bits of the address. 2. bit 7 can only be written with 0 for flag clearing.
529 15.2 register descriptions 15.2.1 a/d data registers a to d (addra to addrd) 15 ad9 0 r bit initial value r/w : : : 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r there are four 16-bit read-only addr registers, addra to addrd, used to store the results of a/d conversion. the 10-bit data resulting from a/d conversion is transferred to the addr register for the selected channel and stored there. the upper 8 bits of the converted data are transferred to the upper byte (bits 15 to 8) of addr, and the lower 2 bits are transferred to the lower byte (bits 7 and 6) and stored. bits 5 to 0 are always read as 0. the correspondence between the analog input channels and addr registers is shown in table 15-3. addr can always be read by the cpu. the upper byte can be read directly, but for the lower byte, data transfer is performed via a temporary register (temp). for details, see section 15.3, interface to bus master. the addr registers are initialized to h'0000 by a reset, and in standby mode or module stop mode. table 15-3 analog input channels and corresponding addr registers analog input channel group 0 group 1 a/d data register an0 an4 addra an1 an5 addrb an2 an6 addrc an3 an7 addrd
530 15.2.2 a/d control/status register (adcsr) 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w bit initial value r/w : : : note: * only 0 can be written to bit 7, to clear this flag. adcsr is an 8-bit readable/writable register that controls a/d conversion operations. adcsr is initialized to h'00 by a reset, and in hardware standby mode or module stop mode. bit 7?/d end flag (adf): status flag that indicates the end of a/d conversion. bit 7 adf description 0 [clearing conditions] (initial value) when 0 is written to the adf flag after reading adf = 1 when the dtc is activated by an adi interrupt and addr is read 1 [setting conditions] single mode: when a/d conversion ends scan mode: when a/d conversion ends on all specified channels bit 6?/d interrupt enable (adie): selects enabling or disabling of interrupt (adi) requests at the end of a/d conversion. bit 6 adie description 0 a/d conversion end interrupt (adi) request disabled (initial value) 1 a/d conversion end interrupt (adi) request enabled
531 bit 5?/d start (adst): selects starting or stopping on a/d conversion. holds a value of 1 during a/d conversion. the adst bit can be set to 1 by software, a timer conversion start trigger, or the a/d external trigger input pin ( adtrg ). bit 5 adst description 0 a/d conversion stopped (initial value) 1 single mode: a/d conversion is started. cleared to 0 automatically when conversion on the specified channel ends scan mode: a/d conversion is started. conversion continues sequentially on the selected channels until adst is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. bit 4?can mode (scan): selects single mode or scan mode as the a/d conversion operating mode. see section 15.4, operation, for single mode and scan mode operation. only set the scan bit while conversion is stopped. bit 4 scan description 0 single mode (initial value) 1 scan mode bit 3?eserved: 0 should be written to this bit. bits 2 to 0?hannel select 2 to 0 (ch2 to ch0): together with the scan bit, these bits select the analog input channels. only set the input channel while conversion is stopped (adst = 0).
532 group selection channel selection description ch2 ch1 ch0 single mode (scan = 0) scan mode (scan = 1) 0 0 0 an0 (initial value) an0 1 an1 an0, an1 1 0 an2 an0 to an2 1 an3 an0 to an3 1 0 0 an4 an4 1 an5 an4, an5 1 0 an6 an4 to an6 1 an7 an4 to an7 15.2.3 a/d control register (adcr) 7 trgs1 0 r/w 6 trgs0 0 r/w 5 1 4 1 3 cks1 0 r/w 0 1 r/w 2 cks0 0 r/w 1 1 bit initial value r/w : : : adcr is an 8-bit readable/writable register that enables or disables external triggering of a/d conversion operations and sets the a/d conversion time. adcr is initialized to h'33 by a reset, and in standby mode or module stop mode. bits 7 and 6?imer trigger select 1 and 0 (trgs1, trgs0): select enabling or disabling of the start of a/d conversion by a trigger signal. only set bits trgs1 and trgs0 while conversion is stopped (adst = 0). bit 7 bit 6 trgs1 trgs0 description 0 0 a/d conversion start by software is enabled (initial value) 1 a/d conversion start by tpu conversion start trigger is enabled 1 0 a/d conversion start by 8-bit timer conversion start trigger is enabled 1 a/d conversion start by external trigger pin ( adtrg ) is enabled bits 5, 4 and 1?eserved: these bits are reserved; they are always read as 1 and cannot be modified.
533 bits 3 and 2?lock select 1 and 0 (cks1, cks0): these bits select the a/d conversion time. the conversion time should be changed only when adst = 0. the conversion time setting should not exceed the conversion times shown in section 21.5, a/d conversion characteristics. bit 3 bit 2 cks1 cks0 description 0 0 conversion time = 530 states (max.) (initial value) 1 conversion time = 260 states (max.) 1 0 conversion time = 134 states (max.) 1 conversion time = 68 states (max.) bit 0?eserved: 1 should be written to this bit. 15.2.4 module stop control register a (mstpcra) 7 mstpa7 0 r/w 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 0 mstpa0 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w bit initial value r/w : : : mstpcr is a 8-bit readable/writable register that performs module stop mode control. when the mstpa1 bit in mstpcr is set to 1, a/d converter operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 20.5, module stop mode. mstpcra is initialized to h'3f by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 1?odule stop (mstpa1): specifies the a/d converter module stop mode. bit 1 mstpa1 description 0 a/d converter module stop mode cleared 1 a/d converter module stop mode set (initial value)
534 15.3 interface to bus master addra to addrd are 16-bit registers, and the data bus to the bus master is 8 bits wide. therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (temp). a data read from addr is performed as follows. when the upper byte is read, the upper byte value is transferred to the cpu and the lower byte value is transferred to temp. next, when the lower byte is read, the temp contents are transferred to the cpu. when reading addr. always read the upper byte before the lower byte. it is possible to read only the upper byte, but if only the lower byte is read, incorrect data may be obtained. figure 15-2 shows the data flow for addr access. bus master (h'aa) addrnh (h'aa) addrnl (h'40) lower byte read addrnh (h'aa) addrnl (h'40) temp (h'40) temp (h'40) (n = a to d) (n = a to d) module data bus module data bus bus interface upper byte read bus master (h'40) bus interface figure 15-2 addr access operation (reading h'aa40)
535 15.4 operation the a/d converter operates by successive approximation with 10-bit resolution. it has two operating modes: single mode and scan mode. 15.4.1 single mode (scan = 0) single mode is selected when a/d conversion is to be performed on a single channel only. a/d conversion is started when the adst bit is set to 1, according to the software or external trigger input. the adst bit remains set to 1 during a/d conversion, and is automatically cleared to 0 when conversion ends. on completion of conversion, the adf flag is set to 1. if the adie bit is set to 1 at this time, an adi interrupt request is generated. the adf flag is cleared by writing 0 after reading adcsr. when the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again. the adst bit can be set at the same time as the operating mode or input channel is changed. typical operations when channel 1 (an1) is selected in single mode are described next. figure 15-3 shows a timing diagram for this example. [1] single mode is selected (scan = 0), input channel an1 is selected (ch2 = 0, ch1 = 0, ch0? 1), the a/d interrupt is enabled (adie = 1), and a/d conversion is started (adst = 1). [2] when a/d conversion is completed, the result is transferred to addrb. at the same time the adf flag is set to 1, the adst bit is cleared to 0, and the a/d converter becomes idle. [3] since adf = 1 and adie = 1, an adi interrupt is requested. [4] the a/d interrupt handling routine starts. [5] the routine reads adcsr, then writes 0 to the adf flag. [6] the routine reads and processes the connection result (addrb). [7] execution of the a/d interrupt handling routine ends. after that, if the adst bit is set to 1, a/d conversion starts again and steps [2] to [7] are repeated.
536 adie adst adf state of channel 0 (an0) a/d conversion starts 2 1 addra addrb addrc addrd state of channel 1 (an1) state of channel 2 (an2) state of channel 3 (an3) note: * vertical arrows ( ) indicate instructions executed by software. set * set * clear * clear * a/d conversion result 1 a/d conversion a/d conversion result 2 read conversion result read conversion result idle idle idle idle idle idle a/d conversion set * figure 15-3 example of a/d converter operation (single mode, channel 1 selected)
537 15.4.2 scan mode (scan = 1) scan mode is useful for monitoring analog inputs in a group of one or more channels. when the adst bit is set to 1 by a software, timer or external trigger input, a/d conversion starts on the first channel in the group (an0). when two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (an1) starts immediately. a/d conversion continues cyclically on the selected channels until the adst bit is cleared to 0. the conversion results are transferred for storage into the addr registers corresponding to the channels. when the operating mode or analog input channel must be changed during analog conversion, to prevent incorrect operation, first clear the adst bit to 0 in adcsr to halt a/d conversion. after making the necessary changes, set the adst bit to 1 to start a/d conversion again from the first channel (an0). the adst bit can be set at the same time as the operating mode or input channel is changed. typical operations when three channels (an0 to an2) are selected in scan mode are described next. figure 15-4 shows a timing diagram for this example. [1] scan mode is selected (scan = 1), scan group 0 is selected (ch2 = 0), analog input channels an0 to an2 are selected (ch1 = 1, ch0 = 0), and a/d conversion is started (adst = 1) [2] when a/d conversion of the first channel (an0) is completed, the result is transferred to addra. next, conversion of the second channel (an1) starts automatically. [3] conversion proceeds in the same way through the third channel (an2). [4] when conversion of all the selected channels (an0 to an2) is completed, the adf flag is set to 1 and conversion of the first channel (an0) starts again. if the adie bit is set to 1 at this time, an adi interrupt is requested after a/d conversion ends. [5] steps [2] to [4] are repeated as long as the adst bit remains set to 1. when the adst bit is cleared to 0, a/d conversion stops. after that, if the adst bit is set to 1, a/d conversion starts again from the first channel (an0).
538 adst adf addra addrb addrc addrd state of channel 0 (an0) state of channel 1 (an1) state of channel 2 (an2) state of channel 3 (an3) set * 1 clear * 1 idle notes: 1. vertical arrows ( ) indicate instructions executed by software. 2. data currently being converted is ignored. clear * 1 idle idle a/d conversion time idle continuous a/d conversion execution a/d conversion 1 idle idle idle idle idle transfer * 2 a/d conversion 3 a/d conversion 2 a/d conversion 5 a/d conversion 4 a/d conversion result 1 a/d conversion result 2 a/d conversion result 3 a/d conversion result 4 figure 15-4 example of a/d converter operation (scan mode, channels an0 to an2 selected)
539 15.4.3 input sampling and a/d conversion time the a/d converter has a built-in sample-and-hold circuit. the a/d converter samples the analog input at a time t d after the adst bit is set to 1, then starts conversion. figure 15-5 shows the a/d conversion timing. table 15-4 indicates the a/d conversion time. as indicated in figure 15-5, the a/d conversion time includes t d and the input sampling time. the length of t d varies depending on the timing of the write access to adcsr. the total conversion time therefore varies within the ranges indicated in table 15-4. in scan mode, the values given in table 15-4 apply to the first conversion time. the values given in table 15-5 apply to the second and subsequent conversions. (1) (2) t d t spl t conv input sampling timing adf address bus write signal legend (1) : adcsr write cycle (2) : adcsr address t d : a/d conversion start delay t spl : input sampling time t conv : a/d conversion time figure 15-5 a/d conversion timing
540 table 15-4 a/d conversion time (single mode) cks1 = 0 cks1 = 0 cks0 = 0 cks0 = 1 cks0 = 0 cks0 = 1 item symbol min typ max min typ max min typ max min typ max a/d conversion start delay t d 18 33 10 17 6 9 4 5 input sampling time t spl 127 63 31 15 a/d conversion time t conv 515 530 259 266 131 134 67 68 note: values in the table are the number of states. table 15-5 a/d conversion time (scan mode) cks1 cks0 conversion time (state) 0 0 512 (fixed) 1 256 (fixed) 1 0 128 (fixed) 1 64 (fixed) 15.4.4 external trigger input timing a/d conversion can be externally triggered. when the trgs1 and trgs0 bits are set to 11 in adcr, external trigger input is enabled at the adtrg pin. a falling edge at the adtrg pin sets the adst bit to 1 in adcsr, starting a/d conversion. other operations, in both single and scan modes, are the same as if the adst bit has been set to 1 by software. figure 15-6 shows the timing. adtrg internal trigger signal adst a/d conversion figure 15-6 external trigger input timing
541 15.5 interrupts the a/d converter generates an a/d conversion end interrupt (adi) at the end of a/d conversion. adi interrupt requests can be enabled or disabled by means of the adie bit in adcsr. the dtc can be activated by an adi interrupt. having the converted data read by the dtc in response to an adi interrupt enables continuous conversion to be achieved without imposing a load on software. the a/d converter interrupt source is shown in table 15-6. table 15-6 a/d converter interrupt source interrupt source description dtc activation adi interrupt due to end of conversion possible 15.6 usage notes the following points should be noted when using the a/d converter. setting range of analog power supply and other pins: (1) analog input voltage range the voltage applied to analog input pin ann during a/d conversion should be in the range avss ann vref. (2) relation between avcc, avss and vcc, vss as the relationship between avcc, avss and vcc, vss, set avss = vss. if the a/d converter is not used, the avcc and avss pins must on no account be left open. (3) vref input range the analog reference voltage input at the vref pin set in the range vref avcc. if conditions (1), (2), and (3) above are not met, the reliability of the device may be adversely affected. notes on board design: in board design, digital circuitry and analog circuitry should be as mutually isolated as possible, and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close proximity should be avoided as far as possible. failure to do so may result in incorrect operation of the analog circuitry due to inductance, adversely affecting a/d conversion values.
542 also, digital circuitry must be isolated from the analog input signals (an0 to an7), analog reference power supply (vref), and analog power supply (avcc) by the analog ground (avss). also, the analog ground (avss) should be connected at one point to a stable digital ground (vss) on the board. notes on noise countermeasures: a protection circuit connected to prevent damage due to an abnormal voltage such as an excessive surge at the analog input pins (an0 to an7) and analog reference power supply (vref ) should be connected between avcc and avss as shown in figure 15-7. also, the bypass capacitors connected to avcc and vref and the filter capacitor connected to an0 to an7 must be connected to avss. if a filter capacitor is connected as shown in figure 15-7, the input currents at the analog input pins (an0 to an7) are averaged, and so an error may arise. also, when a/d conversion is performed frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the a/d converter exceeds the current input via the input impedance (r in ), an error will arise in the analog input pin voltage. careful consideration is therefore required when deciding the circuit constants. avcc * 1 * 1 vref an0 to an7 avss notes: values are reference values. 1. 2. r in : input impedance r in * 2 100 0.1 f 0.01 f 10 f figure 15-7 example of analog input protection circuit
543 table 15-7 analog pin specifications item min max unit analog input capacitance 20 pf permissible signal source impedance 5 * k w note: * when v cc = 2.7 v to 3.6 v 20 pf to a/d converter an0 to an7 10 k note: values are reference values. figure 15-8 analog input pin equivalent circuit a/d conversion precision definitions: h8s/2237 series and h8s/2227 series a/d conversion precision definitions are given below. resolution the number of a/d converter digital output codes offset error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from the minimum voltage value b'0000000000 (h'000) to b'0000000001 (h'001) (see figure 15-10). full-scale error the deviation of the analog input voltage value from the ideal a/d conversion characteristic when the digital output changes from b'1111111110 (h'3fe) to b'1111111111 (h'3ff) (see figure 15-10). quantization error the deviation inherent in the a/d converter, given by 1/2 lsb (see figure 15-9). nonlinearity error the error with respect to the ideal a/d conversion characteristic between the zero voltage and the full-scale voltage. does not include the offset error, full-scale error, or quantization error. absolute precision the deviation between the digital value and the analog input value. includes the offset error, full-scale error, quantization error, and nonlinearity error.
544 111 110 101 100 011 010 001 000 fs quantization error digital output ideal a/d conversion characteristic analog input voltage 1 1024 2 1024 1022 1024 1023 1024 figure 15-9 a/d conversion precision definitions (1)
545 fs offset error nonlinearity error actual a/d conversion characteristic analog input voltage digital output ideal a/d conversion characteristic full-scale error figure 15-10 a/d conversion precision definitions (2) permissible signal source impedance: h8s/2237 series and h8s/2227 series analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 k w or less. this specification is provided to enable the a/d converter? sample- and-hold circuit input capacitance to be charged within the sampling time; if the sensor output impedance exceeds 5 k w , charging may be insufficient and it may not be possible to guarantee the a/d conversion precision. however, if a large capacitance is provided externally, the input load will essentially comprise only the internal input resistance of 10 k w , and the signal source impedance is ignored. however, since a low-pass filter effect is obtained in this case, it may not be possible to follow an analog signal with a large differential coefficient (e.g., 5 mv/ m s or greater). when converting a high-speed analog signal, a low-impedance buffer should be inserted.
546 influences on absolute precision: adding capacitance results in coupling with gnd, and therefore noise in gnd may adversely affect absolute precision. be sure to make the connection to an electrically stable gnd such as av ss . care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. a/d converter equivalent circuit h8s/2237 series and h8s/2227 series 20 pf c in = 15 pf 10 k to 5 k low-pass filter c to 0.1 f sensor output impedance sensor input note: values are reference values. figure 15-11 example of analog input circuit
547 section 16 d/a converter provided in the h8s/2237 series. not provided in the h8s/2227 series. 16.1 overview the h8s/2237 series includes a two-channel d/a converter. 16.1.1 features d/a converter features are listed below 8-bit resolution two output channels maximum conversion time of 10 m s (with 20 pf load) output voltage of 0 v to v ref d/a output hold function in software standby mode module stop mode can be set ? as the initial setting, d/a converter operation is halted. register access is enabled by exiting module stop mode.
548 16.1.2 block diagram figure 16-1 shows a block diagram of the d/a converter. module data bus internal data bus vref avcc da1 da0 avss 8-bit d/a control circuit dadr0 bus interface dadr1 dacr figure 16-1 block diagram of d/a converter
549 16.1.3 pin configuration table 16-1 summarizes the input and output pins of the d/a converter. table 16-1 pin configuration pin name symbol i/o function analog power pin avcc input analog power source analog ground pin avss input analog ground and reference voltage analog output pin 0 da0 output channel 0 analog output analog output pin 1 da1 output channel 1 analog output reference voltage pin vref input analog reference voltage 16.1.4 register configuration table 16-2 summarizes the registers of the d/a converter. table 16-2 d/a converter registers name abbreviation r/w initial value address * d/a data register 0 dadr0 r/w h'00 h'fdac d/a data register 1 dadr1 r/w h'00 h'fdad d/a control register dacr r/w h'1f h'fdae module stop control register c mstpcrc r/w h'ff h'fdea note: * lower 16 bits of the address. 16.2 register descriptions 16.2.1 d/a data registers 0 and 1 (dadr0, dadr1) 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : d/a data registers 0 and 1 (dadr0 and dadr1) are 8-bit readable/writable registers that store data for conversion.
550 whenever output is enabled, the value in the d/a data register is converted and output from the analog output pin. dadr0 and dadr1 are each initialized to h'00 by a reset and in hardware standby mode. 16.2.2 d/a control register (dacr) 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 1 3 1 0 1 2 1 1 1 bit initial value r/w : : : dacr is an 8-bit readable/writable register that controls the operation of the d/a converter. dacr is initialized to h'1f by a reset and in hardware standby mode. bit 7?/a output enable 1 (daoe1): controls d/a conversion and analog output. bit 7 daoe1 description 0 analog output da1 is disabled (initial value) 1 channel 1 d/a conversion is enabled; analog output da1 is enabled bit 6?/a output enable 0 (daoe0): controls d/a conversion and analog output. bit 6 daoe0 description 0 analog output da0 is disabled (initial value) 1 channel 0 d/a conversion is enabled; analog output da0 is enabled bit 5?/a enable (dae): the daoe0 and daoe1 bits both control d/a conversion. when the dae bit is cleared to 0, the channel 0 and 1 d/a conversions are controlled independently. when the dae bit is set to 1, the channel 0 and 1 d/a conversions are controlled together. output of resultant conversions is always controlled independently by the daoe0 and daoe1 bits.
551 bit 7 bit 6 bit 5 daoe1 daoe0 dae description 00 * channel 0 and 1 d/a conversions disabled 1 0 channel 0 d/a conversion enabled channel 1 d/a conversion disabled 1 channel 0 and 1 d/a conversions enabled 1 0 0 channel 0 d/a conversion disabled channel 1 d/a conversion enabled 1 channel 0 and 1 d/a conversions enabled 1 * channel 0 and 1 d/a conversions enabled * : don? care if the h8s/2237 series enters software standby mode when d/a conversion is enabled, the d/a output is held and the analog power current is the same as during d/a conversion. when it is necessary to reduce the analog power current in software standby mode, clear the daoe0, daoe1, and dae bits to 0 to disable d/a output. bits 4 to 0?eserved: read-only bits, always read as 1. 16.2.3 module stop control register c (mstpcrc) 7 mstpc7 1 r/w 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 0 mstpc0 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w bit initial value r/w : : : mstpcrc is a 8-bit readable/writable register that performs module stop mode control. when the mstpc5 bit in mstpcr is set to 1, d/a converter operation stops at the end of the bus cycle and a transition is made to module stop mode. registers cannot be read or written to in module stop mode. for details, see section 20.5, module stop mode. mstpcr is initialized to h'ff by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 5?odule stop (mstpc5): specifies the d/a converter module stop mode.
552 bit 5 mstpc5 description 0 d/a converter module stop mode cleared 1 d/a converter module stop mode set (initial value) 16.3 operation the d/a converter includes d/a conversion circuits for two channels, each of which can operate independently. d/a conversion is performed continuously while enabled by dacr. if either dadr0 or dadr1 is written to, the new data is immediately converted. the conversion result is output by setting the corresponding daoe0 or daoe1 bit to 1. the operation example described in this section concerns d/a conversion on channel 0. figure 16-2 shows the timing of this operation. [1] write the conversion data to dadr0. [2] set the daoe0 bit in dacr to 1. d/a conversion is started and the da0 pin becomes an output pin. the conversion result is output after the conversion time has elapsed. the output value is expressed by the following formula: dadr contents 256 v ref the conversion results are output continuously until dadr0 is written to again or the daoe0 bit is cleared to 0. [3] if dadr0 is written to again, the new data is immediately converted. the new conversion result is output after the conversion time has elapsed. [4] if the daoe0 bit is cleared to 0, the da0 pin becomes an input pin.
553 conversion data 1 conversion result 1 high-impedance state t dconv dadr0 write cycle da0 daoe0 dadr0 address dacr write cycle conversion data 2 conversion result 2 t dconv legend t dconv : d/a conversion time dadr0 write cycle dacr write cycle figure 16-2 example of d/a converter operation
554
555 section 17 ram 17.1 overview the h8s/2237 and h8s/2227 have 16 kbytes of on-chip high-speed static ram, and the h8s/2235, h8s/2233, h8s/2225, and h8s/2223 have 4 kbytes. the ram is connected to the cpu by a 16-bit data bus, enabling one-state access by the cpu to both byte data and word data. this makes it possible to perform fast word data transfer. the on-chip ram can be enabled or disabled by means of the ram enable bit (rame) in the system control register (syscr). 17.1.1 block diagram figure 17-1 shows a block diagram of the on-chip ram. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'ffb000 h'ffb002 h'ffb004 h'ffffc0 h'ffb001 h'ffb003 h'ffb005 h'ffffc1 h'fffffe h'ffffff h'ffefbe h'ffefbf figure 17-1 block diagram of ram (h8s/2237)
556 17.1.2 register configuration the on-chip ram is controlled by syscr. table 17-1 shows the address and initial value of syscr. table 17-1 ram register name abbreviation r/w initial value address * system control register syscr r/w h'01 h'fde5 note: * lower 16 bits of the address. 17.2 register descriptions 17.2.1 system control register (syscr) 7 0 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 0 bit initial value r/w : : : the on-chip ram is enabled or disabled by the rame bit in syscr. for details of other bits in syscr, see section 3.2.2, system control register (syscr). bit 0?am enable (rame): enables or disables the on-chip ram. the rame bit is initialized when the reset state is released. it is not initialized in software standby mode. bit 0 rame description 0 on-chip ram is disabled 1 on-chip ram is enabled (initial value)
557 17.3 operation when the rame bit is set to 1, accesses to addresses h'ffb000 to h'ffefbf and h'ffffc0 to h'ffffff in the h8s/2237 and h8s/2227, and to addresses h'ffe000 to h'ffefbf and h'ffffc0 to h'ffffff in the h8s/2235, h8s/2233, h8s/2225, and h8s/2223, are directed to the on-chip ram. when the rame bit is cleared to 0, the off-chip address space is accessed. since the on-chip ram is connected to the cpu by an internal 16-bit data bus, it can be written to and read in byte or word units. each type of access can be performed in one state. even addresses use the upper 8 bits, and odd addresses use the lower 8 bits. word data must start at an even address. 17.4 usage note dtc register information can be located in addresses h'ffebc0 to h'ffefbf. when the dtc is used, the rame bit must not be cleared to 0.
558
559 section 18 rom 18.1 overview the h8s/2237, h8s/2235, h8s/2227, and h8s/2225 have 128 kbytes of on chip rom (prom or mask rom), and the h8s/2233 and h8s/2223 have 64 kbytes. the cpu accesses both byte data and word data in one state, making possible rapid instruction fetches and high-speed processing. the on-chip rom is enabled or disabled by setting the mode pins (md2, md1, and md0). the prom version of the h8s/2237 series can be programmed with a general-purpose prom programmer, by setting prom mode. 18.1.1 block diagram figure 18-1 shows a block diagram of the on-chip rom. internal data bus (upper 8 bits) internal data bus (lower 8 bits) h'000000 h'000002 h'000001 h'000003 h'01fffe h'01ffff figure 18-1 block diagram of rom (h8s/2237, h8s/2235, h8s/2227, h8s/2225)
560 18.2 operation the on-chip rom is connected to the cpu by a 16-bit data bus, and both byte and word data can be accessed in one state. even addresses are connected to the upper 8 bits, and odd addresses to the lower 8 bits. word data must start at an even address. the on-chip rom is enabled and disabled by setting the mode pins (md2, md1, and md0). these settings are shown in table 18-1. table 18-1 operating modes and rom area mode pin operating mode md2 md1 md0 on-chip rom mode 1 * 1 001 mode 2 * 1 10 mode 3 * 1 1 mode 4 advanced expanded mode with on-chip rom disabled 1 0 0 disabled mode 5 advanced expanded mode with on-chip rom disabled 1 mode 6 advanced expanded mode with on-chip rom enabled 1 0 enabled (128 kbytes) * 2 mode 7 advanced single-chip mode 1 enabled (128 kbytes) * 2 notes: 1. not available in the h8s/2237 series and h8s/2227 series. 2. 128 kbytes in the h8s/2237, h8s/2235, h8s/2227, and h8s/2225; 64 kbytes in the h8s/2233 and h8s/2223.
561 18.3 prom mode 18.3.1 prom mode setting the prom version of the h8s/2237 series suspends its microcontroller functions when placed in prom mode, enabling the on-chip prom to be programmed. this programming can be done with a prom programmer set up in the same way as for the hn27c101 (v pp = 12.5 v). use of a socket adapter to convert from 100 pins to 32 pins enables programming with a commercial prom programmer. caution is required when selecting the prom programmer, as the h8s/2237 series does not support page mode. table 18-2 shows how prom mode is selected. table 18-2 selecting prom mode pin names setting md2, md1, md0 low stby pa2, pa1 high 18.3.2 socket adapter and memory map programs can be written and verified by attaching a socket adapter to convert from 100 pins to 32 pins to the prom programmer. table 18-3 gives ordering information for the socket adapter, and figure 18-2 shows the wiring of the socket adapter. figure 18-3 shows the memory map in prom mode.
562 pin res pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pb0 nmi pb2 pb3 pb4 pb5 pb6 pb7 pa0 pf2 pb1 pf1 vcc avcc vref pa1 pa2 vss avss stby md0 md1 md2 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 16 pin vpp eo0 eo1 eo2 eo3 eo4 eo5 eo6 eo7 ea0 ea1 ea2 ea3 ea4 ea5 ea6 ea7 ea8 ea9 ea10 ea11 ea12 ea13 ea14 ea15 ea16 ce oe pgm v cc v ss hd6472237 (fp-100b, tfp-100b, tfp-100g) eprom socket note: pins not shown in this figure should be left open. vpp eo7 to eo0 ea16 to ea0 oe ce pgm : programming power supply (12.5 v) : data input/output : address input : output enable : chip enable : program pin no. 59 4 5 6 7 8 9 10 11 13 15 16 17 18 19 20 21 22 60 24 25 26 27 28 29 30 73 23 74 12, 62 54 53 31 32 14, 64 42 61 55 56 67 dip-32 pin no. figure 18-2 hd6472237 socket adapter pin correspondence diagram (fp-100b, tfp-100b, tfp-100g)
563 pin res pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pb0 nmi pb2 pb3 pb4 pb5 pb6 pb7 pa0 pf2 pb1 pf1 vcc avcc vref pa1 pa2 vss avss stby md0 md1 md2 1 13 14 15 17 18 19 20 21 12 11 10 9 8 7 6 5 27 26 23 25 4 28 29 3 2 22 24 31 32 16 pin vpp eo0 eo1 eo2 eo3 eo4 eo5 eo6 eo7 ea0 ea1 ea2 ea3 ea4 ea5 ea6 ea7 ea8 ea9 ea10 ea11 ea12 ea13 ea14 ea15 ea16 ce oe pgm v cc v ss hd6472237 (fp-100a) eprom socket note: pins not shown in this figure should be left open. vpp: programming power supply (12.5 v) eo7 to eo0: data input/output ea16 to ea0: address input oe: output enable ce: chip enable pgm: program pin no. 62 7 8 9 10 11 12 13 14 16 18 19 20 21 22 23 24 25 63 27 28 29 30 31 32 33 76 26 77 15, 65 57 56 34 35 17, 67 45 64 58 59 70 hn27c101 (dip-32) pin no. figure 18-3 hd6472237 socket adapter pin correspondence diagram (fp-100a)
564 table 18-3 socket adapters microcontroller package minato electronics data io japan h8s/2237 100-pin tqfp (tfp-100b) me2237esns1h h7223bt100d3201 100-pin tqfp (tfp-100g) me2237esms1h h7223gt100d3201 100-pin qfp (fp-100a) me2237esfs1h h7223aq100d3201 100-pin qfp (fp-100b) me2237eshs1h h7223bq100d3201 on-chip prom addresses in mcu mode addresses in prom mode h'000000 h'01ffff h'00000 h'1ffff figure 18-4 memory map in prom mode
565 18.4 programming 18.4.1 overview table 18-4 shows how to select the program, verify, and program-inhibit modes in prom mode. table 18-4 mode selection in prom mode pins mode ce oe pgm v pp v cc eo7 to eo0 ea16 to ea0 program l h l v pp v cc data input address input verify l l h v pp v cc data output address input program-inhibit lllv pp v cc high impedance address input lhh hl l hhh legend l : low voltage level h : high voltage level v pp : v pp voltage level v cc : v cc voltage level programming and verification should be carried out using the same specifications as for the standard hn27c101. however, do not set the prom programmer to page mode does not support page programming. a prom programmer that only supports page programming cannot be used. when choosing a prom programmer, check that it supports high-speed programming in byte units. always set addresses within the range h'00000 to h'1ffff. 18.4.2 programming and verification an efficient, high-speed programming procedure can be used to program and verify prom data. this procedure writes data quickly without subjecting the chip to voltage stress or sacrificing data reliability. it leaves the data h'ff in unused addresses. figure 18-5 shows the basic high-speed programming flowchart. tables 18-5 and 18-6 list the electrical characteristics of the chip during programming. figure 18-6 shows a timing chart.
566 start set programming/ verification mode v cc = 6.0v 0.25v, v pp = 12.5v 0.3v address = 0 verification ok? yes no n = 0 n + 1 ? n program with t pw = 0.2 ms 5% program with t opw = 0.2n ms last address? set read mode v cc = 5.0 v 0.25 v v pp = v cc all addresses read? yes no no yes go address + 1 ? address n<25 end fail no go figure 18-5 high-speed programming flowchart
567 table 18-5 dc characteristics in prom mode (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, v ss = 0 v, t a = 25 c 5 c) item symbol min typ max unit test conditions input high voltage eo7 to eo0, ea16 to ea0, oe , ce , pgm v ih 2.4 v cc + 0.3 v input low voltage eo7 to eo0, ea16 to ea0, oe , ce , pgm v il ?.3 0.8 v output high voltage eo7 to eo0 v oh 2.4 v i oh = ?00 m a output low voltage eo7 to eo0 v ol 0.45 v i ol = 1.6 ma input leakage current eo7 to eo0, ea16 to ea0, oe , ce , pgm | i li | 2 m av in = 5.25 v/0.5 v v cc current i cc 40 ma v pp current i pp 40 ma
568 table 18-6 ac characteristics in prom mode (when v cc = 6.0 v 0.25 v, v pp = 12.5 v 0.3 v, t a = 25 c 5 c) item symbol min typ max unit test conditions address setup time t as 2 m s figure 18-6 * 1 oe setup time t oes 2 m s data setup time t ds 2 m s address hold time t ah 0 m s data hold time t dh 2 m s data output disable time t df * 2 130 ns v pp setup time t vps 2 m s programming pulse width t pw 0.19 0.20 0.21 ms pgm pulse width for overwrite programming t opw * 3 0.19 5.25 ms v cc setup time t vcs 2 m s ce setup time t ces 2 m s data output delay time t oe 0 150 ns notes: 1. input pulse level: 0.8 v to 2.2 v input rise time and fall time 20 ns timing reference levels: input: 1.0 v, 2.0 v output: 0.8 v, 2.0 v 2. t df is defined to be when output has reached the open state, and the output level can no longer be referenced. 3. t opw is defined by the value shown in the flowchart.
569 program verify input data output data t as t ah t df t dh t ds t vps t vcs t ces t pw t opw * t oes t oe address data v pp v cc ce pgm oe v pp v cc v cc +1 v cc note: * t opw is defined by the value shown in the flowchart. figure 18-6 prom programming/verification timing
570 18.4.3 programming precautions program using the specified voltages and timing. the programming voltage (v pp ) in prom mode is 12.5 v. applied voltages in excess of the specified values can permanently destroy the mcu. be particularly careful about the prom programmer? overshoot characteristics. if the prom programmer is set to hitachi hn27c101 specifications, v pp will be 12.5 v. before programming, check that the mcu is correctly mounted in the prom programmer. overcurrent damage to the mcu can result if the index marks on the prom programmer, socket adapter, and mcu are not correctly aligned. do not touch the socket adapter or mcu while programming. touching either of these can cause contact faults and programming errors. the mcu cannot be programmed in page programming mode. select the programming mode carefully. the size of the prom is 128 kbytes. always set addresses within the range h'00000 to h'1ffff. during programming, write h'ff to unused addresses to avoid verification errors.
571 18.4.4 reliability of programmed data an effective way to assure the data retention characteristics of the programmed chips is to bake them at 150 c, then screen them for data errors. this procedure quickly eliminates chips with prom memory cells prone to early failure. figure 18-7 shows the recommended screening procedure. mount program chip and verify data bake chip for 24 to 48 hours at 125 c to 150 c with power off read and check program figure 18-7 recommended screening procedure if a series of programming errors occurs while the same prom programmer is being used, stop programming and check the prom programmer and socket adapter for defects. please inform hitachi of any abnormal conditions noted during or after programming or in screening of program data after high-temperature baking.
572
573 section 19 clock pulse generator 19.1 overview the h8s/2237 series and h8s/2227 series have a built-in clock pulse generator (cpg) that generates the system clock (?, the bus master clock, and internal clocks. the clock pulse generator consists of a system clock oscillator, duty adjustment circuit, clock selection circuit, medium-speed clock divider, bus master clock selection circuit, subclock oscillator, and waveform shaping circuit. 19.1.1 block diagram figure 19-1 shows a block diagram of the clock pulse generator. osc1 osc2 legend: lpwrcr: sckcr: low-power control register system clock control register extal xtal waveform shaping circuit subclock oscillator duty adjustment circuit medium- speed clock divider system clock oscillator clock selection circuit ?sub wdt1 count clock system clock to ?pin internal clock to supporting modules bus master clock to cpu and dtc ?2 to ?32 sck2 to sck0 sckcr rfcut lpwrcr bus master clock selection circuit figure 19-1 block diagram of clock pulse generator
574 19.1.2 register configuration the clock pulse generator is controlled by sckcr and lpwrcr. table 19-1 shows the register configuration. table 19-1 clock pulse generator register name abbreviation r/w initial value address * system clock control register sckcr r/w h'00 h'fde6 low-power control register lpwrcr r/w h'00 h'fdec note: * lower 16 bits of the address. 19.2 register descriptions 19.2.1 system clock control register (sckcr) 7 pstop 0 r/w 6 0 r/w 5 0 4 0 3 0 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : sckcr is an 8-bit readable/writable register that performs ?clock output control and medium- speed mode control. sckcr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock output disable (pstop): controls ?output. description bit 7 sleep mode, hardware pstop subsleep mode standby mode 0 output (initial value) ?output fixed high high impedance 1 fixed high fixed high fixed high high impedance bit 6?eserved: this bit can be read or written to, but only 0 should be written. bits 5 to 3?eserved: read-only bits, always read as 0. software standby mode, watch mode, direct transition high-speed mode, medium-speed mode, subactive mode
575 bits 2 to 0?ystem clock select 2 to 0 (sck2 to sck0): these bits select the bus master clock used in high-speed mode and medium-speed mode. when operating the chip in subactive mode, bits sck2 to sck0 should all be cleared to 0. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master is in high-speed mode (initial value) 1 medium-speed clock is ?2 1 0 medium-speed clock is ?4 1 medium-speed clock is ?8 1 0 0 medium-speed clock is ?16 1 medium-speed clock is ?32 1 19.2.2 low-power control register (lpwrcr) 7 dton 0 r/w 6 lson 0 r/w 5 nesel 0 r/w 4 substp 0 r/w 3 rfcut 0 r/w 0 stc0 0 r/w 2 0 r/w 1 stc1 0 r/w bit initial value read/write lpwrcr is an 8-bit readable/writable register that performs power-down mode control. lpwrcr is initialized to h'00 by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. bit 7?irect-transfer on flag (dton): specifies whether a direct transition is made between high-speed mode or medium-speed mode and subactive mode when making a power-down transition by executing a sleep instruction. the operating mode to which the transition is made after sleep instruction execution is determined by a combination of other control bits.
576 bit 7 dton description 0 when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode (initial value) 1 when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode * , or a transition is made to sleep mode or sofware standby mode when a sleep instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode note: * in the case of a transition to watch mode or subactive mode, high-speed mode must be set. bit 6?ow-speed on flag (lson): determines the operating mode in combination with other control bits when making a power-down transition by executing a sleep instruction. also controls whether a transition is made to high-speed mode or medium-speed mode, or to subactive mode, when watch mode is cleared. bit 6 lson description 0 when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode when a sleep instruction is executed in subactive mode, a transition is made to watch mode * , or directly to high-speed mode after watch mode is cleared, a transition is made to high-speed mode (initial value) 1 when a sleep instruction is executed in high-speed mode, a transition is made to watch mode or subactive mode when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode after watch mode is cleared, a transition is made to subactive mode note: * in the case of a transition to watch mode or subactive mode, high-speed mode must be set.
577 bit 5?oise elimination sampling frequency select (nesel): selects the frequency at which the subclock (?ub) generated by the subclock oscillator is sampled with the clock (? generated by the system clock oscillator. when ?= 5 mhz or higher, this bit should be cleared to 0. bit 5 nesel description 0 sampling at ?divided by 32 (initial value) 1 sampling at ?divided by 4 bit 4?ubclock oscillator control (substp): controls operation and stopping of the subclock oscillator. bit 4 substp description 0 subclock oscillator operates (initial value) 1 subclock oscillator is stopped bit 3?uilt-in feedback resistor control (rfcut): selects whether the oscillator? built-in feedback resistor and duty adjustment circuit are used with external clock input. do not access this bit when a crystal oscillator is used. after this bit is set when using external clock input, a transition should intially be made to software standby mode, watch mode, or subactive mode. switching between use and non-use of the oscillator? built-in feedback resistor and duty adjustment circuit is performed when the transition is made to software standby mode, watch mode, or subactive mode. bit 3 rfcut description 0 system clock oscillator? built-in feedback resistor and duty adjustment circuit are used (initial value) 1 system clock oscillator? built-in feedback resistor and duty adjustment circuit are not used bit 2?eserved: this bit can be read or written to, but should only be written with 0.
578 bits 1 and 0?requency multiplication factor (stc1, stc0): the stc bits specify the frequency multiplication factor of the pll circuit incorporated into the evaluation chip. the specified frequency multiplication factor is valid after a transition to software standby mode, watch mode, or subactive mode. with the h8s/2237 series and h8s/2227 series, stc1 and stc0 must both be set to 1. after a reset, stc1 and stc0 are both cleared to 0, and so must be set to 1. bit 1 bit 0 stc1 stc0 description 0 0 x1 (initial value) 1 x2 (setting prohibited) 1 0 x4 (setting prohibited) 1 pll is bypassed
579 19.3 system clock oscillator clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock. 19.3.1 connecting a crystal resonator circuit configuration: a crystal resonator can be connected as shown in the example in figure 19-2. select the damping resistance r d according to table 19-2. an at-cut parallel-resonance crystal should be used. extal xtal r d c l2 c l1 c l1 = c l2 = 10 to 22pf figure 19-2 connection of crystal resonator (example) table 19-2 damping resistance value frequency (mhz) 246810 r d ( w ) 1k 500 300 200 100 crystal resonator: figure 19-3 shows the equivalent circuit of the crystal resonator. use a crystal resonator that has the characteristics shown in table 19-3 and the same resonance frequency as the system clock (?. xtal c l at-cut parallel-resonance type extal c 0 lr s figure 19-3 crystal resonator equivalent circuit
580 table 19-3 crystal resonator parameters frequency (mhz) 246810 r s max ( w ) 500 120 100 80 60 c 0 max (pf) 77777 note on board design: when a crystal resonator is connected, the following points should be noted: other signal lines should be routed away from the oscillator circuit to prevent induction from interfering with correct oscillation. see figure 19-4. when designing the board, place the crystal resonator and its load capacitors as close as possible to the xtal and extal pins. c l2 signal a signal b c l1 h8s/2237 xtal extal avoid figure 19-4 example of incorrect board design
581 19.3.2 external clock input circuit configuration: an external clock signal can be input as shown in the examples in figure 19-5. if the xtal pin is left open, make sure that stray capacitance is no more than 10 pf. in example (b), make sure that the external clock is held high in standby mode, subactive mode, subsleep mode, and watch mode. extal xtal external clock input open (a) xtal pin left open extal xtal external clock input ( b ) com p lementar y clock in p ut at xtal p in figure 19-5 external clock input (examples) external clock: the external clock signal should have the same frequency as the system clock (?. table 19-4 and figure 19-6 show the input conditions for the external clock.
582 table 19-4 external clock input conditions ztat version mask rom version v cc = 2.7 v to 3.6 v v cc = 2.7 v to 3.6 v v cc = 2.2 v to 3.6 v test item symbolmin max min max min max unit conditions external clock input low pulse width t exl 40 30 tbd ns figure 19-6 external clock input high pulse width t exh 40 30 tbd ns external clock rise time t exr 10 7 tbd ns external clock fall time t exf 10 7 tbd ns clock low pulse width level t cl 0.4 0.6 0.4 0.6 tbd tbd t cyc ? 3 5 mhz figure 21-3 80 80 tbd ns < 5 mhz clock high pulse width level t ch 0.4 0.6 0.4 0.6 tbd tbd t cyc ? 3 5 mhz 80 80 tbd ns < 5 mhz the external clock input conditions when the duty adjustment circuit is not used are shown in table 19-5 and figure 19-6. when the duty adjustment circuit is not used, the ?output waveform depends on the external clock input waveform, and so no restrictions apply. table 19-5 external clock input conditions when the duty adjustment circuit is not used ztat version mask rom version v cc = 2.7 to 3.6 v v cc = 2.7 to 3.6 v v cc = 2.2 to 3.6 v test item symbol min max min max min max unit conditions external clock input low pulse width t exl 50 37 tbd ns figure 19-6 external clock input high pulse width t exh 50 37 tbd ns external clock rise time t exr 10 7 tbd ns external clock fall time t exf 10 7 tbd ns note: when duty adjustment circuit is not used, the maximum frequency decreases according to the input waveform. (example: when t exl = t exh = 50 ns, and t exr = t exf = 10 ns, clock cycle time = 120 ns; therefore, maximum operating frequency = 8.3 mhz)
583 t exh t exl t exr t exf v cc 0.5 extal figure 19-6 external clock input timing (3) note on switchover of external clock when two or more external clocks (e.g. 10 mhz and 2 mhz) are used as the system clock, switchover of the input clock should be carried out in software standby mode. an example of an external clock switching circuit is shown in figure 19-7, and an example of the external clock switchover timing in figure 19-8. external clock 1 external clock 2 external clock switchover request external interrupt signal external clock switchover signal control circuit h8s/2237 port output external interrupt extal selector figure 19-7 example of external clock switching circuit
584 200 ns or more (2) (1) (2) (3) (4) ( 5 ) port setting (clock switchover) software standby mode transition external clock switchover external interrupt generation (input interrupt at least 200 ns after transition to software standby mode.) interrupt exception handlin g (5) sleep instruction execution interrupt exception handling operation external clock 1 external clock 2 (1) port setting (3) external clock switchover signal extal internal clock (4) wait time external interrupt active (external clock 2) software standby mode active (external clock 1) clock switchover request figure 19-8 example of external clock switchover timing
585 19.4 duty adjustment circuit when the oscillator frequency is 5 mhz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (?. 19.5 medium-speed clock divider the medium-speed clock divider divides the system clock to generate ?2, ?4, ?8, ?16, and ?32. 19.6 bus master clock selection circuit the bus master clock selection circuit selects the system clock (? or one of the medium-speed clocks (?2, ?4, or ?8, ?16, and ?32) to be supplied to the bus master, according to the settings of the sck2 to sck0 bits in sckcr. 19.7 subclock oscillator (1) method of connecting 32.768 khz crystal resonator to supply a clock to the subclock oscillator, a 32.768 khz crystal resonator should be connected as shown in figure 19-9. cautions concerning the connection are as noted in section 19.3 (3), notes on board design. osc1 osc2 c 1 c 2 c 1 = c 2 = 15pf (typ) figure 19-9 example of connection of 32.768 khz crystal resonator figure 19-10 shows an equivalent circuit for the 32.768 khz crystal resonator.
586 osc1 c l l s =1.5 pf (typ.) =14 k (typ.) =32.768 khz model = mx38t (nippon denpa kogyo) osc2 c 0 c 0 r s f w r s figure 19-10 32.768 khz crystal resonator equivalent circuit (2) pin handling when subclock is not needed when the subclock is not needed, connect the osc1 pin to vcc and leave the osc2 pin open as shown in figure 19-11. osc1 osc2 v cc open figure 19-11 pin handling when subclock is not needed
587 19.8 subclock waveform shaping circuit to eliminate noise in the subclock input from the osc1 pin, the signal is sampled using a clock scaled from the ?clock. the sampling frequency is set with the nesel bit in lpwrcr. for details, see section 19.2.2, low-power control register (lpwrcr). sampling is not performed in subactive mode, subsleep mode, or watch mode. 19.9 note on crystal resonator since various characteristics related to the crystal resonator are closely linked to the user? board design, thorough evaluation is necessary on the user? part, for both the mask versions, and ztat versions, using the resonator connection examples shown in this section as a guide. as the resonator circuit ratings will depend on the floating capacitance of the resonator and the mounting circuit, the ratings should be determined in consultation with the resonator manufacturer. the design must ensure that a voltage exceeding the maximum rating is not applied to the oscillator pin.
588
589 section 20 power-down modes 20.1 overview in addition to the normal program execution state, the h8s/2237 series and h8s/2227 series have power-down modes in which operation of the cpu and oscillator is halted and power dissipation is reduced. low-power operation can be achieved by individually controlling the cpu, on-chip supporting modules, and so on. the h8s/2237 series and h8s/2227 series operating modes are as follows: (1) high-speed mode (2) medium-speed mode (3) subactive mode (4) sleep mode (5) subsleep mode (6) watch mode (7) module stop mode (8) software standby mode (9) hardware standby mode of these, (2) to (9) are power-down modes. sleep mode and subsleep mode are cpu modes, medium-speed mode is a cpu and bus master mode, subactive mode is a cpu, bus master, and on-chip supporting module mode, and module stop mode is an on-chip supporting module mode (including bus masters other than the cpu). certain combinations of these modes can be set. after a reset, the mcu is in high-speed mode. table 20.1 shows the internal chip states in each mode, and table 20.2 shows the conditions for transition to the various modes. figure 20.1 shows a mode transition diagram.
590 table 20.1 h8s/2237 series and h8s/2227 series internal states in each mode function high- speed medium- speed sleep module stop watch subactive subsleep software standby hardware standby system clock oscillator function- ing function- ing function- ing function- ing halted halted halted halted halted subclock oscillator function- ing function- ing function- ing function- ing function- ing function- ing function- ing function- ing/halted halted cpu operation instruc- tions function- ing medium- speed halted function- ing halted subclock operation halted halted halted registers retained retained retained retained undefined ram function- ing function- ing function- ing (dtc) function- ing retained function- ing retained retained retained i/o function- ing function- ing function- ing function- ing retained function- ing function- ing retained high impedance external interrupts function- ing function- ing function- ing function- ing function- ing function- ing function- ing function- ing halted on-chip supporting module pbc function- ing medium- speed function- ing function- ing/halted (retained) halted (retained) subclock operation halted (retained) halted (retained) halted (reset) operation dtc halted (retained) wdt1 function- ing function- ing subclock operation subclock operation subclock operation wdt0 halted tmr0, 1 functio- ing/halted (retained) tpu (retained) halted halted sci (retained) (retained) d/a a/d function- ing/halted (reset) halted (reset) halted (reset) halted (reset) halted (reset) note: ?alted (retained)?means that internal register values are retained. the internal state is operation suspended. ?alted (reset)?means that internal register values and internal states are initialized. in module stop mode, only modules for which a stop setting has been made are halted (reset or retained). : operating state
591 hardware standby mode stby pin = low notes: when a transition is made between modes by means of an interrupt, transition cannot be made on interrupt source generation alone. ensure that interrupt handling is performed after accepting the interrupt request. from any state except hardware standby mode, a transition to the power-on reset state occurs whenever res goes low. from any state except hardware standby mode and the power-on reset state, a transition to the manual reset state occurs whenever mres goes low. from any state, a transition to hardware standby mode occurs when stby goes low. when a transition is made to watch mode or subactive mode, high-speed mode must be set. sleep mode (main clock) ssby = 0, lson = 0 software standby mode ssby = 1 pss = 0, lson = 0 watch mode (subclock) ssby = 1 pss = 1, dton = 0 subsleep mode (subclock) ssby = 0 pss = 1, lson = 1 medium-speed mode (main clock) subactive mode (subclock) high-speed mode (main clock) power-on reset state manual reset state stby pin = high res pin = low res pin = high mres = high program execution state reset state sleep instruction ssby = 1, pss = 1, dton = 1, lson = 0 clock switching exception handling after oscillation stabilization time (sts2 to sts0) sleep instruction ssby = 1, pss = 1, dton = 1, lson = 1 clock switching exception handling sck2 to sck0 1 0 sck2 to sck0 = 0 program-halted state sleep instruction all interrupt * 3 sleep instruction external interrupt * 4 sleep instruction interrupt * 1 , lson bit = 0 sleep instruction interrupt * 1 , lson bit = 1 interrupt * 2 sleep instruction : transition after exception handling : power-down mode * 1 nmi, irq0 to irq7, and wdt1 interrupts * 2 nmi, irq0 to irq7, wdt0 interrupts, wdt1 interrupt, tmr0 interrupt, and tmr1 interrupt * 3 all interrupts * 4 nmi, irq0 to irq7 figure 20.1 mode transitions
592 table 20.2 power-down mode transition conditions control bit states at time of transition state before transition ssby pss lson dton state after transition by sleep instruction state after return by interrupt high-speed/ medium-speed 0 * 0 * sleep high-speed/ medium-speed 0 * 1 * 100 * software standby high-speed/ medium-speed 101 * 1100 watch high-speed 1110 watch subactive 1101 1111 subactive subactive 0 0 ** 010 * 011 * subsleep subactive 10 ** 1100 watch high-speed 1110 watch subactive 1101 high-speed 1111 * : don? care ? don? set.
593 20.1.1 register configuration the power-down modes are controlled by the sbycr, sckcr, lpwrcr, tcsr (wdt1), and mstpcr registers. table 20.3 summarizes these registers. table 20.3 power-down mode registers name abbreviation r/w initial value address * standby control register sbycr r/w h'08 h'fde4 system clock control register sckcr r/w h'00 h'fde6 low-power control register lpwrcr r/w h'00 h'fdec timer control/status register (wdt1) tcsr r/w h'00 h'ffa2 module stop control register mstpcra r/w h'3f h'fde8 mstpcrb r/w h'ff h'fde9 mstpcrc r/w h'ff h'fdea note: * lower 16 bits of the address. 20.2 register descriptions 20.2.1 standby control register (sbycr) 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ope 1 r/w 0 0 2 0 1 0 bit initial value read/write sbycr is an 8-bit readable/writable register that performs power-down mode control. sbycr is initialized to h'08 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7?oftware standby (ssby): determines the operating mode, in combination with other control bits, when a power-down mode transition is made by executing a sleep instruction. the ssby setting is not changed by a mode transition due to an interrupt, etc.
594 bit 7 ssby description 0 transition to sleep mode after execution of sleep instruction in high-speed mode or medium-speed mode transition to subsleep mode after execution of sleep instruction in subactive mode (initial value) 1 transition to software standby mode, subactive mode, or watch mode after execution of sleep instruction in high-speed mode or medium-speed mode transition to watch mode or high-speed mode after execution of sleep instruction in subactive mode bits 6 to 4?tandby timer select 2 to 0 (sts2 to sts0): these bits select the time the mcu waits for the clock to stabilize when software standby mode, watch mode, or subactive mode is cleared and a transition is made to high-speed mode or medium-speed mode by means of a specific interrupt or instruction. with crystal oscillation, refer to table 20.4 and make a selection according to the operating frequency so that the standby time is at least 8 ms (the oscillation stabilization time). with an external clock, any selection can be made. bit 6 bit 5 bit 4 sts2 sts1 sts0 description 0 0 0 standby time = 8192 states (initial value) 1 standby time = 16384 states 1 0 standby time = 32768 states 1 standby time = 65536 states 1 0 0 standby time = 131072 states 1 standby time = 262144 states 1 0 reserved 1 standby time = 16 states bit 2 to 0?eserved: this bit cannot be modified and is always read as 0. bit 3?utput port enable (ope): specifies whether the address bus and bus control signals ( cs0 to cs7 , as , rd , hwr , and lwr ) retain their output state or go to the high-impedance state in software standby mode and watch mode, and in a direct transition.
595 bit 3 ope description 0 in software standby mode, watch mode, and in a direct transition, address bus and bus control signals are high-impedance 1 in software standby mode, watch mode, and in a direct transition, address bus and bus control signals retain their output state (initial value) 20.2.2 system clock control register (sckcr) 7 pstop 0 r/w 6 0 r/w 5 0 4 0 3 0 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value read/write sckcr is an 8-bit readable/writable register that performs ?clock output control and medium- speed mode control. sckcr is initialized to h?0 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 7? clock output disable (pstop): controls ?output. bit 7 description pstop active mode, subactive mode sleep mode, subsleep mode software standby mode, watch mode, direct transition hardware standby mode 0 output (initial value) ?output fixed high high impedance 1 fixed high fixed high fixed high high impedance bit 6?eserved: this bit can be read or written to, but should only be written with 0. bits 5 to 3?eserved: these bits cannot be modified and are always read as 0.
596 bits 2 to 0?ystem clock select 2 to 0 (sck2 to sck0): these bits select the clock for the bus master in high-speed mode and medium-speed mode. when operating the device after a transition to subactive mode or watch mode, bits sck2 to sck0 should all be cleared to 0. bit 2 bit 1 bit 0 sck2 sck1 sck0 description 0 0 0 bus master is in high-speed mode (initial value) 1 medium-speed clock is ?2 1 0 medium-speed clock is ?4 1 medium-speed clock is ?8 1 0 0 medium-speed clock is ?16 1 medium-speed clock is ?32 1 20.2.3 low-power control register (lpwrcr) 7 dton 0 r/w 6 lson 0 r/w 5 nesel 0 r/w 4 substp 0 r/w 3 rfcut 0 r/w 0 stc0 0 r/w 2 0 r/w 1 stc1 0 r/w bit initial value read/write lpwrcr is an 8-bit readable/writable register that performs power-down mode control. lpwrcr is initialized to h'00 by a power-on reset and in hardware standby mode. it is not initialized by a manual reset or in software standby mode. only bits 7 to 4 are described here; for details of the other bits, see section 19.2.2, low-power control register (lpwrcr). bit 7?irect-transfer on flag (dton): specifies whether a direct transition is made between high-speed mode, medium-speed mode, and subactive mode when making a power-down transition by executing a sleep instruction. the operating mode to which the transition is made after sleep instruction execution is determined by a combination of other control bits.
597 bit 7 dton description 0 when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode * when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode (initial value) 1 when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode * , or a transition is made to sleep mode or software standby mode when a sleep instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode note: * when a transition is made to watch mode or subactive mode, high-speed mode must be set. bit 6?ow-speed on flag (lson): determines the operating mode in combination with other control bits when making a power-down transition by executing a sleep instruction. also controls whether a transition is made to high-speed mode or medium-speed mode, or to subactive mode when watch mode is cleared. bit 6 lson description 0 when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode * when a sleep instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode after watch mode is cleared, a transition is made to high-speed mode (initial value) 1 when a sleep instruction is executed in high-speed mode a transition is made to watch mode or subactive mode * when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode after watch mode is cleared, a transition is made to subactive mode note: * when a transition is made to watch mode or subactive mode, high-speed mode must be set. bit 5?oise elimination sampling frequency select (nesel): selects the frequency at which the subclock (?ub) generated by the subclock oscillator is sampled with the clock (? generated by the system clock oscillator. when ?= 5 mhz or higher, clear this bit to 0.
598 bit 5 nesel description 0 sampling at ?divided by 32 (initial value) 1 sampling at ?divided by 4 bit 4?ubclock oscillator control (substp): controls operation and stopping of the subclock oscillator. bit 4 substp description 0 subclock oscillator operates (initial value) 1 subclock oscillator is stopped 20.2.4 timer control/status register (tcsr) wdt1 tcsr 7 ovf 0 r/(w) * 6 wt/it 0 r/w 5 tme 0 r/w 4 pss 0 r/w 3 rst/nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write note: * only 0 can be written in bit 7, to clear the flag. tcsr is an 8-bit readable/writable register that performs selection of the wdt1 tcnt input clock, mode, etc. only bit 4 is described here. for details of the other bits, see section 12.2.2, timer control/status register (tcsr). tcsr is initialized to h'00 by a reset and in hardware standby mode. it is not initialized in software standby mode. bit 4?rescaler select (pss): selects the wdt1 tcnt input clock. this bit also controls the operation in a power-down mode transition. the operating mode to which a transition is made after execution of a sleep instruction is determined in combination with other control bits. for details, see the description of clock select 2 to 0 in section 12.2.2, timer control/status register (tcsr).
599 bit 4 pss description 0 tcnt counts ?based prescaler (psm) divided clock pulses when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode or software standby mode (initial value) 1 tcnt counts ?ub-based prescaler (pss) divided clock pulses when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, watch mode * , or subactive mode * when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode, watch mode, or high-speed mode note: * when a transition is made to watch mode or subactive mode, high-speed mode must be set. 20.2.5 module stop control register (mstpcr) 7 mstpa7 0 r/w 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 0 mstpa0 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w bit initial value read/write mstpcra 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 0 mstpb0 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w bit initial value read/write mstpcrb 7 mstpc7 1 r/w 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 0 mstpc0 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w bit initial value read/write mstpcrc mstpcra, mstpcrb, and mstpcrc are 8-bit readable/writable registers that perform module stop mode control.
600 mstpcra is initialized to h'3f by a reset and in hardware standby mode. mstpcrb and mstpcrc are initialized to h'ff. they are not initialized in software standby mode. mstpcra, mstpcrb, and mstpcrc bits 7 to 0?odule stop (mstpa7 to mstpa0, mstpb7 to mstpb0, and mstpc7 to mstpc0): these bits specify module stop mode. see table 20.4 for the method of selecting on-chip supporting modules. mstpcra, mstpcrb, and mstpcrc bits 7 to 0 mstpa7 to mstpa0, mstpb7 to mstpb0, and mstpc7 to mstpc0 description 0 module stop mode is cleared (initial value of mstpa7, mstpa6) 1 module stop mode is set (initial value of except mstpa7 to mstpa6) 20.3 medium-speed mode when the sck2 to sck0 bits in sckcr are set to 1 in high-speed mode, the operating mode changes to medium-speed mode at the end of the bus cycle. in medium-speed mode, the cpu operates on the operating clock (?2, ?4, ?8, ?16, or ?32) specified by the sck2 to sck0 bits. the bus master other than the cpu (the dtc) also operates in medium-speed mode. on-chip supporting modules other than the bus masters always operate on the high-speed clock (?. in medium-speed mode, a bus access is executed in the specified number of states with respect to the bus master operating clock. for example, if ?4 is selected as the operating clock, on-chip memory is accessed in 4 states, and internal i/o registers in 8 states. medium-speed mode is cleared by clearing all of bits sck2 to sck0 to 0. a transition is made to high-speed mode and medium-speed mode is cleared at the end of the current bus cycle. if a sleep instruction is executed when the ssby bit in sbycr and the lson bit in lpwrcr are cleared to 0, a transition is made to sleep mode. when sleep mode is cleared by an interrupt, medium-speed mode is restored. if a sleep instruction is executed when the ssby bit in sbycr is set to 1, and the lson bit in lpwrcr and the pss bit in tcsr (wdt1) are both cleared to 0, a transition is made to software standby mode. when software standby mode is cleared by an external interrupt, medium-speed mode is restored. when the res pin and mres pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. the same applies in the case of a reset caused by overflow of the watchdog timer.
601 when the stby pin is driven low, a transition is made to hardware standby mode. figure 20.2 shows the timing for transition to and clearance of medium-speed mode. bus master clock ? supporting module clock internal address bus internal write signal medium-speed mode sbycr sbycr figure 20.2 medium-speed mode transition and clearance timing 20.4 sleep mode 20.4.1 sleep mode if a sleep instruction is executed when the ssby bit in sbycr and the lson bit in lpwrcr are both cleared to 0, the cpu enters sleep mode. in sleep mode, cpu operation stops but the contents of the cpu? internal registers are retained. other supporting modules do not stop. 20.4.2 clearing sleep mode sleep mode is cleared by all interrupts, or with the res pin, mres pin or stby pin. clearing with an interrupt: when an interrupt request signal is input, sleep mode is cleared and interrupt exception handling is started. sleep mode will not be cleared if interrupts are disabled, or if interrupts other than nmi have been masked by the cpu. clearing with the res pin and mres pin: when the res pin and mres pin is driven low, the reset state is entered. when the res pin and mres pin is driven high after the prescribed reset input period, the cpu begins reset exception handling. clearing with the stby pin: when the stby pin is driven low, a transition is made to hardware standby mode.
602 20.5 module stop mode 20.5.1 module stop mode module stop mode can be set for individual on-chip supporting modules. when the corresponding mstp bit in mstpcr is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. the cpu continues operating independently. table 20.4 shows mstp bits and the corresponding on-chip supporting modules. when the corresponding mstp bit is cleared to 0, module stop mode is cleared and the module starts operating again at the end of the bus cycle. in module stop mode, the internal states of modules other than the a/d converter are retained. after reset release, all modules other than the dtc are in module stop mode. when an on-chip supporting module is in module stop mode, read/write access to its registers is disabled. when a transition is made to sleep mode with all modules stopped (mstpcr = h'ffffff), the bus controller and i/o ports also stop operating, enabling current dissipation to be further reduced.
603 table 20.4 mstp bits and corresponding on-chip supporting modules register bit module mstpcra mstpa7 * mstpa6 data transfer controller (dtc) mstpa5 16-bit timer pulse unit (tpu) mstpa4 8-bit timers (tmr0, tmr1) mstpa3 * mstpa2 * mstpa1 a/d converter mstpa0 * mstpcrb mstpb7 serial communication interface 0 (sci0) mstpb6 serial communication interface 1 (sci1) mstpb5 serial communication interface 2 (sci2) mstpb4 * mstpb3 * mstpb2 * mstpb1 * mstpb0 * mstpcrc mstpc7 serial communication interface 3 (sci3) mstpc6 * mstpc5 d/a converter mstpc4 pc break controller (pbc) mstpc3 * mstpc2 * mstpc1 * mstpc0 * note: * reserved. 20.5.2 usage note dtc module stop mode: depending on the operating status of the dtc, the mstpa6 bit may not be set to 1. setting of the dtc module stop mode should be carried out only when the dtc is not activated. for details, see section 8, data transfer controller (dtc). on-chip supporting module interrupts: relevant interrupt operations cannot be performed in module stop mode. consequently, if module stop mode is entered when an interrupt has been
604 requested, it will not be possible to clear the cpu interrupt source or dtc activation source. interrupts should therefore be disabled before setting module stop mode. writing to mstpcr: mstpcr should be written to only by the cpu. 20.6 software standby mode 20.6.1 software standby mode if a sleep instruction is executed when the ssby bit in sbycr is set to 1, the lson bit in lpwrcr is cleared to 0, and the pss bit in tcsr (wdt1) is cleared to 0, software standby mode is entered. in this mode, the cpu, on-chip supporting modules, and oscillator all stop. however, the contents of the cpu? internal registers, ram data, and the states of on-chip supporting module other than the a/d converter, and of the i/o ports, are retained. the address bus and bus control signals are placed in the high-impedance state. in this mode the oscillator stops, and therefore power dissipation is significantly reduced. 20.6.2 clearing software standby mode software standby mode is cleared by an external interrupt (nmi pin, or pins irq0 to irq7 ), or by means of the res pin, mres pin or stby pin. clearing with an interrupt: when an nmi or irq0 to irq7 interrupt request signal is input, clock oscillation starts, and after the elapse of the time set in bits sts2 to sts0 in syscr, stable clocks are supplied to the entire h8s/2237 series or h8s/2227 series chip, software standby mode is cleared, and interrupt exception handling is started. when software standby mode is cleared with an irq0 to irq7 interrupt, set the corresponding enable bit to 1 and ensure that an interrupt of higher priority than interrupts irq0 to irq7 is not generated. software standby mode cannot be cleared if the interrupt has been masked by the cpu side or has been designated as a dtc activation source. clearing with the res pin and mres pin: when the res pin and mres pin are driven low, clock oscillation is started. at the same time as clock oscillation starts, clocks are supplied to the entire h8s/2237 series or h8s/2227 series chip. note that the res pin and mres pin must be held low until clock oscillation stabilizes. when the res pin and mres pin go high, the cpu begins reset exception handling. clearing with the stby pin: when the stby pin is driven low, a transition is made to hardware standby mode.
605 20.6.3 setting oscillation stabilization time after clearing software standby mode bits sts2 to sts0 in sbycr should be set as described below. using a crystal oscillator: set bits sts2 to sts0 so that the standby time is at least 8 ms (the oscillation stabilization time). table 20.5 shows the standby times for different operating frequencies and settings of bits sts2 to sts0. table 20.5 oscillation stabilization time settings sts2 sts1 sts0 standby time 13 mhz 10 mhz 8 mhz 6 mhz 4 mhz 2 mhz unit 0 0 0 8192 states 0.6 0.8 1.0 1.3 2.0 4.1 ms 1 16384 states 1.3 1.6 2.0 2.7 4.1 8.2 1 0 32768 states 2.5 3.3 4.1 5.5 8.2 16.4 1 65536 states 5.0 6.6 8.2 10.9 16.4 32.8 1 0 0 131072 states 10.1 13.1 16.4 21.8 32.8 65.5 1 262144 states 20.2 26.2 32.8 43.6 65.6 131.2 1 0 reserved 1 16 states 1.2 1.6 2.0 1.7 4.0 8.0 m s : recommended time setting using an external clock: any value can be set. normally, use of the minimum time is recommended. 20.6.4 software standby mode application example figure 20.3 shows an example in which a transition is made to software standby mode at the falling edge on the nmi pin, and software standby mode is cleared at the rising edge on the nmi pin. in this example, an nmi interrupt is accepted with the nmieg bit in syscr cleared to 0 (falling edge specification), then the nmieg bit is set to 1 (rising edge specification), the ssby bit is set to 1, and a sleep instruction is executed, causing a transition to software standby mode. software standby mode is then cleared at the rising edge on the nmi pin.
606 oscillator nmi nmieg ssby nmi exception handling nmieg = 1 ssby = 1 sleep instruction software standby mode (power-down mode) oscillation stabilization time t osc2 nmi exception handling figure 20.3 software standby mode application example 20.6.5 usage notes i/o port states: in software standby mode, i/o port states are retained. if the ope bit is set to 1, the address bus and bus control signal output is also retained. therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. current dissipation during the oscillation stabilization wait period: current dissipation increases during the oscillation stabilization wait period. 20.7 hardware standby mode 20.7.1 hardware standby mode when the stby pin is driven low, a transition is made to hardware standby mode from any mode. in hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. as long as the prescribed voltage is supplied, on-chip ram data is retained. i/o ports are set to the high-impedance state.
607 in order to retain on-chip ram data, the rame bit in syscr should be cleared to 0 before driving the stby pin low. do not change the state of the mode pins (md2 to md0) while the h8s/2237 series and h8s/2227 series are in hardware standby mode. hardware standby mode is cleared by means of the stby pin and the res pin. when the stby pin is driven high while the res pin is low, the reset state is set and clock oscillation is started. ensure that the res pin is held low until the clock oscillation stabilizes (at least 8 ms?he oscillation stabilization time?hen using a crystal oscillator). when the res pin is subsequently driven high, a transition is made to the program execution state via the reset exception handling state. 20.7.2 hardware standby mode timing figure 20.4 shows an example of hardware standby mode timing. when the stby pin is driven low after the res pin has been driven low, a transition is made to hardware standby mode. hardware standby mode is cleared by driving the stby pin high, waiting for the oscillation stabilization time, then changing the res pin from low to high. oscillator res stby oscillation stabilization time reset exception handling figure 20.4 hardware standby mode timing (example)
608 20.8 watch mode 20.8.1 watch mode if a sleep instruction is executed in high-speed mode or subactive mode when the ssby in sbycr is set to 1, the dton bit in lpwrcr is cleared to 0, and the pss bit in tcsr (wdt1) is set to 1, the cpu makes a transition to watch mode. in this mode, the cpu and all on-chip supporting modules except wdt1 stop. the contents of cpu internal registers and on-chip ram, and the states of the on-chip supporting functions (except the a/d converter) and i/o ports, are retained. the address bus and bus control signals go to the high-impedance state. when a transition is made to watch mode, bits sck2 to sck0 in sckcr must all be cleared to 0. 20.8.2 clearing watch mode watch mode is cleared by an interrupt (wovi1 interrupt, nmi pin, or pins irq0 to irq7 ), or by means of the res pin, mres pin or stby pin. clearing with an interrupt: when an interrupt request signal is input, watch mode is cleared and a transition is made to high-speed mode or medium-speed mode if the lson bit in lpwrcr is cleared to 0, or to subactive mode if the lson bit is set to 1. when making a transition to high- speed mode, after the elapse of the time set in bits sts2 to sts0 in sbycr, stable clocks are supplied to the entire chip, and interrupt exception handling is started. watch mode cannot be cleared with an irq0 to irq7 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the cpu. see section 20.6.3, setting oscillation stabilization time after clearing software standby mode, for the oscillation stabilization time setting when making a transition from watch mode to high- speed mode. clearing with the res pin and mres pin: see ?learing with the res pin, mres pin?in section 20.6.2, clearing software standby mode. clearing with the stby pin: when the stby pin is driven low, a transition is made to hardware standby mode.
609 20.8.3 usage notes i/o port states: in watch mode, i/o port states are retained. if the ope bit is set to 1, address bus and bus control signal output is also retained. therefore, there is no reduction in current dissipation for the output current when a high-level signal is output. current dissipation during the oscillation stabilization wait period: current dissipation increases during the oscillation stabilization wait period. 20.9 subsleep mode 20.9.1 subsleep mode if a sleep instruction is executed in subactive mode when the ssby in sbycr is cleared to 0, the lson bit in lpwrcr is set to 1, and the pss bit in tcsr (wdt1) is set to 1, the cpu makes a transition to subsleep mode. in this mode, the cpu and all on-chip supporting modules except tmr0, tmr1, wdt0, and wdt1 stop. the contents of cpu internal registers and on-chip ram, and the states of the on- chip supporting functions (except the a/d converter) and i/o ports, are retained. 20.9.2 clearing subsleep mode subsleep mode is cleared by an interrupt (on-chip supporting module interrupt, nmi pin, or pin irq0 to irq7 ), or by means of the res pin, mres pin, or stby pin. clearing with an interrupt: when an interrupt request signal is input, subsleep mode is cleared and interrupt exception handling is started. subsleep mode cannot be cleared with an irq0 to irq7 interrupt if the corresponding enable bit has been cleared to 0, or with an on-chip supporting module interrupt if acceptance of the relevant interrupt has been disabled by the interrupt enable register or masked by the cpu. clearing with the res pin and mres pin: see ?learing with the res pin, mres pin?in section 20.6.2, clearing software standby mode. clearing with the stby pin: when the stby pin is driven low, a transition is made to hardware standby mode
610 20.10 subactive mode 20.10.1 subactive mode if a sleep instruction is executed in high-speed mode when the ssby bit in sbycr, the dton bit in lpwrcr, and the pss bit in tcsr (wdt1) are all set to 1, the cpu makes a transition to subactive mode. when an interrupt is generated in watch mode, if the lson bit in lpwrcr is set to 1, a transition is made to subactive mode. when an interrupt is generated in subsleep mode, a transition is made to subactive mode. in subactive mode, the cpu performs sequential program execution at low speed on the subclock. in this mode, all on-chip supporting modules except tmr0, tmr1, wdt0, and wdt1 stop. when operating the device in subactive mode, bits sck2 to sck0 in sbycr must all be cleared to 0. 20.10.2 clearing subactive mode subsleep mode is cleared by a sleep instruction, or by means of the res pin, mres pin, or stby pin. clearing with a sleep instruction: when a sleep instruction is executed while the ssby bit in sbycr is set to 1, the dton bit in lpwrcr is cleared to 0, and the pss bit in tcsr (wdt1) is set to 1, subactive mode is cleared and a transition is made to watch mode. when a sleep instruction is executed while the ssby bit in sbycr is cleared to 0, the lson bit in lpwrcr is set to 1, and the pss bit in tcsr (wdt1) is set to 1, a transition is made to subsleep mode. when a sleep instruction is executed while the ssby bit in sbycr is set to 1, the dton bit is set to 1 and the lson bit is cleared to 0 in lpwrcr, and the pss bit in tcsr (wdt1) is set to 1, a transition is made directly to high-speed mode (sck0 to sck2 all 0). fort details of direct transition, see section 20.11, direct transition. clearing with the res pin and mres pin: see "clearing with the res pin or mres pin" in section 20.6.2., clearing software standby mode. clearing with the stby pin: when the stby pin is driven low, a transition is made to hardware standby mode
611 20.11 direct transition 20.11.1 overview of direct transition there are three operating modes in which the cpu executes programs: high-speed mode, medium- speed mode, and subactive mode. a transition between high-speed mode and subactive mode without halting the program is called a direct transition. a direct transition can be carried out by setting the dton bit in lpwrcr to 1 and executing a sleep instruction. after the transition, direct transition interrupt exception handling is started. direct transition from high-speed mode to subactive mode: if a sleep instruction is executed in high-speed mode while the ssby bit in sbycr, the lson bit and dton bit in lpwrcr, and the pss bit in tscr (wdt1) are all set to 1, a transition is made to subactive mode. direct transition from subactive mode to high-speed mode: if a sleep instruction is executed in subactive mode while the ssby bit in sbycr is set to 1, the lson bit is cleared to 0 and the dton bit is set to 1 in lpwrcr, and the pss bit in tscr (wdt1) is set to 1, after the elapse of the time set in bits sts2 to sts0 in sbycr, a transition is made to directly to high- speed mode. 20.12 ?clock output disabling function output of the ?clock can be controlled by means of the pstop bit in sckcr and the corresponding ddr bit. when the pstop bit is set to 1, the ?clock is stopped at the end of the bus cycle, and ?output goes high. ?clock output is enabled when pstop bit is cleared to 0. when ddr for the corresponding port is cleared to 0, ?clock output is disabled and input port mode is set. table 20-6 shows the state of the ?pin in each processing mode. table 20-6 ?pin state in each processing mode ddr 0 1 1 pstop 0 1 hardware standby mode high impedance high impedance high impedance software standby mode, watch mode, direct transition high impedance fixed high fixed high sleep mode, subsleep mode high impedance ?output fixed high high-speed mode, medium-speed mode, subactive mode high impedance ?output fixed high
612
613 section 21 electrical characteristics 21.1 absolute maximum ratings table 21-1 lists the absolute maximum ratings. table 21-1 absolute maximum ratings ?preliminary item symbol value unit power supply voltage v cc ?.3 to +4.6 v programming voltage v pp ?.3 to +13.5 v input voltage (except port 4 and 9) v in ?.3 to v cc +0.3 v input voltage (port 4 and 9) v in ?.3 to av cc +0.3 v reference voltage v ref ?.3 to av cc +0.3 v analog power supply voltage av cc ?.3 to +4.6 v analog input voltage v an ?.3 to av cc +0.3 v operating temperature t opr regular specifications: ?0 to +75 c wide-range specifications: ?0 to +85 c storage temperature t stg ?5 to +125 c caution: permanent damage to the chip may result if absolute maximum rating are exceeded.
614 21.2 power supply voltage and operating frequency range power supply voltage and operating frequency ranges (shaded areas) are shown in figure 21.1. ?preliminary system clock (1) power supply voltage and oscillation frequency range (ztat tm version) ?active (high-speed/medium-speed) mode ?sleep mode f (mhz) 13.5 10.0 6.0 5.0 2.0 0 2.2 2.7 3.0 3.6 vcc (v) ?all operating modes f (khz) 32.768 0 2.2 2.7 3.0 3.6 vcc (v) vcc (v) subclock system clock (3) power supply voltage and instruction execution time range (ztat tm version) ?active (high-speed/medium-speed) mode (ns) 74 100 200 500 0 2.2 2.7 3.0 3.6 vcc (v) ?subactive mode ( s) 30.5 0 2.2 2.7 3.0 3.6 3.0 3.6 subclock system clock (2) power supply voltage and oscillation frequency range (mask rom version) ?active (high-speed/medium-speed) mode ?sleep mode f (mhz) 13.5 10.0 5.0 2.0 0 2.2 2.7 3.0 3.6 vcc (v) ?all operating modes f (khz) 32.768 0 2.2 2.7 3.0 3.6 subclock system clock (4) power supply voltage and instruction execution time range (mask rom version) ?active (high-speed/medium-speed) mode (ns) 74 100 200 500 0 2.2 2.7 3.0 3.6 vcc (v) ?subactive mode ( s) 30.5 0 2.2 2.7 subclock figure 21-1 power supply voltage and operating ranges
615 21.3 dc characteristics table 21-2 lists the dc characteristics. table 21-3 lists the permissible output currents. table 21-2 dc characteristics ?preliminary conditions: ztat version: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?0 c to +75 c (regular specifications), t a = ?0 c to +85 c (wide-range specifications)* 1 mask rom version: v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, t a = ?0 c to +75 c (regular specifications), t a = ?0 c to +85 c (wide-range specifications)* 1 item symbol min typ max unit test conditions schmitt irq7 to irq0 v t v cc 0.2 v trigger input v t + v cc 0.8 v voltage v t + ?v t v cc 0.07 v input high voltage res , stby , nmi, md2 to md0 v ih v cc 0.9 v cc + 0.3 v extal v cc 0.8 v cc + 0.3 v port 1, 3, 7, a to g port4 and 9 v cc 0.8 av cc + 0.3 v input low voltage res , stby , md2 to md0 v il ?.3 v cc 0.1 v nmi, extal, port 1, 3, 4, 7, 9, a to g ?.3 v cc 0.2 v output high all output pins v oh v cc ?0.5 v i oh = ?00 m a voltage v cc ?1.0 v i oh = ? ma * 2 output low all output pins v ol 0.4 v i ol = 0.4 ma voltage 0.4 v i ol = 0.8 ma * 2 input leakage res | i in | 10.0 m av in = current stby , nmi, md2 to md0 1.0 m a 0.5 to v cc ?0.5 v port 4, 9 1.0 m av in = 0.5 to av cc ?0.5 v
616 table 21-2 dc characteristics (cont) ?preliminary conditions: ztat version: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?0 c to +75 c (regular specifications), t a = ?0 c to +85 c (wide-range specifications)* 1 mask rom version: v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, t a = ?0 c to +75 c (regular specifications), t a = ?0 c to +85 c (wide-range specifications)* 1 item symbol min typ max unit test conditions three-state leakage current (off state) port 1, 3, 7, a to g ? i tsi ? 1.0 m av in = 0.5 to v cc ?0.5 v mos input pull-up current port a to e i p 10 300 m av in = 0 v input res c in 80 pf v in = 0 v capacitance nmi 50 pf f = 1 mhz all input pins except res and nmi 15 pf t a = 25 c notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. apply a voltage between 2.0 v and 3.6 v to the av cc and v ref pins by connecting them to v cc , for instance. set v ref av cc . 2. v cc = 2.7 v to 3.6 v
617 table 21-2 dc characteristics (cont) ?preliminary conditions: ztat version: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?0 c to +75 c (regular specifications), t a = ?0 c to +85 c (wide-range specifications)* 1 item symbol min typ max unit test conditions current dissipation * 2 normal operation i cc * 4 ?6 v cc =3.0 v 28 v cc =3.6 v ma f = 10 mhz sleep mode 12 v cc =3.0 v 22 v cc =3.6 v ma f = 10 mhz all modules stopped 12 ma f = 10 mhz, v cc = 3.0 v (reference values) medium-speed mode (?32) 8.5 ma f = 10 mhz, v cc = 3.0 v (reference values) subactive mode 80 120 m a using 32.768 khz crystal resonator v cc = 3.0 v subsleep mode ?0 90 m a using 32.768 khz crystal resonator v cc = 3.0 v watch mode 8 12 m a using 32.768 khz crystal resonator v cc = 3.0 v standby mode * 3 0.01 5.0 m at a 50 c not using 32.768 khz 20.0 50 c < t a not using 32.768 khz
618 table 21-2 dc characteristics (cont) ?preliminary conditions: ztat version: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?0 c to +75 c (regular specifications), t a = ?0 c to +85 c (wide-range specifications)* 1 item symbol min typ max unit test conditions analog power supply current during a/d and d/a conversion al cc 0.2 1.0 ma av cc =3.0 v idle 0.01 5.0 m a reference current during a/d and d/a conversion al cc 1.3 2.5 ma v ref =3.0 v idle 0.01 5.0 m a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. apply a voltage between 2.0 v and 3.6 v to the av cc and v ref pins by connecting them to v cc , for instance. set v ref av cc . 2. current dissipation values are for v ih min = v cc ?0.5 v, v il max = 0.5 v with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. the values are for v ram v cc < 2.7 v, v ih min = v cc 0.9, and v il max = 0.3 v. 4. i cc depends on v cc and f as follows: i cc max = 1.0 (ma) + 0.74 (ma/(mhz v)) v cc f (normal operation) i cc max = 1.0 (ma) + 0.58 (ma/(mhz v)) v cc f (sleep mode)
619 table 21-2 dc characteristics (cont) ?preliminary conditions: mask rom version: v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, t a = ?0 c to +75 c (regular specifications), t a = ?0 c to +85 c (wide-range specifications)* 1 item symbol min typ max unit test conditions current dissipation * 2 normal operation i cc * 4 tbd v cc =3.0 v tbd v cc =3.6 v ma f = 13 mhz sleep mode tbd v cc =3.0 v tbd v cc =3.6 v ma f = 13 mhz all modules stopped tbd ma f = 13 mhz, v cc = 3.0 v (reference values) medium-speed mode (?32) tbd ma f = 13 mhz, v cc = 3.0 v (reference values) subactive mode tbd tbd m a using 32.768 khz crystal resonator v cc =3.0 v subsleep mode tbd tbd m a using 32.768 khz crystal resonator v cc =3.0 v watch mode tbd tbd m a using 32.768 khz crystal resonator v cc =3.0 v standby mode * 3 tbd tbd m at a 50 c not using 32.768 khz tbd 50 c < t a not using 32.768 khz
620 table 21-2 dc characteristics (cont) ?preliminary conditions: mask rom version: v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, t a = ?0 c to +75 c (regular specifications), t a = ?0 c to +85 c (wide-range specifications)* 1 item symbol min typ max unit test conditions analog power supply current during a/d and d/a conversion al cc tbd tbd ma av cc =3.0 v idle tbd tbd m a reference current during a/d and d/a conversion al cc tbd tbd ma v ref =3.0 v idle tbd tbd m a ram standby voltage v ram 2.0 v notes: 1. if the a/d and d/a converters are not used, do not leave the av cc , v ref , and av ss pins open. apply a voltage between 2.0 v and 3.6 v to the av cc and v ref pins by connecting them to v cc , for instance. set v ref av cc . 2. current dissipation values are for v ih min = v cc ?0.5 v, v il max = 0.5 v with all output pins unloaded and the on-chip pull-up resistors in the off state. 3. the values are for v ram v cc < 2.7 v, v ih min = v cc 0.9, and v il max = 0.3 v. 4. i cc depends on v cc and f as follows: i cc max = tbd (ma) + tbd (ma/(mhz v)) v cc f (normal operation) i cc max = tbd (ma) + tbd (ma/(mhz v)) v cc f (sleep mode)
621 table 21-3 permissible output currents ?preliminary conditions: ztat version: v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, t a = ?0 c to +75 c (regular specifications), t a = ?0 c to +85 c (wide-range specifications)* 1 mask rom version: v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, t a = ?0 c to +75 c (regular specifications), t a = ?0 c to +85 c (wide-range specifications)* 1 item symbol min typ max unit permissible output all output pins v cc = 2.2 to 3.6 v i ol 0.5 ma low current (per pin) v cc = 2.7 to 3.6 v 1.0 permissible output total of all v cc = 2.2 to 3.6 v ? i ol 30ma low current (total) output pins v cc = 2.7 to 3.6 v 60 permissible output all output pins v cc = 2.2 to 3.6 v i oh 0.5 ma high current (per pin) v cc = 2.7 to 3.6 v 1.0 permissible output total of all v cc = 2.2 to 3.6 v ? ? oh 15ma high current (total) output pins v cc = 2.7 to 3.6 v 30 note: to protect chip reliability, do not exceed the output current values in table 21-3. 21.4 ac characteristics figure 21-2 show, the test conditions for the ac characteristics. 3v r l r h c lsi output pin c=30pf: r l =2.4k r h =12k i/o timing test levels ?low level: 0.8 v ?high level: 2.0 v (vcc: 2.7 to 3.6 v) 1.5 v (vcc: 2.2 to 2.7 v) figure 21-2 output load circuit
622 21.4.1 clock timing table 21-4 lists the clock timing table 21-4 clock timing ?preliminary condition a (ztat version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 10 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition b (mask rom version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 13 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition c (mask rom version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , ?= 32.768 khz, 2 to 5 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition a condition b condition c item symbol min max min max min max unit test conditions clock cycle time t cyc 100 500 74 500 200 500 ns figure 21-3 clock high pulse width t ch 35 25 50 ns clock low pulse width t cl 35 25 50 ns clock rise time t cr ?5 10 ?5ns clock fall time t cf ?5 10 ?5ns clock oscillator settling time at reset (crystal) t osc1 20 20 tbd ms figure 21-4 clock oscillator settling time in software standby (crystal) t osc2 8 8 tbd ms figure 20-3 external clock output stabilization delay time t dext 500 500 tbd m s figure 21-4 32 khz clock oscillation settling time t osc3 ? ? ?bds subclock oscillator frequency f sub 32.768 32.768 32.768 khz subclock ( sub ) cycle time f sub 30.5 30.5 30.5 m s
623 t ch t cf t cyc t cl t cr figure 21-3 system clock timing t osc1 t osc1 extal v cc stby res ? t dext t dext figure 21-4 oscillator settling timing
624 21.4.2 control signal timing table 21-5 lists the control signal timing. table 21-5 control signal timing ?preliminary condition a (ztat version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 10 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition b (mask rom version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 13 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition c (mask rom version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 5 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition a condition b condition c item symbol min max min max min max unit test conditions res setup time t ress 250 250 350 ns figure 21-5 res pulse width t resw 20 20 20 t cyc mres setup time t mress 250 250 350 ns mres pulse width t mresw 20 20 20 t cyc nmi setup time t nmis 250 250 350 ns figure 21-6 nmi hold time t nmih 10 10 10 nmi pulse width (exiting software standby mode) t nmiw 200 200 300 ns irq setup time t irqs 250 250 350 ns irq hold time t irqh 10 10 10 ns irq pulse width (exiting software standby mode) t irqw 200 200 300 ns
625 t resw t ress t mress t mress t mresw t ress res mres figure 21-5 reset input timing t irqs t nmis t nmih irq edge input nmi t irqs t irqh irq irq level input t nmiw t irqw figure 21-6 interrupt input timing
626 21.4.3 bus timing table 21-6 lists the bus timing. table 21-6 bus timing ?preliminary condition a (ztat version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 to 10 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition b (mask rom version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ? 2 to 13 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition c (mask rom version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, ?= 2 to 5 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition a condition b condition c item symbol min max min max min max unit test conditions address delay time t ad 60 50 tbd ns figure 21-7 to address setup time t as 0.5 t cyc ?40 0.5 t cyc ?30 0.5 t cyc ?60 ?s figure 21-11 address hold time t ah 0.5 t cyc ?20 0.5 t cyc ?15 0.5 t cyc ?30 ?s cs delay time 1 t csd1 60 50 tbd ns as delay time t asd 60 50 tbd ns rd delay time 1 t rsd1 60 50 tbd ns rd delay time 2 t rsd2 60 50 tbd ns read data setup time t rds 30 30 tbd ns read data hold time t rdh 00 0ns read data access time1 t acc1 1.0 t cyc ?65 1.0 t cyc ?65 tbd ns read data access time2 t acc2 1.5 t cyc ?65 1.5 t cyc ?65 tbd ns read data access time3 t acc3 2.0 t cyc ?65 2.0 t cyc ?65 tbd ns
627 table 21-6 bus timing (cont) ?preliminary condition a (ztat version): v cc = 2.7 v to 5.5 v, av cc = 2.7 v to 5.5 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 to 10 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition b (mask rom version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ? 2 to 13 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition c (mask rom version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, ?= 2 to 5 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition a condition b condition c item symbol min max min max min max unit test conditions read data access time 4 t acc4 2.5 t cyc ?65 2.5 t cyc ?65 tbd ns figure 21-7 to figure 21-12 read data access time 5 t acc5 3.0 t cyc ?65 3.0 t cyc ?65 tbd ns wr delay time 1 t wrd1 60 50 tbd ns wr delay time 2 t wrd2 60 50 tbd ns wr pulse width 1 t wsw1 1.0 t cyc ?40 1.0 t cyc ?30 1.0 t cyc ?60 ?s wr pulse width 2 t wsw2 1.5 t cyc ?40 1.5 t cyc ?30 1.5 t cyc ?60 ?s write data delay time t wdd 80 70 tbd ns write data setup time t wds 0.5 t cyc ?50 0.5 t cyc ?37 0.5 t cyc ?100 ?s write data hold time t wdh 0.5 t cyc ?30 0.5 t cyc ?15 0.5 t cyc ?80 ?s wait setup time t wts 60 50 90 ns figure 21-9 wait hold time t wth 10 10 10 ns breq setup time t brqs 60 50 90 ns figure 21-12 back delay time t bacd 60 50 tbd ns bus-floating time t bzd 100 80 tbd ns
628 t rsd2 t1 t ad as a23 to a0 t asd rd (read) t2 t csd t as t asd t acc2 t as t as t rsd1 t acc3 t rds t rdh t wrd2 t wdd t wsw1 t wdh t ah cs7 to cs0 d15 to d0 (read) hwr , lwr (write) d15 to d0 (write) t ah t wrd2 figure 21-7 basic bus timing (two-state access)
629 t rsd2 t2 as a23 to a0 t asd rd (read) t3 t as t ah t asd t acc4 t rsd1 t acc5 t as t rds t rdh t wrd1 t wrd2 t wds t wsw2 t wdh t ah cs7 to cs0 d15 to d0 (read) hwr , lwr (write) d15 to d0 (write) t1 t csd t wdd t ad figure 21-8 basic bus timing (three-state access)
630 tw as a23 to a0 rd (read) t3 cs7 to cs0 d15 to d0 (read) hwr , lwr (write) d15 to d0 (write) t2 t wts t1 t wth t wts t wth wait figure 21-9 basic bus timing (three-state access with one wait state)
631 t rsd2 t1 as a23 to a0 t2 t ah t acc3 t rds cs7 to cs0 d15 to d0 (read) t2 or t3 t as t1 t asd t asd t rdh t ad rd (read) figure 21-10 burst rom access timing (two-state access)
632 t rsd2 t1 as a23 to a0 t1 t acc1 cs7 to cs0 d15 to d0 (read) t2 or t3 t rdh t ad rd (read) t rds figure 21-11 burst rom access timing (one-state access)
633 breq a23 to a0, cs7 to cs0 , t brqs t bacd t bzd t bacd t bzd t brqs back as , rd , hwr , lwr figure 21-12 external bus release timing
634 21.4.4 timing of on-chip supporting modules table 21-7 lists the timing of on-chip supporting modules. table 21-7 timing of on-chip supporting modules ?preliminary condition a (ztat version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 10 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition b (mask rom version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 13 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition c (mask rom version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 5 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition a condition b condition c item symbol min max min max min max unit test conditions i/o port output data delay time t pwd 100 100 tbd ns figure 21-13 input data setup time t prs 50 50 80 input data hold time t prh 50 50 50 tpu timer output delay time t tocd 100 100 tbd ns figure 21-14 timer input setup time t tics 50 40 60 timer clock input setup time t tcks 50 40 60 ns figure 21-15 timer clock single edge t tckwh 1.5 1.5 1.5 t cyc pulse width both edges t tckwl 2.5 2.5 2.5
635 table 21-7 timing of on-chip supporting modules (cont) condition a (ztat version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 10 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition b (mask rom version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 13 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition c (mask rom version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 5 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition a condition b condition c item symbol min max min max min max unit test conditions tmr timer output delay time t tmod 100 100 tbd ns figure 21-16 timer reset input setup time t tmrs 50 50 80 ns figure 21-18 timer clock input setup time t tmcs 50 50 80 ns figure 21-17 timer clock single edge t tmcwh 1.5 1.5 1.5 t cyc pulse width both edges t tmcwl 2.5 2.5 2.5 wdt1 buzz output delay time t buzd 100 100 tbd ns figure 21-19 sci input clock asynchro- nous t scyc 44 4t cyc figure 21-20 cycle synchro- nous 666 input clock pulse width t sckw 0.4 0.6 0.4 0.6 0.4 0.6 t scyc input clock rise time t sckr 1.5 1.5 1.5 t cyc input clock fall time t sckf 1.5 1.5 1.5 transmit data delay time t txd 100 100 tbd ns figure 21-21
636 table 21-7 timing of on-chip supporting modules (cont) condition a (ztat version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 10 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition b (mask rom version): v cc = 2.7 v to 3.6 v, av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 13 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition c (mask rom version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, ?= 32.768 khz, 2 to 5 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition a condition b condition c item symbol min max min max min max unit test conditions sci receive data setup time (synchronous) t rxs 100 75 150 ns figure 21-21 receive data hold time (synchronous) t rxh 100 75 150 ns a/d converter trigger input setup time t trgs 50 40 60 ns figure 21-22 port 1, 3, 4, 7, 9 a to g (read) t 2 t 1 t pwd t prh t prs port 1, 3, 7 a to g (write) figure 21-13 i/o port input/output timing
637 t tics t tocd output compare output * input capture input * note: * tioca0 to tioca5, tiocb0 to tiocb5, tiocc0, tiocc3, tiocd0, tiocd3 figure 21-14 tpu input/output timing t tcks t tcks tclka to tclkd t tckwh t tckwl figure 21-15 tpu clock input timing tmo0, tmo1 t tmod figure 21-16 8-bit timer output timing
638 tmci01 t tmcs t tmcs t tmcwh t tmcwl figure 21-17 8-bit timer clock input timing tmri01 t tmrs figure 21-18 8-bit timer reset input timing buzz t buzd t buzd figure 21-19 wdt1 output timing sck0 to sck3 t sckw t sckr t sckf t scyc figure 21-20 sck clock input timing
639 txd0 to txd3 (transit data) rxd0 to rxd3 (receive data) sck0 to sck3 t rxs t rxh t txd figure 21-21 sci input/output timing (clock synchronous mode) adtrg t trgs figure 21-22 a/d converter external trigger input timing
640 21.5 a/d conversion characteristics table 21-8 lists the a/d conversion characteristics. table 21-8 a/d conversion characteristics ?preliminary condition a (ztat version): v cc = av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 to 10 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition b (mask rom version): v cc = av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 to 13 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition c (mask rom version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, ?= 2 to 5 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition a condition b condition c item min typ max min typ max min typ max unit resolution 10 10 10 10 10 10 10 10 10 bits conversion time 13.4 9.9 26.8 m s analog input capacitance 20 20 20 pf permissible signal-source impedance 5 5 tbdk w nonlinearity error 6.0 6.0 tbd lsb offset error 4.0 4.0 tbd lsb full-scale error 4.0 4.0 tbd lsb quantization 0.5 0.5 tbd lsb absolute accuracy 8.0 8.0 tbd lsb
641 21.6 d/a convervion characteristics table 21-9 lists the d/a conversion characteristics. table 21-9 d/a conversion characteristics ?preliminary condition a (ztat version): v cc = av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 to 10 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition b (mask rom version): v cc = av cc = 2.7 v to 3.6 v, v ref = 2.7 v to av cc , v ss = av ss = 0 v, ?= 2 to 13 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition c (mask rom version): v cc = 2.2 v to 3.6 v, av cc = 2.2 v to 3.6 v, v ref = 2.2 v to av cc , v ss = av ss = 0 v, ?= 2 to 5 mhz, t a = ?0 to +75 c (regular specifications), t a = ?0 to +85 c (wide-range specifications) condition a condition b condition c item min typ max min typ max min typ max unit test conditions resolution 8 8 8 8 8 8 888bit conversion time 10 10 tbd m s 20-pf capacitive load absolute accuracy 2.0 3.0 2.0 3.0 tbd tbd lsb 2-m w resistive load 2.0 2.0 tbd lsb 4-m w resistive load 21.7 usage note although both the ztat and mask rom versions fully meet the electrical specifications listed in this manual, due to differences in the fabrication process, the on-chip rom, and the layout patterns, there will be differences in the actual values of the electrical characteristics, the operating margins, the noise margins, and other aspects. therefore, if a system is evaluated using the ztat version, a similar evaluation should also be performed using the mask rom version.
642
643 appendix a instruction set a.1 instruction list operand notation rd general register (destination) * 1 rs general register (source) * 1 rn general register * 1 ern general register (32-bit register) mac multiply-and-accumulate register (32-bit register) * 2 (ead) destination operand (eas) source operand exr extended control register ccr condition-code register n n (negative) flag in ccr z z (zero) flag in ccr v v (overflow) flag in ccr c c (carry) flag in ccr pc program counter sp stack pointer #imm immediate data disp displacement + add subtract multiply ? divide logical and logical or ? logical exclusive or ? transfer from the operand on the left to the operand on the right, or transition from the state on the left to the state on the right logical not (logical complement) ( ) < > contents of operand :8/:16/:24/:32 8-, 16-, 24-, or 32-bit length notes: 1. general registers include 8-bit registers (r0h to r7h, r0l to r7l), 16-bit registers (r0 to r7, e0 to e7), and 32-bit registers (er0 to er7). 2. the mac register cannot be used in the h8s/2237 series and h8s/2227 series.
644 condition code notation symbol changes according to the result of instruction * undetermined (no guaranteed value) 0 always cleared to 0 1 always set to 1 not affected by execution of the instruction
645 table a-1 instruction set (1) data transfer instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic mov mov.b #xx:8,rd b 2 mov.b rs,rd b 2 mov.b @ers,rd b 2 mov.b @(d:16,ers),rd b 4 mov.b @(d:32,ers),rd b 8 mov.b @ers+,rd b 2 mov.b @aa:8,rd b 2 mov.b @aa:16,rd b 4 mov.b @aa:32,rd b 6 mov.b rs,@erd b 2 mov.b rs,@(d:16,erd) b 4 mov.b rs,@(d:32,erd) b 8 mov.b rs,@-erd b 2 mov.b rs,@aa:8 b 2 mov.b rs,@aa:16 b 4 mov.b rs,@aa:32 b 6 mov.w #xx:16,rd w 4 mov.w rs,rd w 2 mov.w @ers,rd w 2 #xx:8 ? rd8 ? ? 0 ? 1 rs8 ? rd8 ? ? 0 ? 1 @ers ? rd8 ? ? 0 ? 2 @(d:16,ers) ? rd8 ? ? 0 ? 3 @(d:32,ers) ? rd8 ? ? 0 ? 5 @ers ? rd8,ers32+1 ? ers32 ? ? 0 ? 3 @aa:8 ? rd8 ? ? 0 ? 2 @aa:16 ? rd8 ? ? 0 ? 3 @aa:32 ? rd8 ? ? 0 ? 4 rs8 ? @erd ? ? 0 ? 2 rs8 ? @(d:16,erd) ? ? 0 ? 3 rs8 ? @(d:32,erd) ? ? 0 ? 5 erd32-1 ? erd32,rs8 ? @erd ? ? 0 ? 3 rs8 ? @aa:8 ? ? 0 ? 2 rs8 ? @aa:16 ? ? 0 ? 3 rs8 ? @aa:32 ? ? 0 ? 4 #xx:16 ? rd16 ? ? 0 ? 2 rs16 ? rd16 ? ? 0 ? 1 @ers ? rd16 ? ? 0 ? 2 operation condition code ihnzvc advanced no. of states * 1 ??????????????????? ???????????????????
646 table a-1 instruction set (cont) (1) data transfer instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic mov mov.w @(d:16,ers),rd w 4 mov.w @(d:32,ers),rd w 8 mov.w @ers+,rd w 2 mov.w @aa:16,rd w 4 mov.w @aa:32,rd w 6 mov.w rs,@erd w 2 mov.w rs,@(d:16,erd) w 4 mov.w rs,@(d:32,erd) w 8 mov.w rs,@-erd w 2 mov.w rs,@aa:16 w 4 mov.w rs,@aa:32 w 6 mov.l #xx:32,erd l 6 mov.l ers,erd l 2 mov.l @ers,erd l 4 mov.l @(d:16,ers),erd l 6 mov.l @(d:32,ers),erd l 10 mov.l @ers+,erd l 4 mov.l @aa:16,erd l 6 mov.l @aa:32,erd l 8 @(d:16,ers) ? rd16 ? ? 0 ? 3 @(d:32,ers) ? rd16 ? ? 0 ? 5 @ers ? rd16,ers32+2 ? ers32 ? ? 0 ? 3 @aa:16 ? rd16 ? ? 0 ? 3 @aa:32 ? rd16 ? ? 0 ? 4 rs16 ? @erd ? ? 0 ? 2 rs16 ? @(d:16,erd) ? ? 0 ? 3 rs16 ? @(d:32,erd) ? ? 0 ? 5 erd32-2 ? erd32,rs16 ? @erd ? ? 0 ? 3 rs16 ? @aa:16 ? ? 0 ? 3 rs16 ? @aa:32 ? ? 0 ? 4 #xx:32 ? erd32 ? ? 0 ? 3 ers32 ? erd32 ? ? 0 ? 1 @ers ? erd32 ? ? 0 ? 4 @(d:16,ers) ? erd32 ? ? 0 ? 5 @(d:32,ers) ? erd32 ? ? 0 ? 7 @ers ? erd32,ers32+4 ? @ers32 ?? 0 ? 5 @aa:16 ? erd32 ? ? 0 ? 5 @aa:32 ? erd32 ? ? 0 ? 6 operation condition code ihnzvc advanced no. of states * 1 ??????????????????? ???????????????????
647 table a-1 instruction set (cont) (1) data transfer instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic mov pop push ldm stm movfpe movtpe mov.l ers,@erd l 4 mov.l ers,@(d:16,erd) l 6 mov.l ers,@(d:32,erd) l 10 mov.l ers,@-erd l 4 mov.l ers,@aa:16 l 6 mov.l ers,@aa:32 l 8 pop.w rn w 2 pop.l ern l 4 push.w rn w 2 push.l ern l 4 ldm @sp+,(erm-ern) l 4 stm (erm-ern),@-sp l 4 movfpe @aa:16,rd movtpe rs,@aa:16 ers32 ? @erd ? ? 0 ? 4 ers32 ? @(d:16,erd) ? ? 0 ? 5 ers32 ? @(d:32,erd) ? ? 0 ? 7 erd32-4 ? erd32,ers32 ? @ erd ?? 0 ? 5 ers32 ? @aa:16 ? ? 0 ? 5 ers32 ? @aa:32 ? ? 0 ? 6 @sp ? rn16,sp+2 ? sp ? ? 0 ? 3 @sp ? ern32,sp+4 ? sp ? ? 0 ? 5 sp-2 ? sp,rn16 ? @sp ? ? 0 ? 3 sp-4 ? sp,ern32 ? @sp ? ? 0 ? 5 (@sp ? ern32,sp+4 ? sp) ?????? 7/9/11 [1] repeated for each register restored (sp-4 ? sp,ern32 ? @sp) ?????? 7/9/11 [1] repeated for each register saved [2] [2] operation condition code ihnzvc advanced no. of states * 1 ?????????? ?????????? cannot be used in the h8s/2237 series and h8s/2227 series cannot be used in the h8s/2237 series and h8s/2227 series
648 table a-1 instruction set (2) arithmetic instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic add addx adds inc daa sub add.b #xx:8,rd b 2 add.b rs,rd b 2 add.w #xx:16,rd w 4 add.w rs,rd w 2 add.l #xx:32,erd l 6 add.l ers,erd l 2 addx #xx:8,rd b 2 addx rs,rd b 2 adds #1,erd l 2 adds #2,erd l 2 adds #4,erd l 2 inc.b rd b 2 inc.w #1,rd w 2 inc.w #2,rd w 2 inc.l #1,erd l 2 inc.l #2,erd l 2 daa rd b 2 sub.b rs,rd b 2 sub.w #xx:16,rd w 4 rd8+#xx:8 ? rd8 ? 1 rd8+rs8 ? rd8 ? 1 rd16+#xx:16 ? rd16 ? [3] 2 rd16+rs16 ? rd16 ? [3] 1 erd32+#xx:32 ? erd32 ? [4] 3 erd32+ers32 ? erd32 ? [4] 1 rd8+#xx:8+c ? rd8 ? [5] 1 rd8+rs8+c ? rd8 ? [5] 1 erd32+1 ? erd32 ? ? ? ? ? ? 1 erd32+2 ? erd32 ? ? ? ? ? ? 1 erd32+4 ? erd32 ? ? ? ? ? ? 1 rd8+1 ? rd8 ? ? ? 1 rd16+1 ? rd16 ? ? ? 1 rd16+2 ? rd16 ? ? ? 1 erd32+1 ? erd32 ? ? ? 1 erd32+2 ? erd32 ? ? ? 1 rd8 decimal adjust ? rd8 ? ** 1 rd8-rs8 ? rd8 ? 1 rd16-#xx:16 ? rd16 ? [3] 2 operation condition code ihnzvc advanced no. of states * 1 ??? ? ???????? ?? ????? ???????? ???????? ???????? ?????? ???????? ?? ??
649 table a-1 instruction set (cont) (2) arithmetic instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic sub subx subs dec das mulxu mulxs sub.w rs,rd w 2 sub.l #xx:32,erd l 6 sub.l ers,erd l 2 subx #xx:8,rd b 2 subx rs,rd b 2 subs #1,erd l 2 subs #2,erd l 2 subs #4,erd l 2 dec.b rd b 2 dec.w #1,rd w 2 dec.w #2,rd w 2 dec.l #1,erd l 2 dec.l #2,erd l 2 das rd b 2 mulxu.b rs,rd b 2 mulxu.w rs,erd w 2 mulxs.b rs,rd b 4 mulxs.w rs,erd w 4 rd16-rs16 ? rd16 ? [3] 1 erd32-#xx:32 ? erd32 ? [4] 3 erd32-ers32 ? erd32 ? [4] 1 rd8-#xx:8-c ? rd8 ? [5] 1 rd8-rs8-c ? rd8 ? [5] 1 erd32-1 ? erd32 ?????? 1 erd32-2 ? erd32 ?????? 1 erd32-4 ? erd32 ?????? 1 rd8-1 ? rd8 ? ? ? 1 rd16-1 ? rd16 ? ? ? 1 rd16-2 ? rd16 ? ? ? 1 erd32-1 ? erd32 ? ? ? 1 erd32-2 ? erd32 ? ? ? 1 rd8 decimal adjust ? rd8 ? * * ?1 rd8 rs8 ? rd16 (unsigned multiplication) ?????? 12 rd16 rs16 ? erd32 ?????? 20 (unsigned multiplication) rd8 rs8 ? rd16 (signed multiplication) ?? ?? 13 rd16 rs16 ? erd32 ? ? ? ? 21 (signed multiplication) operation condition code ihnzvc advanced no. of states * 1 ?? ?? ?????? ?????? ????? ??? ????? ????? ????? ??
650 table a-1 instruction set (cont) (2) arithmetic instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic divxu divxs cmp neg extu divxu.b rs,rd b 2 divxu.w rs,erd w 2 divxs.b rs,rd b 4 divxs.w rs,erd w 4 cmp.b #xx:8,rd b 2 cmp.b rs,rd b 2 cmp.w #xx:16,rd w 4 cmp.w rs,rd w 2 cmp.l #xx:32,erd l 6 cmp.l ers,erd l 2 neg.b rd b 2 neg.w rd w 2 neg.l erd l 2 extu.w rd w 2 extu.l erd l 2 rd16 rs8 ? rd16 (rdh: remainder, ? ? [6] [7] ? ? 12 rdl: quotient) (unsigned division) erd32 ? rs16 ? erd32 (ed: remainder, ? ? [6] [7] ? ? 20 rd: quotient) (unsigned division) rd16 ? rs8 ? rd16 (rdh: remainder, ? ? [8] [7] ? ? 13 rdl: quotient) (signed division) erd32 ? rs16 ? erd32 (ed: remainder, ? ? [8] [7] ? ? 21 rd: quotient) (signed division) rd8-#xx:8 ? 1 rd8-rs8 ? 1 rd16-#xx:16 ? [3] 2 rd16-rs16 ? [3] 1 erd32-#xx:32 ? [4] 3 erd32-ers32 ? [4] 1 0-rd8 ? rd8 ? 1 0-rd16 ? rd16 ? 1 0-erd32 ? erd32 ? 1 0 ? ( of rd16) ? ? 0 0 ? 1 0 ? ( of erd32) ? ? 0 0 ? 1 operation condition code ihnzvc advanced no. of states * 1 ??? ?? ??????????? ????????? ????????? ?????????
651 table a-1 instruction set (cont) (2) arithmetic instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic exts tas mac clrmac ldmac stmac exts.w rd w 2 exts.l erd l 2 tas @erd b 4 mac @ern+, @erm+ clrmac ldmac ers,mach ldmac ers,macl stmac mach,erd stmac macl,erd ( of rd16) ? ?? 0 ? 1 ( of rd16) ( of erd32) ? ?? 0 ? 1 ( of erd32) @erd-0 ? ccr set, (1) ? ?? 0 ? 4 ( < bit 7 > of @erd) [2] operation condition code ihnzvc advanced no. of states * 1 ? ? ? ? ? ? cannot be used in the h8s/2237 series and h8s/2227 series
652 table a-1 instruction set (3) logical instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic and or xor not and.b #xx:8,rd b 2 and.b rs,rd b 2 and.w #xx:16,rd w 4 and.w rs,rd w 2 and.l #xx:32,erd l 6 and.l ers,erd l 4 or.b #xx:8,rd b 2 or.b rs,rd b 2 or.w #xx:16,rd w 4 or.w rs,rd w 2 or.l #xx:32,erd l 6 or.l ers,erd l 4 xor.b #xx:8,rd b 2 xor.b rs,rd b 2 xor.w #xx:16,rd w 4 xor.w rs,rd w 2 xor.l #xx:32,erd l 6 xor.l ers,erd l 4 not.b rd b 2 not.w rd w 2 not.l erd l 2 rd8 #xx:8 ? rd8 ? ? 0 ? 1 rd8 rs8 ? rd8 ? ? 0 ? 1 rd16 #xx:16 ? rd16 ? ? 0 ? 2 rd16 rs16 ? rd16 ? ? 0 ? 1 erd32 #xx:32 ? erd32 ? ? 0 ? 3 erd32 ers32 ? erd32 ? ? 0 ? 2 rd8 #xx:8 ? rd8 ? ? 0 ? 1 rd8 rs8 ? rd8 ? ? 0 ? 1 rd16 #xx:16 ? rd16 ? ? 0 ? 2 rd16 rs16 ? rd16 ? ? 0 ? 1 erd32 #xx:32 ? erd32 ? ? 0 ? 3 erd32 ers32 ? erd32 ? ? 0 ? 2 rd8 ? #xx:8 ? rd8 ? ? 0 ? 1 rd8 ? rs8 ? rd8 ? ? 0 ? 1 rd16 ? #xx:16 ? rd16 ? ? 0 ? 2 rd16 ? rs16 ? rd16 ? ? 0 ? 1 erd32 ? #xx:32 ? erd32 ? ? 0 ? 3 erd32 ? ers32 ? erd32 ? ? 0 ? 2 a rd8 ? rd8 ? ? 0 ? 1 a rd16 ? rd16 ? ? 0 ? 1 a erd32 ? erd32 ? ? 0 ? 1 operation condition code ihnzvc advanced no. of states * 1 ????????????????????? ?????????????????????
653 table a-1 instruction set (4) shift instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic shal shar shll shal.b rd b 2 shal.b #2,rd b 2 shal.w rd w 2 shal.w #2,rd w 2 shal.l erd l 2 shal.l #2,erd l 2 shar.b rd b 2 shar.b #2,rd b 2 shar.w rd w 2 shar.w #2,rd w 2 shar.l erd l 2 shar.l #2,erd l 2 shll.b rd b 2 shll.b #2,rd b 2 shll.w rd w 2 shll.w #2,rd w 2 shll.l erd l 2 shll.l #2,erd l 2 1 1 1 1 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 operation condition code ihnzvc advanced no. of states * 1 ?????????????????? ?????????????????? ?????? ?????????????????? c msb lsb msb lsb 0 c msb lsb c 0
654 table a-1 instruction set (cont) (4) shift instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic shlr rotxl rotxr shlr.b rd b 2 shlr.b #2,rd b 2 shlr.w rd w 2 shlr.w #2,rd w 2 shlr.l erd l 2 shlr.l #2,erd l 2 rotxl.b rd b 2 rotxl.b #2,rd b 2 rotxl.w rd w 2 rotxl.w #2,rd w 2 rotxl.l erd l 2 rotxl.l #2,erd l 2 rotxr.b rd b 2 rotxr.b #2,rd b 2 rotxr.w rd w 2 rotxr.w #2,rd w 2 rotxr.l erd l 2 rotxr.l #2,erd l 2 001 001 001 001 001 001 01 01 01 01 01 01 01 01 01 01 01 01 operation condition code ihnzvc advanced no. of states * 1 ?????????????????? ?????????????????? ???????????? c msb lsb 0 c msb lsb c msb lsb
655 0 1 0 1 0 1 0 1 0 1 0 1 01 01 01 0 1 01 101 table a-1 instruction set (cont) (4) shift instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic rotl rotr rotl.b rd b 2 rotl.b #2,rd b 2 rotl.w rd w 2 rotl.w #2,rd w 2 rotl.l erd l 2 rotl.l #2,erd l 2 rotr.b rd b 2 rotr.b #2,rd b 2 rotr.w rd w 2 rotr.w #2,rd w 2 rotr.l erd l 2 rotr.l #2,erd l 2 operation condition code ihnzvc advanced no. of states * 1 ???????????? ???????????? ???????????? c msb lsb c msb lsb
656 table a-1 instruction set (5) bit-manipulation instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic bset bclr bset #xx:3,rd b 2 bset #xx:3,@erd b 4 bset #xx:3,@aa:8 b 4 bset #xx:3,@aa:16 b 6 bset #xx:3,@aa:32 b 8 bset rn,rd b 2 bset rn,@erd b 4 bset rn,@aa:8 b 4 bset rn,@aa:16 b 6 bset rn,@aa:32 b 8 bclr #xx:3,rd b 2 bclr #xx:3,@erd b 4 bclr #xx:3,@aa:8 b 4 bclr #xx:3,@aa:16 b 6 bclr #xx:3,@aa:32 b 8 bclr rn,rd b 2 bclr rn,@erd b 4 bclr rn,@aa:8 b 4 bclr rn,@aa:16 b 6 (#xx:3 of rd8) ? 1 ?????? 1 (#xx:3 of @erd) ? 1 ?????? 4 (#xx:3 of @aa:8) ? 1 ?????? 4 (#xx:3 of @aa:16) ? 1 ?????? 5 (#xx:3 of @aa:32) ? 1 ?????? 6 (rn8 of rd8) ? 1 ?????? 1 (rn8 of @erd) ? 1 ?????? 4 (rn8 of @aa:8) ? 1 ?????? 4 (rn8 of @aa:16) ? 1 ?????? 5 (rn8 of @aa:32) ? 1 ?????? 6 (#xx:3 of rd8) ? 0 ?????? 1 (#xx:3 of @erd) ? 0 ?????? 4 (#xx:3 of @aa:8) ? 0 ?????? 4 (#xx:3 of @aa:16) ? 0 ?????? 5 (#xx:3 of @aa:32) ? 0 ?????? 6 (rn8 of rd8) ? 0 ?????? 1 (rn8 of @erd) ? 0 ?????? 4 (rn8 of @aa:8) ? 0 ?????? 4 (rn8 of @aa:16) ? 0 ?????? 5 operation condition code ihnzvc advanced no. of states * 1
657 table a-1 instruction set (cont) (5) bit-manipulation instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic bclr bnot btst bclr rn,@aa:32 b 8 bnot #xx:3,rd b 2 bnot #xx:3,@erd b 4 bnot #xx:3,@aa:8 b 4 bnot #xx:3,@aa:16 b 6 bnot #xx:3,@aa:32 b 8 bnot rn,rd b 2 bnot rn,@erd b 4 bnot rn,@aa:8 b 4 bnot rn,@aa:16 b 6 bnot rn,@aa:32 b 8 btst #xx:3,rd b 2 btst #xx:3,@erd b 4 btst #xx:3,@aa:8 b 4 btst #xx:3,@aa:16 b 6 (rn8 of @aa:32) ? 0 ?????? 6 (#xx:3 of rd8) ? [a (#xx:3 of rd8)] ?????? 1 (#xx:3 of @erd) ? ?????? 4 [a (#xx:3 of @erd)] (#xx:3 of @aa:8) ? ?????? 4 [a (#xx:3 of @aa:8)] (#xx:3 of @aa:16) ? ?????? 5 [a (#xx:3 of @aa:16)] (#xx:3 of @aa:32) ? ?????? 6 [a (#xx:3 of @aa:32)] (rn8 of rd8) ? [a (rn8 of rd8)] ?????? 1 (rn8 of @erd) ? [a (rn8 of @erd)] ?????? 4 (rn8 of @aa:8) ? [a (rn8 of @aa:8)] ?????? 4 (rn8 of @aa:16) ? ?????? 5 [a (rn8 of @aa:16)] (rn8 of @aa:32) ? ?????? 6 [a (rn8 of @aa:32)] a (#xx:3 of rd8) ? z ??? ?? 1 a (#xx:3 of @erd) ? z ??? ?? 3 a (#xx:3 of @aa:8) ? z ??? ?? 3 a (#xx:3 of @aa:16) ? z ??? ?? 4 operation condition code ihnzvc advanced no. of states * 1 ????
658 table a-1 instruction set (cont) (5) bit-manipulation instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic btst bld bild bst btst #xx:3,@aa:32 b 8 btst rn,rd b 2 btst rn,@erd b 4 btst rn,@aa:8 b 4 btst rn,@aa:16 b 6 btst rn,@aa:32 b 8 bld #xx:3,rd b 2 bld #xx:3,@erd b 4 bld #xx:3,@aa:8 b 4 bld #xx:3,@aa:16 b 6 bld #xx:3,@aa:32 b 8 bild #xx:3,rd b 2 bild #xx:3,@erd b 4 bild #xx:3,@aa:8 b 4 bild #xx:3,@aa:16 b 6 bild #xx:3,@aa:32 b 8 bst #xx:3,rd b 2 bst #xx:3,@erd b 4 bst #xx:3,@aa:8 b 4 ?(#xx:3 of @aa:32) ? z ??? ?? 5 a (rn8 of rd8) ? z ??? ?? 1 a (rn8 of @erd) ? z ??? ?? 3 a (rn8 of @aa:8) ? z ??? ?? 3 a (rn8 of @aa:16) ? z ??? ?? 4 a (rn8 of @aa:32) ? z ??? ?? 5 (#xx:3 of rd8) ? c ????? 1 (#xx:3 of @erd) ? c ????? 3 (#xx:3 of @aa:8) ? c ????? 3 (#xx:3 of @aa:16) ? c ????? 4 (#xx:3 of @aa:32) ? c ????? 5 a (#xx:3 of rd8) ? c ????? 1 a (#xx:3 of @erd) ? c ????? 3 a (#xx:3 of @aa:8) ? c ????? 3 a (#xx:3 of @aa:16) ? c ????? 4 a (#xx:3 of @aa:32) ? c ????? 5 c ? (#xx:3 of rd8) ?????? 1 c ? (#xx:3 of @erd) ?????? 4 c ? (#xx:3 of @aa:8) ?????? 4 operation condition code ihnzvc advanced no. of states * 1 ?????????? ??????
659 table a-1 instruction set (cont) (5) bit-manipulation instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic bst bist band biand bor bst #xx:3,@aa:16 b 6 bst #xx:3,@aa:32 b 8 bist #xx:3,rd b 2 bist #xx:3,@erd b 4 bist #xx:3,@aa:8 b 4 bist #xx:3,@aa:16 b 6 bist #xx:3,@aa:32 b 8 band #xx:3,rd b 2 band #xx:3,@erd b 4 band #xx:3,@aa:8 b 4 band #xx:3,@aa:16 b 6 band #xx:3,@aa:32 b 8 biand #xx:3,rd b 2 biand #xx:3,@erd b 4 biand #xx:3,@aa:8 b 4 biand #xx:3,@aa:16 b 6 biand #xx:3,@aa:32 b 8 bor #xx:3,rd b 2 bor #xx:3,@erd b 4 c ? (#xx:3 of @aa:16) ?????? 5 c ? (#xx:3 of @aa:32) ?????? 6 a c ? (#xx:3 of rd8) ?????? 1 a c ? (#xx:3 of @erd) ?????? 4 a c ? (#xx:3 of @aa:8) ?????? 4 a c ? (#xx:3 of @aa:16) ?????? 5 a c ? (#xx:3 of @aa:32) ?????? 6 c (#xx:3 of rd8) ? c ????? 1 c (#xx:3 of @erd) ? c ????? 3 c (#xx:3 of @aa:8) ? c ????? 3 c (#xx:3 of @aa:16) ? c ????? 4 c (#xx:3 of @aa:32) ? c ????? 5 c [a (#xx:3 of rd8)] ? c ????? 1 c [a (#xx:3 of @erd)] ? c ????? 3 c [a (#xx:3 of @aa:8)] ? c ????? 3 c [a (#xx:3 of @aa:16)] ? c ????? 4 c [a (#xx:3 of @aa:32)] ? c ????? 5 c (#xx:3 of rd8) ? c ????? 1 c (#xx:3 of @erd) ? c ????? 3 operation condition code ihnzvc advanced no. of states * 1 ????????????
660 table a-1 instruction set (cont) (5) bit-manipulation instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic bor bior bxor bixor bor #xx:3,@aa:8 b 4 bor #xx:3,@aa:16 b 6 bor #xx:3,@aa:32 b 8 bior #xx:3,rd b 2 bior #xx:3,@erd b 4 bior #xx:3,@aa:8 b 4 bior #xx:3,@aa:16 b 6 bior #xx:3,@aa:32 b 8 bxor #xx:3,rd b 2 bxor #xx:3,@erd b 4 bxor #xx:3,@aa:8 b 4 bxor #xx:3,@aa:16 b 6 bxor #xx:3,@aa:32 b 8 bixor #xx:3,rd b 2 bixor #xx:3,@erd b 4 bixor #xx:3,@aa:8 b 4 bixor #xx:3,@aa:16 b 6 bixor #xx:3,@aa:32 b 8 c (#xx:3 of @aa:8) ? c ????? 3 c (#xx:3 of @aa:16) ? c ????? 4 c (#xx:3 of @aa:32) ? c ????? 5 c [a (#xx:3 of rd8)] ? c ????? 1 c [a (#xx:3 of @erd)] ? c ????? 3 c [a (#xx:3 of @aa:8)] ? c ????? 3 c [a (#xx:3 of @aa:16)] ? c ????? 4 c [a (#xx:3 of @aa:32)] ? c ????? 5 c ? (#xx:3 of rd8) ? c ????? 1 c ? (#xx:3 of @erd) ? c ????? 3 c ? (#xx:3 of @aa:8) ? c ????? 3 c ? (#xx:3 of @aa:16) ? c ????? 4 c ? (#xx:3 of @aa:32) ? c ????? 5 c ? [a (#xx:3 of rd8)] ? c ????? 1 c ? [a (#xx:3 of @erd)] ? c ????? 3 c ? [a (#xx:3 of @aa:8)] ? c ????? 3 c ? [a (#xx:3 of @aa:16)] ? c ????? 4 c ? [a (#xx:3 of @aa:32)] ? c ????? 5 operation condition code ihnzvc advanced no. of states * 1 ??????????????????
661 table a-1 instruction set (6) branch instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic bcc always 2 3 never 2 3 c z=0 ?????? 2 ?????? 3 c z=1 ?????? 2 ?????? 3 c=0 ?????? 2 ?????? 3 c=1 ?????? 2 ?????? 3 z=0 ?????? 2 ?????? 3 z=1 ?????? 2 ?????? 3 v=0 ?????? 2 ?????? 3 operation condition code branching condition ihnzvc advanced no. of states * 1 bra d:8(bt d:8) 2 if condition is true then bra d:16(bt d:16) 4 pc ? pc+d brn d:8(bf d:8) ? 2 else next; brn d:16(bf d:16) ? 4 bhi d:8 ? 2 bhi d:16 ? 4 bls d:8 ? 2 bls d:16 ? 4 bcc d:b(bhs d:8) ? 2 bcc d:16(bhs d:16) ? 4 bcs d:8(blo d:8) ? 2 bcs d:16(blo d:16) ? 4 bne d:8 ? 2 bne d:16 ? 4 beq d:8 ? 2 beq d:16 ? 4 bvc d:8 ? 2 bvc d:16 ? 4
662 table a-1 instruction set (cont) (6) branch instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic bcc v=1 2 3 n=0 2 3 n=1 2 3 n ? v=0 ?????? 2 ?????? 3 n ? v=1 ?????? 2 ?????? 3 z (n ? v)=0 ?????? 2 ?????? 3 z (n ? v)=1 ?????? 2 ?????? 3 operation condition code branching condition ihnzvc advanced no. of states * 1 bvs d:8 2 bvs d:16 4 bpl d:8 2 bpl d:16 4 bmi d:8 2 bmi d:16 4 bge d:8 2 bge d:16 4 blt d:8 2 blt d:16 4 bgt d:8 2 bgt d:16 4 ble d:8 2 ble d:16 4
663 table a-1 instruction set (cont) (6) branch instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic jmp bsr jsr rts jmp @ern 2 jmp @aa:24 4 jmp @@aa:8 2 bsr d:8 2 bsr d:16 4 jsr @ern 2 jsr @aa:24 4 jsr @@aa:8 2 rts 2 pc ? ern ?????? 2 pc ? aa:24 ?????? 3 pc ? @aa:8 ?????? 5 pc ? @-sp,pc ? pc+d:8 ?????? 4 pc ? @-sp,pc ? pc+d:16 ?????? 5 pc ? @-sp,pc ? ern ?????? 4 pc ? @-sp,pc ? aa:24 ?????? 5 pc ? @-sp,pc ? @aa:8 ?????? 6 pc ? @sp+ ?????? 5 operation condition code ihnzvc advanced no. of states * 1
664 table a-1 instruction set (7) system control instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic trapa rte sleep ldc trapa #xx:2 rte sleep ldc #xx:8,ccr b 2 ldc #xx:8,exr b 4 ldc rs,ccr b 2 ldc rs,exr b 2 ldc @ers,ccr w 4 ldc @ers,exr w 4 ldc @(d:16,ers),ccr w 6 ldc @(d:16,ers),exr w 6 ldc @(d:32,ers),ccr w 10 ldc @(d:32,ers),exr w 10 ldc @ers+,ccr w 4 ldc @ers+,exr w 4 ldc @aa:16,ccr w 6 ldc @aa:16,exr w 6 ldc @aa:32,ccr w 8 ldc @aa:32,exr w 8 pc ? @-sp,ccr ? @-sp, 1 ????? 8 [9] exr ? @-sp, ? pc exr ? @sp+,ccr ? @sp+, 5 [9] pc ? @sp+ transition to power-down state ?????? 2 #xx:8 ? ccr 1 #xx:8 ? exr ?????? 2 rs8 ? ccr 1 rs8 ? exr ?????? 1 @ers ? ccr 3 @ers ? exr ?????? 3 @(d:16,ers) ? ccr 4 @(d:16,ers) ? exr ?????? 4 @(d:32,ers) ? ccr 6 @(d:32,ers) ? exr ?????? 6 @ers ? ccr,ers32+2 ? ers32 4 @ers ? exr,ers32+2 ? ers32 ?????? 4 @aa:16 ? ccr 4 @aa:16 ? exr ?????? 4 @aa:32 ? ccr 5 @aa:32 ? exr ?????? 5 operation condition code ihnzvc advanced no. of states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
665 table a-1 instruction set (cont) (7) system control instructions (cont) addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic stc andc orc xorc nop stc ccr,rd b 2 stc exr,rd b 2 stc ccr,@erd w 4 stc exr,@erd w 4 stc ccr,@(d:16,erd) w 6 stc exr,@(d:16,erd) w 6 stc ccr,@(d:32,erd) w 10 stc exr,@(d:32,erd) w 10 stc ccr,@-erd w 4 stc exr,@-erd w 4 stc ccr,@aa:16 w 6 stc exr,@aa:16 w 6 stc ccr,@aa:32 w 8 stc exr,@aa:32 w 8 andc #xx:8,ccr b 2 andc #xx:8,exr b 4 orc #xx:8,ccr b 2 orc #xx:8,exr b 4 xorc #xx:8,ccr b 2 xorc #xx:8,exr b 4 nop 2 ccr ? rd8 ?????? 1 exr ? rd8 ?????? 1 ccr ? @erd ?????? 3 exr ? @erd ?????? 3 ccr ? @(d:16,erd) ?????? 4 exr ? @(d:16,erd) ?????? 4 ccr ? @(d:32,erd) ?????? 6 exr ? @(d:32,erd) ?????? 6 erd32-2 ? erd32,ccr ? @erd ?????? 4 erd32-2 ? erd32,exr ? @erd ?????? 4 ccr ? @aa:16 ?????? 4 exr ? @aa:16 ?????? 4 ccr ? @aa:32 ?????? 5 exr ? @aa:32 ?????? 5 ccr #xx:8 ? ccr 1 exr #xx:8 ? exr ?????? 2 ccr #xx:8 ? ccr 1 exr #xx:8 ? exr ?????? 2 ccr ? #xx:8 ? ccr 1 exr ? #xx:8 ? exr ?????? 2 pc ? pc+2 ?????? 1 operation condition code ihnzvc advanced no. of states * 1 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
666 table a-1 instruction set (8) block transfer instructions addressing mode/ instruction length (bytes) operand size #xx rn @ern @(d,ern) @?rn/@ern+ @aa @(d,pc) @@aa mnemonic eepmov notes: 1. the number of states is the number of states required for execution when the instruction and its operands are located i n on-chip memory. 2. n is the initial value of r4l or r4. [1] seven states for saving or restoring two registers, nine states for three registers, or eleven states for four registers. [2] cannot be used in the h8s/2237 series and h8/2227 series. [3] set to 1 when a carry or borrow occurs at bit 11; otherwise cleared to 0. [4] set to 1 when a carry or borrow occurs at bit 27; otherwise cleared to 0. [5] retains its previous value when the result is zero; otherwise cleared to 0. [6] set to 1 when the divisor is negative; otherwise cleared to 0. [7] set to 1 when the divisor is zero; otherwise cleared to 0. [8] set to 1 when the quotient is negative; otherwise cleared to 0. [9] one additional state is required for execution when exr is valid. eepmov.b 4 eepmov.w 4 if r4l 0 4+2n * 2 repeat @er5 ? @er6 er5+1 ? er5 er6+1 ? er6 r4l-1 ? r4l until r4l=0 else next; if r4 - 0 ?????? 4+2n * 2 repeat @er5 ? @er6 er5+1 ? er5 er6+1 ? er6 r4-1 ? r4 until r4=0 else next; operation condition code ihnzvc advanced no. of states * 1
667 a.2 instruction codes table a-2 shows the instruction codes. t able a-2 instruction codes add.b #xx:8,rd add.b rs,rd add.w #xx:16,rd add.w rs,rd add.l #xx:32,erd add.l ers,erd adds #1,erd adds #2,erd adds #4,erd addx #xx:8,rd addx rs,rd and.b #xx:8,rd and.b rs,rd and.w #xx:16,rd and.w rs,rd and.l #xx:32,erd and.l ers,erd andc #xx:8,ccr andc #xx:8,exr band #xx:3,rd band #xx:3,@erd band #xx:3,@aa:8 band #xx:3,@aa:16 band #xx:3,@aa:32 bra d:8 (bt d:8) bra d:16 (bt d:16) brn d:8 (bf d:8) brn d:16 (bf d:16) mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion add adds addx and andc band bcc b b w w l l l l l b b b b w w l l b b b b b b b 1 0 0 ers imm erd 0 0 0 0 0 0 erd erd erd erd erd erd ers imm imm 0 erd 0 imm 0 imm 0 0 0 8 0 7 0 7 0 0 0 0 9 0 e 1 7 6 7 0 0 0 7 7 7 6 6 4 5 4 5 rd 8 9 9 a a b b b rd e rd 6 9 6 a 1 6 1 6 c e a a 0 8 1 8 rd rd rd rd rd rd rd 0 1 rd 0 0 0 0 0 6 0 7 7 6 6 6 6 0 0 76 0 76 0 imm imm imm imm abs disp disp rs 1 rs 1 0 8 9 rs rs 6 rs 6 f 4 1 3 0 1 imm imm abs disp disp imm imm abs imm
668 table a-2 instruction codes (cont) bhi d:8 bhi d:16 bls d:8 bls d:16 bcc d:8 (bhs d:8) bcc d:16 (bhs d:16) bcs d:8 (blo d:8) bcs d:16 (blo d:16) bne d:8 bne d:16 beq d:8 beq d:16 bvc d:8 bvc d:16 bvs d:8 bvs d:16 bpl d:8 bpl d:16 bmi d:8 bmi d:16 bge d:8 bge d:16 blt d:8 blt d:16 bgt d:8 bgt d:16 ble d:8 ble d:16 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bcc 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 2 8 3 8 4 8 5 8 6 8 7 8 8 8 9 8 a 8 b 8 c 8 d 8 e 8 f 8 2 3 4 5 6 7 8 9 a b c d e f disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp 0 0 0 0 0 0 0 0 0 0 0 0 0 0
669 table a-2 instruction codes (cont) bclr #xx:3,rd bclr #xx:3,@erd bclr #xx:3,@aa:8 bclr #xx:3,@aa:16 bclr #xx:3,@aa:32 bclr rn,rd bclr rn,@erd bclr rn,@aa:8 bclr rn,@aa:16 bclr rn,@aa:32 biand #xx:3,rd biand #xx:3,@erd biand #xx:3,@aa:8 biand #xx:3,@aa:16 biand #xx:3,@aa:32 bild #xx:3,rd bild #xx:3,@erd bild #xx:3,@aa:8 bild #xx:3,@aa:16 bild #xx:3,@aa:32 bior #xx:3,rd bior #xx:3,@erd bior #xx:3,@aa:8 bior #xx:3,@aa:16 bior #xx:3,@aa:32 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bclr biand bild bior b b b b b b b b b b b b b b b b b b b b b b b b b 0 0 0 1 0 1 0 1 0 imm erd erd imm erd imm erd imm erd 0 1 1 1 imm imm imm imm 0 1 1 1 imm imm imm imm 7 7 7 6 6 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 2 d f a a 2 d f a a 6 c e a a 7 c e a a 4 c e a a 1 3 rn 1 3 1 3 1 3 1 3 rd 0 8 8 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 0 0 7 7 6 6 7 7 7 7 7 7 2 2 2 2 6 6 7 7 4 4 rn rn 0 0 0 0 0 0 0 0 0 0 7 6 7 7 7 2 2 6 7 4 rn 0 0 0 0 0 7 6 7 7 7 2 2 6 7 4 rn 0 0 0 0 0 abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs 0 0 1 1 1 1 1 1 imm imm imm imm imm imm imm imm
670 table a-2 instruction codes (cont) bist #xx:3,rd bist #xx:3,@erd bist #xx:3,@aa:8 bist #xx:3,@aa:16 bist #xx:3,@aa:32 bixor #xx:3,rd bixor #xx:3,@erd bixor #xx:3,@aa:8 bixor #xx:3,@aa:16 bixor #xx:3,@aa:32 bld #xx:3,rd bld #xx:3,@erd bld #xx:3,@aa:8 bld #xx:3,@aa:16 bld #xx:3,@aa:32 bnot #xx:3,rd bnot #xx:3,@erd bnot #xx:3,@aa:8 bnot #xx:3,@aa:16 bnot #xx:3,@aa:32 bnot rn,rd bnot rn,@erd bnot rn,@aa:8 bnot rn,@aa:16 bnot rn,@aa:32 mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bist bixor bld bnot b b b b b b b b b b b b b b b b b b b b b b b b b 1 0 1 0 0 0 0 0 0 imm erd imm erd imm erd imm erd erd imm imm imm imm imm imm imm imm 1 1 0 0 imm imm imm imm 1 1 0 0 imm imm imm imm 1 1 1 1 0 0 0 0 6 7 7 6 6 7 7 7 6 6 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 7 d f a a 5 c e a a 7 c e a a 1 d f a a 1 d f a a 1 3 1 3 1 3 1 3 rn 1 3 rd 0 8 8 rd 0 0 0 rd 0 0 0 rd 0 8 8 rd 0 8 8 6 6 7 7 7 7 7 7 6 6 7 7 5 5 7 7 1 1 1 1 rn rn 0 0 0 0 0 0 0 0 0 0 6 7 7 7 6 7 5 7 1 1rn 0 0 0 0 0 6 7 7 7 6 7 5 7 1 1rn 0 0 0 0 0 abs abs abs abs abs abs abs abs abs abs abs abs abs abs abs
671 table a-2 instruction codes (cont) bor #xx:3,rd bor #xx:3,@erd bor #xx:3,@aa:8 bor #xx:3,@aa:16 bor #xx:3,@aa:32 bset #xx:3,rd bset #xx:3,@erd bset #xx:3,@aa:8 bset #xx:3,@aa:16 bset #xx:3,@aa:32 bset rn,rd bset rn,@erd bset rn,@aa:8 bset rn,@aa:16 bset rn,@aa:32 bsr d:8 bsr d:16 bst #xx:3,rd bst #xx:3,@erd bst #xx:3,@aa:8 bst #xx:3,@aa:16 bst #xx:3,@aa:32 btst #xx:3,rd btst #xx:3,@erd btst #xx:3,@aa:8 btst #xx:3,@aa:16 btst #xx:3,@aa:32 btst rn,rd btst rn,@erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion bor bset bsr bst btst b b b b b b b b b b b b b b b b b b b b b b b b b b b 0 0 0 0 0 0 0 0 0 0 imm erd imm erd erd imm erd imm erd erd abs abs abs disp abs abs imm imm imm imm imm imm imm imm 0 0 0 0 imm imm imm imm 0 0 0 0 imm imm imm imm 0 0 0 0 0 0 0 0 7 7 7 6 6 7 7 7 6 6 6 7 7 6 6 5 5 6 7 7 6 6 7 7 7 6 6 6 7 4 c e a a 0 d f a a 0 d f a a 5 c 7 d f a a 3 c e a a 3 c 1 3 1 3 rn 1 3 0 1 3 1 3 rn rd 0 0 0 rd 0 8 8 rd 0 8 8 0 rd 0 8 8 rd 0 0 0 rd 0 7 7 7 7 6 6 6 6 7 7 6 4 4 0 0 0 0 7 7 3 3 3 rn rn rn 0 0 0 0 0 0 0 0 0 0 0 7 7 6 6 7 4 0 0 7 3 rn 0 0 0 0 0 7 7 6 6 7 4 0 0 7 3 rn 0 0 0 0 0 abs abs abs disp abs abs abs abs abs abs abs
672 table a-2 instruction codes (cont) btst rn,@aa:8 btst rn,@aa:16 btst rn,@aa:32 bxor #xx:3,rd bxor #xx:3,@erd bxor #xx:3,@aa:8 bxor #xx:3,@aa:16 bxor #xx:3,@aa:32 clrmac cmp.b #xx:8,rd cmp.b rs,rd cmp.w #xx:16,rd cmp.w rs,rd cmp.l #xx:32,erd cmp.l ers,erd daa rd das rd dec.b rd dec.w #1,rd dec.w #2,rd dec.l #1,erd dec.l #2,erd divxs.b rs,rd divxs.w rs,erd divxu.b rs,rd divxu.w rs,erd eepmov.b eepmov.w mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion btst bxor clrmac cmp daa das dec divxs divxu eepmov b b b b b b b b b b w w l l b b b w w l l b w b w 0 0 1 imm erd ers 0 0 0 0 0 erd erd erd erd erd imm imm 0 erd 0 imm 0 imm 0 0 7 6 6 7 7 7 6 6 a 1 7 1 7 1 0 1 1 1 1 1 1 0 0 5 5 7 7 e a a 5 c e a a rd c 9 d a f f f a b b b b 1 1 1 3 b b 1 3 1 3 rs 2 rs 2 0 0 0 5 d 7 f d d rs rs 5 d 0 0 rd 0 0 0 rd rd rd rd rd rd rd rd 0 0 rd c 4 6 7 7 5 5 5 5 3 5 5 1 3 9 9 rn rs rs 8 8 0 0 0 rd f f 6 7 3 5 rn 0 0 6 7 3 5 rn 0 0 abs abs imm abs abs imm abs abs imm cannot be used in the h8s/2237 series and h8s/2227 series.
673 table a-2 instruction codes (cont) exts.w rd exts.l erd extu.w rd extu.l erd inc.b rd inc.w #1,rd inc.w #2,rd inc.l #1,erd inc.l #2,erd jmp @ern jmp @aa:24 jmp @@aa:8 jsr @ern jsr @aa:24 jsr @@aa:8 ldc #xx:8,ccr ldc #xx:8,exr ldc rs,ccr ldc rs,exr ldc @ers,ccr ldc @ers,exr ldc @(d:16,ers),ccr ldc @(d:16,ers),exr ldc @(d:32,ers),ccr ldc @(d:32,ers),exr ldc @ers+,ccr ldc @ers+,exr ldc @aa:16,ccr ldc @aa:16,exr mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion exts extu inc jmp jsr ldc w l w l b w w l l b b b b w w w w w w w w w w 0 0 ern ern 0 0 0 0 erd erd erd erd ers ers ers ers ers ers ers ers 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 5 5 5 5 5 5 0 0 0 0 0 0 0 0 0 0 0 0 0 0 7 7 7 7 a b b b b 9 a b d e f 7 1 3 3 1 1 1 1 1 1 1 1 1 1 d f 5 7 0 5 d 7 f 4 0 1 4 4 4 4 4 4 4 4 4 4 rd rd rd rd rd 0 0 1 rs rs 0 1 0 1 0 1 0 1 0 1 0 6 6 6 6 7 7 6 6 6 6 7 9 9 f f 8 8 d d b b 0 0 0 0 0 0 0 0 0 0 0 0 6 6 b b 2 2 0 0 abs abs abs abs imm imm disp disp abs abs disp disp
674 0 0 rd abs rs rd table a-2 instruction codes (cont) ldc @aa:32,ccr ldc @aa:32,exr ldm.l @sp+, (ern-ern+1) ldm.l @sp+, (ern-ern+2) ldm.l @sp+, (ern-ern+3) ldmac ers,mach ldmac ers,macl mac @ern+,@erm+ mov.b #xx:8,rd mov.b rs,rd mov.b @ers,rd mov.b @(d:16,ers),rd mov.b @(d:32,ers),rd mov.b @ers+,rd mov.b @aa:8,rd mov.b @aa:16,rd mov.b @aa:32,rd mov.b rs,@erd mov.b rs,@(d:16,erd) mov.b rs,@(d:32,erd) mov.b rs,@-erd mov.b rs,@aa:8 mov.b rs,@aa :16 mov.b rs,@aa:32 mov.w #xx:16,rd mov.w rs,rd mov.w @ers,rd mov.w @(d:16,ers),rd mov.w @(d:32,ers),rd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion ldc ldm ldmac mac mov w w l l l l l b b b b b b b b b b b b b b b b w w w w w 0 0 0 0 1 1 0 1 0 0 0 ers ers ers ers erd erd erd erd ers ers ers 0 0 0 ern+1 ern+2 ern+3 0 0 0 0 0 f 0 6 6 7 6 2 6 6 6 6 7 6 3 6 6 7 0 6 6 7 1 1 1 1 1 rd c 8 e 8 c rd a a 8 e 8 c rs a a 9 d 9 f 8 4 4 1 2 3 rs 0 2 8 a 0 rs 0 1 0 0 0 rd rd rd 0 rd rd rd rs rs 0 rs rs rs rd rd rd rd 0 6 6 6 6 6 6 6 6 b b d d d a a b 2 2 7 7 7 2 a 2 imm abs abs disp abs disp abs imm disp abs abs abs abs disp disp disp cannot be used in the h8s/2237 and h8s/2227 series
675 table a-2 instruction codes (cont) mov.w @ers+,rd mov.w @aa:16,rd mov.w @aa:32,rd mov.w rs,@erd mov.w rs,@(d:16,erd) mov.w rs,@(d:32,erd) mov.w rs,@-erd mov.w rs,@aa:16 mov.w rs,@aa:32 mov.l #xx:32,rd mov.l ers,erd mov.l @ers,erd mov.l @(d:16,ers),erd mov.l @(d:32,ers),erd mov.l @ers+,erd mov.l @aa:16 ,erd mov.l @aa:32 ,erd mov.l ers,@erd mov.l ers,@(d:16,erd) mov.l ers,@(d:32,erd) * mov.l ers,@-erd mov.l ers,@aa:16 mov.l ers,@aa:32 movfpe @aa:16,rd movtpe rs,@aa:16 mulxs.b rs,rd mulxs.w rs,erd mulxu.b rs,rd mulxu.w rs,erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion mov movfpe movtpe mulxs mulxu w w w w w w w w w l l l l l l l l l l l l l l b b b w b w 0 1 1 0 1 1 ers erd erd erd erd ers 0 0 0 erd erd erd ers ers ers ers erd erd erd erd 0 0 0 0 0 0 0 0 0 0 0 erd erd erd erd erd ers ers ers ers ers erd 0 0 erd ers 0 0 0 0 1 1 0 1 6 6 6 6 6 7 6 6 6 7 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 5 5 d b b 9 f 8 d b b a f 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 2 0 2 8 a 0 0 0 0 0 0 0 0 0 0 0 0 0 c c rs rs rd rd rd rs rs 0 rs rs rs 0 0 0 0 0 0 0 0 0 0 0 0 0 0 rd 6 6 6 7 6 6 6 6 6 7 6 6 6 5 5 b 9 f 8 d b b 9 f 8 d b b 0 2 a 0 2 8 a rs rs rs 0 0 rd 6 6 b b 2 a abs disp abs abs abs imm disp abs disp abs disp abs abs cannot be used in the h8s/2237 and h8s/2227 series disp disp
676 table a-2 instruction codes (cont) neg.b rd neg.w rd neg.l erd nop not.b rd not.w rd not.l erd or.b #xx:8,rd or.b rs,rd or.w #xx:16,rd or.w rs,rd or.l #xx:32,erd or.l ers,erd orc #xx:8,ccr orc #xx:8,exr pop.w rn pop.l ern push.w rn push.l ern rotl.b rd rotl.b #2, rd rotl.w rd rotl.w #2, rd rotl.l erd rotl.l #2, erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion neg nop not or orc pop push rotl b w l b w l b b w w l l b b w l w l b b w w l l 0 0 0 0 0 erd erd erd erd erd 1 1 1 0 1 1 1 c 1 7 6 7 0 0 0 6 0 6 0 1 1 1 1 1 1 7 7 7 0 7 7 7 rd 4 9 4 a 1 4 1 d 1 d 1 2 2 2 2 2 2 8 9 b 0 0 1 3 rs 4 rs 4 f 4 7 0 f 0 8 c 9 d b f rd rd 0 rd rd rd rd rd 0 1 rn 0 rn 0 rd rd rd rd imm imm 6 0 6 6 4 4 d d ers 0 0 0 erd ern ern 0 7 f imm imm imm
677 table a-2 instruction codes (cont) rotr.b rd rotr.b #2, rd rotr.w rd rotr.w #2, rd rotr.l erd rotr.l #2, erd rotxl.b rd rotxl.b #2, rd rotxl.w rd rotxl.w #2, rd rotxl.l erd rotxl.l #2, erd rotxr.b rd rotxr.b #2, rd rotxr.w rd rotxr.w #2, rd rotxr.l erd rotxr.l #2, erd rte rts shal.b rd shal.b #2, rd shal.w rd shal.w #2, rd shal.l erd shal.l #2, erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion rotr rotxl rotxr rte rts shal b b w w l l b b w w l l b b w w l l b b w w l l 0 0 0 0 0 0 0 0 erd erd erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 5 5 1 1 1 1 1 1 3 3 3 3 3 3 2 2 2 2 2 2 3 3 3 3 3 3 6 4 0 0 0 0 0 0 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 7 7 8 c 9 d b f rd rd rd rd rd rd rd rd rd rd rd rd 0 0 rd rd rd rd
678 table a-2 instruction codes (cont) shar.b rd shar.b #2, rd shar.w rd shar.w #2, rd shar.l erd shar.l #2, erd shll.b rd shll.b #2, rd shll.w rd shll.w #2, rd shll.l erd shll.l #2, erd shlr.b rd shlr.b #2, rd shlr.w rd shlr.w #2, rd shlr.l erd shlr.l #2, erd sleep stc.b ccr,rd stc.b exr,rd stc.w ccr,@erd stc.w exr,@erd stc.w ccr,@(d:16,erd) stc.w exr,@(d:16,erd) stc.w ccr,@(d:32,erd) stc.w exr,@(d:32,erd) stc.w ccr,@-erd stc.w exr,@-erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion shar shll shlr sleep stc b b w w l l b b w w l l b b w w l l b b w w w w w w w w 0 0 0 0 0 0 erd erd erd erd erd erd 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 1 8 c 9 d b f 0 4 1 5 3 7 0 4 1 5 3 7 8 0 1 4 4 4 4 4 4 4 4 rd rd rd rd rd rd rd rd rd rd rd rd 0 rd rd 0 1 0 1 0 1 0 1 erd erd erd erd erd erd erd erd 1 1 1 1 0 0 1 1 6 6 6 6 7 7 6 6 9 9 f f 8 8 d d 0 0 0 0 0 0 0 0 6 6 b b a a 0 0 disp disp disp disp
679 table a-2 instruction codes (cont) stc.w ccr,@aa:16 stc.w exr,@aa:16 stc.w ccr,@aa:32 stc.w exr,@aa:32 stm.l(ern-ern+1), @-sp stm.l (ern-ern+2), @-sp stm.l (ern-ern+3), @-sp stmac mach,erd stmac macl,erd sub.b rs,rd sub.w #xx:16,rd sub.w rs,rd sub.l #xx:32,erd sub.l ers,erd subs #1,erd subs #2,erd subs #4,erd subx #xx:8,rd subx rs,rd tas @erd trapa #x:2 xor.b #xx:8,rd xor.b rs,rd xor.w #xx:16,rd xor.w rs,rd xor.l #xx:32,erd xor.l ers,erd mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion stc stm stmac sub subs subx tas trapa xor w w w w l l l l l b w w l l l l l b b b b b w w l l 1 00 ers imm 0 0 0 0 0 0 erd erd erd erd erd erd erd ers 0 0 0 0 ern ern ern erd 0 0 0 0 0 0 0 0 0 1 7 1 7 1 1 1 1 b 1 0 5 d 1 7 6 7 0 1 1 1 1 1 1 1 8 9 9 a a b b b rd e 1 7 rd 5 9 5 a 1 4 4 4 4 1 2 3 rs 3 rs 3 0 8 9 rs e rs 5 rs 5 f 0 1 0 1 0 0 0 rd rd rd rd 0 0 rd rd rd 0 6 6 6 6 6 6 6 7 6 b b b b d d d b 5 8 8 a a f f f 0 0 0 0 c abs abs abs abs imm imm imm imm imm imm cannot be used in the h8s/2237 and h8s/2227 series
680 table a-2 instruction codes (cont) xorc #xx:8,ccr xorc #xx:8,exr mnemonic size instruction format 1st byte 2nd byte 3rd byte 4th byte 5th byte 6th byte 7th byte 8th byte 9th byte 10th byte instruc- tion xorc b b 0 0 5 1 4 1 0 5 imm imm note: bit 7 of the 4th byte of the mov.l ers, @(d:32,erd) instruction can be either 1 or 0. legend address register 32-bit register register field general register register field general register register field general register 000 001 111 er0 er1 er7 0000 0001 0111 1000 1001 1111 r0 r1 r7 e0 e1 e7 0000 0001 0111 1000 1001 1111 r0h r1h r7h r0l r1l r7l 16-bit register 8-bit register imm: abs: disp: rs, rd, rn: ers, erd, ern, erm: the register fields specify general registers as follows. immediate data (2, 3, 8, 16, or 32 bits) absolute address (8, 16, 24, or 32 bits) displacement (8, 16, or 32 bits) register field (4 bits specifying an 8-bit or 16-bit register. the symbols rs, rd, and rn correspond to operand symbols rs, rd, and rn.) register field (3 bits specifying an address register or 32-bit register. the symbols ers, erd, ern, and erm correspond to oper and symbols ers, erd, ern, and erm.) *
681 a.3 operation code map table a-3 shows the operation code map. instruction code 1st byte 2nd byte ah al bh bl instruction when most significant bit of bh is 0. instruction when most significant bit of bh is 1. 0 nop bra mulxu bset ah note: * cannot be used in the h8s/2237 series and h8s/2227 series. al 0 1 2 3 4 5 6 7 8 9 a b c d e f 1 brn divxu bnot 2 bhi mulxu bclr 3 bls divxu btst stc stmac ldc ldmac 4 orc or bcc rts or bor bior 6 andc and bne rte and 5 xorc xor bcs bsr xor bxor bixor band biand 7 ldc beq trapa bst bist bld bild 8 bvc mov 9 bvs a bpl jmp b bmi eepmov c bge bsr d blt mov e addx subx bgt jsr f ble mov.b add addx cmp subx or xor and mov add sub mov mov cmp table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(2) table a.3(3) table a-3 operation code map (1) **
682 instruction code 1st byte 2nd byte ah al bh bl 01 0a 0b 0f 10 11 12 13 17 1a 1b 1f 58 6a 79 7a 0 mov inc adds daa dec subs das bra mov mov mov shll shlr rotxl rotxr not 1 ldm brn add add 2 bhi mov cmp cmp 3 stm not bls sub sub 4 shll shlr rotxl rotxr bcc movfpe * or or 5 inc extu dec bcs xor xor 6 mac bne and and 7 inc shll shlr rotxl rotxr extu dec beq ldc stc 8 sleep bvc mov adds shal shar rotl rotr neg subs 9 bvs a clrmac bpl mov b neg bmi add mov sub cmp c shal shar rotl rotr bge movtpe * d inc exts dec blt e tas bgt f inc shal shar rotl rotr exts dec ble bh ah al table a.3(3) table a.3(3) table a.3(3) table a.3(4) table a.3(4) table a-3 operation code map (2) * * note: * cannot be used in the h8s/2237 series and h8s/2227 series.
683 instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl r is the register specification field. aa is the absolute address specification. instruction when most significant bit of dh is 0. instruction when most significant bit of dh is 1. notes: ah al bh bl ch cl 01c05 01d05 01f06 7cr06 * 1 7cr07 * 1 7dr06 * 1 7dr07 * 1 7eaa6 * 2 7eaa7 * 2 7faa6 * 2 7faa7 * 2 0 mulxs bset bset bset bset 1 divxs bnot bnot bnot bnot 2 mulxs bclr bclr bclr bclr 3 divxs btst btst btst btst 4 or 5 xor 6 and 789abcdef 1. 2. bor bior bxor bixor band biand bld bild bst bist bor bior bxor bixor band biand bld bild bst bist table a-3 operation code map (3)
684 instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl instruction when most significant bit of fh is 0. instruction when most significant bit of fh is 1. 5th byte 6th byte eh el fh fl instruction code 1st byte 2nd byte ah al bh bl 3rd byte 4th byte ch cl dh dl instruction when most significant bit of hh is 0. instruction when most significant bit of hh is 1. note: * aa is the absolute address specification. 5th byte 6th byte eh el fh fl 7th byte 8th byte gh gl hh hl 6a10aaaa6 * 6a10aaaa7 * 6a18aaaa6 * 6a18aaaa7 * ahalbhblchcldhdleh el 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef 6a30aaaaaaaa6 * 6a30aaaaaaaa7 * 6a38aaaaaaaa6 * 6a38aaaaaaaa7 * ahalbhbl ... fhflgh gl 0 bset 1 bnot 2 bclr 3 btst bor bior bxor bixor band biand bld bild bst bist 456789abcdef table a-3 operation code map (4)
685 a.4 number of states required for instruction execution the tables in this section can be used to calculate the number of states required for instruction execution by the h8s/2000 cpu. table a-5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. table a-4 indicates the number of states required for each cycle, depending on its size. the number of states required for execution of an instruction can be calculated from these two tables as follows: execution states = i s i + j s j + k s k + l s l + m s m + n s n examples: advanced mode, program code and stack located in external memory, on-chip supporting modules accessed in two states with 8-bit bus width, external devices accessed in three states with one wait state and 16-bit bus width. 1. bset #0, @ffffb3:8 from table a-5: i = l = 2, j = k = m = n = 0 from table a-4: s i = 4, s l = 2 number of states required for execution = 2 4 + 2 2 = 12 2. jsr @@30 from table a-5: i = j = k = 2, l = m = n = 0 from table a-4: s i = s j = s k = 4 number of states required for execution = 2 4 + 2 4 + 2 4 = 24
686 table a-4 number of states per cycle access conditions on-chip supporting external device module 8-bit bus 16-bit bus cycle on-chip memory 8-bit bus 16-bit bus 2-state access 3-state access 2-state access 3-state access instruction fetch s i 1 4 2 4 6 + 2m 2 3 + m branch address read s j stack operation s k byte data access s l 2 2 3 + m word data access s m 4 4 6 + 2m internal operation s n 11 1 1111 legend m: number of wait states inserted into external device access
687 table a-5 number of cycles in instruction execution instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n add add.b #xx:8,rd 1 add.b rs,rd 1 add.w #xx:16,rd 2 add.w rs,rd 1 add.l #xx:32,erd 3 add.l ers,erd 1 adds adds #1/2/4,erd 1 addx addx #xx:8,rd 1 addx rs,rd 1 and and.b #xx:8,rd 1 and.b rs,rd 1 and.w #xx:16,rd 2 and.w rs,rd 1 and.l #xx:32,erd 3 and.l ers,erd 2 andc andc #xx:8,ccr 1 andc #xx:8,exr 2 band band #xx:3,rd 1 band #xx:3,@erd 2 1 band #xx:3,@aa:8 2 1 band #xx:3,@aa:16 3 1 band #xx:3,@aa:32 4 1 bcc bra d:8 (bt d:8) 2 brn d:8 (bf d:8) 2 bhi d:8 2 bls d:8 2 bcc d:8 (bhs d:8) 2 bcs d:8 (blo d:8) 2 bne d:8 2 beq d:8 2 bvc d:8 2 bvs d:8 2 bpl d:8 2
688 table a-5 number of cycles in instruction execution (cont) instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bcc bmi d:8 2 bge d:8 2 blt d:8 2 bgt d:8 2 ble d:8 2 bra d:16 (bt d:16) 2 1 brn d:16 (bf d:16) 2 1 bhi d:16 2 1 bls d:16 2 1 bcc d:16 (bhs d:16) 2 1 bcs d:16 (blo d:16) 2 1 bne d:16 2 1 beq d:16 2 1 bvc d:16 2 1 bvs d:16 2 1 bpl d:16 2 1 bmi d:16 2 1 bge d:16 2 1 blt d:16 2 1 bgt d:16 2 1 ble d:16 2 1 bclr bclr #xx:3,rd 1 bclr #xx:3,@erd 2 2 bclr #xx:3,@aa:8 2 2 bclr #xx:3,@aa:16 3 2 bclr #xx:3,@aa:32 4 2 bclr rn,rd 1 bclr rn,@erd 2 2 bclr rn,@aa:8 2 2 bclr rn,@aa:16 3 2 bclr rn,@aa:32 4 2
689 table a-5 number of cycles in instruction execution (cont) instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n biand biand #xx:3,rd 1 biand #xx:3,@erd 2 1 biand #xx:3,@aa:8 2 1 biand #xx:3,@aa:16 3 1 biand #xx:3,@aa:32 4 1 bild bild #xx:3,rd 1 bild #xx:3,@erd 2 1 bild #xx:3,@aa:8 2 1 bild #xx:3,@aa:16 3 1 bild #xx:3,@aa:32 4 1 bior bior #xx:8,rd 1 bior #xx:8,@erd 2 1 bior #xx:8,@aa:8 2 1 bior #xx:8,@aa:16 3 1 bior #xx:8,@aa:32 4 1 bist bist #xx:3,rd 1 bist #xx:3,@erd 2 2 bist #xx:3,@aa:8 2 2 bist #xx:3,@aa:16 3 2 bist #xx:3,@aa:32 4 2 bixor bixor #xx:3,rd 1 bixor #xx:3,@erd 2 1 bixor #xx:3,@aa:8 2 1 bixor #xx:3,@aa:16 3 1 bixor #xx:3,@aa:32 4 1 bld bld #xx:3,rd 1 bld #xx:3,@erd 2 1 bld #xx:3,@aa:8 2 1 bld #xx:3,@aa:16 3 1 bld #xx:3,@aa:32 4 1
690 table a-5 number of cycles in instruction execution (cont) instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n bnot bnot #xx:3,rd 1 bnot #xx:3,@erd 2 2 bnot #xx:3,@aa:8 2 2 bnot #xx:3,@aa:16 3 2 bnot #xx:3,@aa:32 4 2 bnot rn,rd 1 bnot rn,@erd 2 2 bnot rn,@aa:8 2 2 bnot rn,@aa:16 3 2 bnot rn,@aa:32 4 2 bor bor #xx:3,rd 1 bor #xx:3,@erd 2 1 bor #xx:3,@aa:8 2 1 bor #xx:3,@aa:16 3 1 bor #xx:3,@aa:32 4 1 bset bset #xx:3,rd 1 bset #xx:3,@erd 2 2 bset #xx:3,@aa:8 2 2 bset #xx:3,@aa:16 3 2 bset #xx:3,@aa:32 4 2 bset rn,rd 1 bset rn,@erd 2 2 bset rn,@aa:8 2 2 bset rn,@aa:16 3 2 bset rn,@aa:32 4 2 bsr bsr d:8 2 2 bsr d:16 2 2 1 bst bst #xx:3,rd 1 bst #xx:3,@erd 2 2 bst #xx:3,@aa:8 2 2 bst #xx:3,@aa:16 3 2 bst #xx:3,@aa:32 4 2
691 table a-5 number of cycles in instruction execution (cont) instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n btst btst #xx:3,rd 1 btst #xx:3,@erd 2 1 btst #xx:3,@aa:8 2 1 btst #xx:3,@aa:16 3 1 btst #xx:3,@aa:32 4 1 btst rn,rd 1 btst rn,@erd 2 1 btst rn,@aa:8 2 1 btst rn,@aa:16 3 1 btst rn,@aa:32 4 1 bxor bxor #xx:3,rd 1 bxor #xx:3,@erd 2 1 bxor #xx:3,@aa:8 2 1 bxor #xx:3,@aa:16 3 1 bxor #xx:3,@aa:32 4 1 clrmac clrmac cannot be used in the h8s/2237 series and h8s/2227 series cmp cmp.b #xx:8,rd 1 cmp.b rs,rd 1 cmp.w #xx:16,rd 2 cmp.w rs,rd 1 cmp.l #xx:32,erd 3 cmp.l ers,erd 1 daa daa rd 1 das das rd 1 dec dec.b rd 1 dec.w #1/2,rd 1 dec.l #1/2,erd 1 divxs divxs.b rs,rd 2 11 divxs.w rs,erd 2 19 divxu divxu.b rs,rd 1 11 divxu.w rs,erd 1 19
692 table a-5 number of cycles in instruction execution (cont) instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n eepmov eepmov.b 2 2n+2 * 2 eepmov.w 2 2n+2 * 2 exts exts.w rd 1 exts.l erd 1 extu extu.w rd 1 extu.l erd 1 inc inc.b rd 1 inc.w #1/2,rd 1 inc.l #1/2,erd 1 jmp jmp @ern 2 jmp @aa:24 2 1 jmp @@aa:8 2 2 1 jsr jsr @ern 2 2 jsr @aa:24 2 2 1 jsr @@aa:8 2 2 2 ldc ldc #xx:8,ccr 1 ldc #xx:8,exr 2 ldc rs,ccr 1 ldc rs,exr 1 ldc @ers,ccr 2 1 ldc @ers,exr 2 1 ldc @(d:16,ers),ccr 3 1 ldc @(d:16,ers),exr 3 1 ldc @(d:32,ers),ccr 5 1 ldc @(d:32,ers),exr 5 1 ldc @ers+,ccr 2 1 1 ldc @ers+,exr 2 1 1 ldc @aa:16,ccr 3 1 ldc @aa:16,exr 3 1 ldc @aa:32,ccr 4 1 ldc @aa:32,exr 4 1
693 table a-5 number of cycles in instruction execution (cont) instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n ldm ldm.l @sp+, (ern-ern+1) 24 1 ldm.l @sp+, (ern-ern+2) 26 1 ldm.l @sp+, (ern-ern+3) 28 1 ldmac ldmac ers,mach cannot be used in the h8s/2237 series and h8s/2227 series ldmac ers,macl mac mac @ern+,@erm+ cannot be used in the h8s/2237 series and h8s/2227 series mov mov.b #xx:8,rd 1 mov.b rs,rd 1 mov.b @ers,rd 1 1 mov.b @(d:16,ers),rd 2 1 mov.b @(d:32,ers),rd 4 1 mov.b @ers+,rd 1 1 1 mov.b @aa:8,rd 1 1 mov.b @aa:16,rd 2 1 mov.b @aa:32,rd 3 1 mov.b rs,@erd 1 1 mov.b rs,@(d:16,erd) 2 1 mov.b rs,@(d:32,erd) 4 1 mov.b rs,@-erd 1 1 1 mov.b rs,@aa:8 1 1 mov.b rs,@aa:16 2 1 mov.b rs,@aa:32 3 1 mov.w #xx:16,rd 2 mov.w rs,rd 1 mov.w @ers,rd 1 1 mov.w @(d:16,ers),rd 2 1 mov.w @(d:32,ers),rd 4 1 mov.w @ers+,rd 1 1 1 mov.w @aa:16,rd 2 1 mov.w @aa:32,rd 3 1 mov.w rs,@erd 1 1
694 table a-5 number of cycles in instruction execution (cont) instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n mov mov.w rs,@(d:16,erd) 2 1 mov.w rs,@(d:32,erd) 4 1 mov.w rs,@-erd 1 1 1 mov.w rs,@aa:16 2 1 mov.w rs,@aa:32 3 1 mov.l #xx:32,erd 3 mov.l ers,erd 1 mov.l @ers,erd 2 2 mov.l @(d:16,ers),erd 3 2 mov.l @(d:32,ers),erd 5 2 mov.l @ers+,erd 2 2 1 mov.l @aa:16,erd 3 2 mov.l @aa:32,erd 4 2 mov.l ers,@erd 2 2 mov.l ers,@(d:16,erd) 3 2 mov.l ers,@(d:32,erd) 5 2 mov.l ers,@-erd 2 2 1 mov.l ers,@aa:16 3 2 mov.l ers,@aa:32 4 2 movfpe movfpe @:aa:16,rd can not be used in the h8s/2237 series and h8s/2227 series movtpe movtpe rs,@:aa:16 mulxs mulxs.b rs,rd 2 11 mulxs.w rs,erd 2 19 mulxu mulxu.b rs,rd 1 11 mulxu.w rs,erd 1 19 neg neg.b rd 1 neg.w rd 1 neg.l erd 1 nop nop 1 not not.b rd 1 not.w rd 1 not.l erd 1
695 table a-5 number of cycles in instruction execution (cont) instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n or or.b #xx:8,rd 1 or.b rs,rd 1 or.w #xx:16,rd 2 or.w rs,rd 1 or.l #xx:32,erd 3 or.l ers,erd 2 orc orc #xx:8,ccr 1 orc #xx:8,exr 2 pop pop.w rn 1 1 1 pop.l ern 2 2 1 push push.w rn 1 1 1 push.l ern 2 2 1 rotl rotl.b rd 1 rotl.b #2,rd 1 rotl.w rd 1 rotl.w #2,rd 1 rotl.l erd 1 rotl.l #2,erd 1 rotr rotr.b rd 1 rotr.b #2,rd 1 rotr.w rd 1 rotr.w #2,rd 1 rotr.l erd 1 rotr.l #2,erd 1 rotxl rotxl.b rd 1 rotxl.b #2,rd 1 rotxl.w rd 1 rotxl.w #2,rd 1 rotxl.l erd 1 rotxl.l #2,erd 1
696 table a-5 number of cycles in instruction execution (cont) instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n rotxr rotxr.b rd 1 rotxr.b #2,rd 1 rotxr.w rd 1 rotxr.w #2,rd 1 rotxr.l erd 1 rotxr.l #2,erd 1 rte rte 2 2/3 * 1 1 rts rts 2 2 1 shal shal.b rd 1 shal.b #2,rd 1 shal.w rd 1 shal.w #2,rd 1 shal.l erd 1 shal.l #2,erd 1 shar shar.b rd 1 shar.b #2,rd 1 shar.w rd 1 shar.w #2,rd 1 shar.l erd 1 shar.l #2,erd 1 shll shll.b rd 1 shll.b #2,rd 1 shll.w rd 1 shll.w #2,rd 1 shll.l erd 1 shll.l #2,erd 1 shlr shlr.b rd 1 shlr.b #2,rd 1 shlr.w rd 1 shlr.w #2,rd 1 shlr.l erd 1 shlr.l #2,erd 1 sleep sleep 1 1
697 table a-5 number of cycles in instruction execution (cont) instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n stc stc.b ccr,rd 1 stc.b exr,rd 1 stc.w ccr,@erd 2 1 stc.w exr,@erd 2 1 stc.w ccr,@(d:16,erd) 3 1 stc.w exr,@(d:16,erd) 3 1 stc.w ccr,@(d:32,erd) 5 1 stc.w exr,@(d:32,erd) 5 1 stc.w ccr,@-erd 2 1 1 stc.w exr,@-erd 2 1 1 stc.w ccr,@aa:16 3 1 stc.w exr,@aa:16 3 1 stc.w ccr,@aa:32 4 1 stc.w exr,@aa:32 4 1 stm stm.l (ern-ern+1), @-sp 24 1 stm.l (ern-ern+2), @-sp 26 1 stm.l (ern-ern+3), @-sp 28 1 stmac stmac mach,erd cannot be used in the h8s/2237 series and h8s/2227 series stmac macl,erd sub sub.b rs,rd 1 sub.w #xx:16,rd 2 sub.w rs,rd 1 sub.l #xx:32,erd 3 sub.l ers,erd 1 subs subs #1/2/4,erd 1 subx subx #xx:8,rd 1 subx rs,rd 1 tas tas @erd 2 2 trapa trapa #x:2 2 2 2/3 * 1 2
698 table a-5 number of cycles in instruction execution (cont) instruction fetch branch address read stack operation byte data access word data access internal operation instruction mnemonic i j k l m n xor xor.b #xx:8,rd 1 xor.b rs,rd 1 xor.w #xx:16,rd 2 xor.w rs,rd 1 xor.l #xx:32,erd 3 xor.l ers,erd 2 xorc xorc #xx:8,ccr 1 xorc #xx:8,exr 2 notes: 1. 2 when exr is invalid, 3 when exr is valid. 2. when n bytes of data are transferred.
699 a.5 bus states during instruction execution table a-6 indicates the types of cycles that occur during instruction execution by the cpu. see table a-4 for the number of states per cycle. how to read the table: instruction jmp@aa:24 r:w 2nd internal operation 1 state r:w ea 1 2345678 end of instruction order of execution read effective address (word-size read) no read or write read 2nd word of current instruction (word-size read) legend r:b byte-size read r:w word-size read w:b byte-size write w:w word-size write :m transfer of the bus is not performed immediately after this cycle 2nd address of 2nd word (3rd and 4th bytes) 3rd address of 3rd word (5th and 6th bytes) 4th address of 4th word (7th and 8th bytes) 5th address of 5th word (9th and 10th bytes) next address of next instruction ea effective address vec vector address
700 figure a-1 shows timing waveforms for the address bus and the rd , hwr , and lwr signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. address bus rd hwr , lwr r:w 2nd fetching 2nd byte of instruction at jump address fetching 1nd byte of instruction at jump address fetching 4th byte of instruction fetching 3rd byte of instruction r:w ea high level internal operation figure a-1 address bus, rd , hwr , and lwr timing (8-bit bus, three-state access, no wait states)
701 instruction add.b #xx:8,rd r:w next add.b rs,rd r:w next add.w #xx:16,rd r:w 2nd r:w next add.w rs,rd r:w next add.l #xx:32,erd r:w 2nd r:w 3rd r:w next add.l ers,erd r:w next adds #1/2/4,erd r:w next addx #xx:8,rd r:w next addx rs,rd r:w next and.b #xx:8,rd r:w next and.b rs,rd r:w next and.w #xx:16,rd r:w 2nd r:w next and.w rs,rd r:w next and.l #xx:32,erd r:w 2nd r:w 3rd r:w next and.l ers,erd r:w 2nd r:w next andc #xx:8,ccr r:w next andc #xx:8,exr r:w 2nd r:w next band #xx:3,rd r:w next band #xx:3,@erd r:w 2nd r:b ea r:w:m next band #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next band #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next band #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bra d:8 (bt d:8) r:w next r:w ea brn d:8 (bf d:8) r:w next r:w ea bhi d:8 r:w next r:w ea bls d:8 r:w next r:w ea bcc d:8 (bhs d:8) r:w next r:w ea bcs d:8 (blo d:8) r:w next r:w ea bne d:8 r:w next r:w ea beq d:8 r:w next r:w ea bvc d:8 r:w next r:w ea bvs d:8 r:w next r:w ea bpl d:8 r:w next r:w ea bmi d:8 r:w next r:w ea bge d:8 r:w next r:w ea blt d:8 r:w next r:w ea bgt d:8 r:w next r:w ea 1 234 56789 table a-6 instruction execution cycles
702 instruction table a-6 instruction execution cycles (cont) ble d:8 r:w next r:w ea bra d:16 (bt d:16) r:w 2nd internal operation, r:w ea 1 state brn d:16 (bf d:16) r:w 2nd internal operation, r:w ea 1 state bhi d:16 r:w 2nd internal operation, r:w ea 1 state bls d:16 r:w 2nd internal operation, r:w ea 1 state bcc d:16 (bhs d:16) r:w 2nd internal operation, r:w ea 1 state bcs d:16 (blo d:16) r:w 2nd internal operation, r:w ea 1 state bne d:16 r:w 2nd internal operation, r:w ea 1 state beq d:16 r:w 2nd internal operation, r:w ea 1 state bvc d:16 r:w 2nd internal operation, r:w ea 1 state bvs d:16 r:w 2nd internal operation, r:w ea 1 state bpl d:16 r:w 2nd internal operation, r:w ea 1 state bmi d:16 r:w 2nd internal operation, r:w ea 1 state bge d:16 r:w 2nd internal operation, r:w ea 1 state blt d:16 r:w 2nd internal operation, r:w ea 1 state bgt d:16 r:w 2nd internal operation, r:w ea 1 state ble d:16 r:w 2nd internal operation, r:w ea 1 state bclr #xx:3,rd r:w next bclr #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea 1 234 56789
703 instruction table a-6 instruction execution cycles (cont) bclr #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bclr rn,rd r:w next bclr rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bclr rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bclr rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea biand #xx:3,rd r:w next biand #xx:3,@erd r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next biand #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next biand #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bild #xx:3,rd r:w next bild #xx:3,@erd r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bild #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bild #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bior #xx:3,rd r:w next bior #xx:3,@erd r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bior #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bior #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bist #xx:3,rd r:w next bist #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bist #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bixor #xx:3,rd r:w next bixor #xx:3,@erd r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bixor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bixor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bld #xx:3,rd r:w next bld #xx:3,@erd r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bld #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bld #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bnot #xx:3,rd r:w next 1 234 56789
704 instruction table a-6 instruction execution cycles (cont) bnot #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bnot rn,rd r:w next bnot rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bnot rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bnot rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bor #xx:3,rd r:w next bor #xx:3,@erd r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bset #xx:3,rd r:w next bset #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bset rn,rd r:w next bset rn,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bset rn,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bset rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea bsr d:8 r:w next r:w ea w:w :m stack (h) w:w stack (l) bsr d:16 r:w 2nd internal operation, r:w ea w:w :m stack (h) w:w stack (l) 1 state bst #xx:3,rd r:w next bst #xx:3,@erd r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:8 r:w 2nd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b:m ea r:w:m next w:b ea bst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b:m ea r:w:m next w:b ea btst #xx:3,rd r:w next btst #xx:3,@erd r:w 2nd r:b ea r:w:m next 1 234 56789
705 instruction table a-6 instruction execution cycles (cont) 1 234 56789 btst #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next btst #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next btst rn,rd r:w next btst rn,@erd r:w 2nd r:b ea r:w:m next btst rn,@aa:8 r:w 2nd r:b ea r:w:m next btst rn,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next btst rn,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next bxor #xx:3,rd r:w next bxor #xx:3,@erd r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:8 r:w 2nd r:b ea r:w:m next bxor #xx:3,@aa:16 r:w 2nd r:w 3rd r:b ea r:w:m next bxor #xx:3,@aa:32 r:w 2nd r:w 3rd r:w 4th r:b ea r:w:m next clrmac cannot be used in the h8s/2237 series and h8s/2227 series cmp.b #xx:8,rd r:w next cmp.b rs,rd r:w next cmp.w #xx:16,rd r:w 2nd r:w next cmp.w rs,rd r:w next cmp.l #xx:32,erd r:w 2nd r:w 3rd r:w next cmp.l ers,erd r:w next daa rd r:w next das rd r:w next dec.b rd r:w next dec.w #1/2,rd r:w next dec.l #1/2,erd r:w next divxs.b rs,rd r:w 2nd r:w next internal operation, 11 states divxs.w rs,erd r:w 2nd r:w next internal operation, 19 states divxu.b rs,rd r:w next internal operation, 11 states divxu.w rs,erd r:w next internal operation, 19 states eepmov.b r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next eepmov.w r:w 2nd r:b eas * 1 r:b ead * 1 r:b eas * 2 w:b ead * 2 r:w next exts.w rd r:w next ? repeated n times * 2 ? exts.l erd r:w next extu.w rd r:w next extu.l erd r:w next inc.b rd r:w next
706 instruction table a-6 instruction execution cycles (cont) inc.w #1/2,rd r:w next inc.l #1/2,erd r:w next jmp @ern r:w next r:w ea jmp @aa:24 r:w 2nd internal operation, r:w ea 1 state jmp @@aa:8 r:w next r:w:m aa:8 r:w aa:8 internal operation, r:w ea 1 state jsr @ern r:w next r:w ea w:w :m stack (h) w:w stack (l) jsr @aa:24 r:w 2nd internal operation, r:w ea w:w :m stack (h) w:w stack (l) 1 state jsr @@aa:8 r:w next r:w:m aa:8 r:w aa:8 w:w :m stack (h) w:w stack (l) r:w ea ldc #xx:8,ccr r:w next ldc #xx:8,exr r:w 2nd r:w next ldc rs,ccr r:w next ldc rs,exr r:w next ldc @ers,ccr r:w 2nd r:w next r:w ea ldc @ers,exr r:w 2nd r:w next r:w ea ldc @(d:16,ers),ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:16,ers),exr r:w 2nd r:w 3rd r:w next r:w ea ldc @(d:32,ers),ccr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @(d:32,ers),exr r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next r:w ea ldc @ers+,ccr r:w 2nd r:w next internal operation, r:w ea 1 state ldc @ers+,exr r:w 2nd r:w next internal operation, r:w ea 1 state ldc @aa:16,ccr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:16,exr r:w 2nd r:w 3rd r:w next r:w ea ldc @aa:32,ccr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldc @aa:32,exr r:w 2nd r:w 3rd r:w 4th r:w next r:w ea ldm.l @sp+, r:w 2nd r:w:m next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 (ern?rn+1) 1 state ldm.l @sp+,(ern?rn+2) r:w 2nd r:w next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state ldm.l @sp+,(ern?rn+3) r:w 2nd r:w next internal operation, r:w:m stack (h) * 3 r:w stack (l) * 3 1 state ldmac ers,mach cannot be used in the h8s/2237 series and h8s/2227 series 1 234 56789
707 instruction table a-6 instruction execution cycles (cont) ldmac ers,macl cannot be used in the h8s/2237 series and h8s/2227 series mac @ern+,@erm+ mov.b #xx:8,rd r:w next mov.b rs,rd r:w next mov.b @ers,rd r:w next r:b ea mov.b @(d:16,ers),rd r:w 2nd r:w next r:b ea mov.b @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:b ea mov.b @ers+,rd r:w next internal operation, r:b ea 1 state mov.b @aa:8,rd r:w next r:b ea mov.b @aa:16,rd r:w 2nd r:w next r:b ea mov.b @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.b rs,@erd r:w next w:b ea mov.b rs,@(d:16,erd) r:w 2nd r:w next w:b ea mov.b rs,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w next w:b ea mov.b rs,@?rd r:w next internal operation, w:b ea 1 state mov.b rs,@aa:8 r:w next w:b ea mov.b rs,@aa:16 r:w 2nd r:w next w:b ea mov.b rs,@aa:32 r:w 2nd r:w 3rd r:w next w:b ea mov.w #xx:16,rd r:w 2nd r:w next mov.w rs,rd r:w next mov.w @ers,rd r:w next r:w ea mov.w @(d:16,ers),rd r:w 2nd r:w next r:w ea mov.w @(d:32,ers),rd r:w 2nd r:w 3rd r:w 4th r:w next r:w ea mov.w @ers+, rd r:w next internal operation, r:w ea 1 state mov.w @aa:16,rd r:w 2nd r:w next r:w ea mov.w @aa:32,rd r:w 2nd r:w 3rd r:w next r:b ea mov.w rs,@erd r:w next w:w ea mov.w rs,@(d:16,erd) r:w 2nd r:w next w:w ea mov.w rs,@(d:32,erd) r:w 2nd r:w 3rd r:e 4th r:w next w:w ea mov.w rs,@?rd r:w next internal operation, w:w ea 1 state mov.w rs,@aa:16 r:w 2nd r:w next w:w ea mov.w rs,@aa:32 r:w 2nd r:w 3rd r:w next w:w ea 1 234 56789
708 instruction table a-6 instruction execution cycles (cont) 1 234 56789 mov.l #xx:32,erd r:w 2nd r:w 3rd r:w next mov.l ers,erd r:w next mov.l @ers,erd r:w 2nd r:w:m next r:w:m ea r:w ea+2 mov.l @(d:16,ers),erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @(d:32,ers),erd r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next r:w:m ea r:w ea+2 mov.l @ers+,erd r:w 2nd r:w:m next internal operation, r:w:m ea r:w ea+2 1 state mov.l @aa:16,erd r:w 2nd r:w:m 3rd r:w next r:w:m ea r:w ea+2 mov.l @aa:32,erd r:w 2nd r:w:m 3rd r:w 4th r:w next r:w:m ea r:w ea+2 mov.l ers,@erd r:w 2nd r:w:m next w:w:m ea w:w ea+2 mov.l ers,@(d:16,erd) r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@(d:32,erd) r:w 2nd r:w:m 3rd r:w:m 4th r:w 5th r:w next w:w:m ea w:w ea+2 mov.l ers,@?rd r:w 2nd r:w:m next internal operation, w:w:m ea w:w ea+2 1 state mov.l ers,@aa:16 r:w 2nd r:w:m 3rd r:w next w:w:m ea w:w ea+2 mov.l ers,@aa:32 r:w 2nd r:w:m 3rd r:w 4th r:w next w:w:m ea w:w ea+2 movfpe @aa:16,rd cannot be used in the h8s/2237 series and h8s/2227 series movtpe rs,@aa:16 mulxs.b rs,rd r:w 2nd r:w next internal operation, 11 states mulxs.w rs,erd r:w 2nd r:w next internal operation, 19 states mulxu.b rs,rd r:w next internal operation, 11 states mulxu.w rs,erd r:w next internal operation, 19 states neg.b rd r:w next neg.w rd r:w next neg.l erd r:w next nop r:w next not.b rd r:w next not.w rd r:w next not.l erd r:w next or.b #xx:8,rd r:w next or.b rs,rd r:w next or.w #xx:16,rd r:w 2nd r:w next or.w rs,rd r:w next or.l #xx:32,erd r:w 2nd r:w 3rd r:w next or.l ers,erd r:w 2nd r:w next orc #xx:8,ccr r:w next orc #xx:8,exr r:w 2nd r:w next
709 instruction table a-6 instruction execution cycles (cont) pop.w rn r:w next internal operation, r:w ea 1 state pop.l ern r:w 2nd r:w:m next internal operation, r:w:m ea r:w ea+2 1 state push.w rn r:w next internal operation, w:w ea 1 state push.l ern r:w 2nd r:w:m next internal operation, w:w:m ea w:w ea+2 1 state rotl.b rd r:w next rotl.b #2,rd r:w next rotl.w rd r:w next rotl.w #2,rd r:w next rotl.l erd r:w next rotl.l #2,erd r:w next rotr.b rd r:w next rotr.b #2,rd r:w next rotr.w rd r:w next rotr.w #2,rd r:w next rotr.l erd r:w next rotr.l #2,erd r:w next rotxl.b rd r:w next rotxl.b #2,rd r:w next rotxl.w rd r:w next rotxl.w #2,rd r:w next rotxl.l erd r:w next rotxl.l #2,erd r:w next rotxr.b rd r:w next rotxr.b #2,rd r:w next rotxr.w rd r:w next rotxr.w #2,rd r:w next rotxr.l erd r:w next rotxr.l #2,erd r:w next rte r:w next r:w stack (exr) r:w stack (h) r:w stack (l) internal operation, r:w * 4 1 state rts r:w next r:w:m stack (h) r:w stack (l) internal operation, r:w * 4 1 state shal.b rd r:w next 1 234 56789
710 instruction table a-6 instruction execution cycles (cont) shal.b #2,rd r:w next shal.w rd r:w next shal.w #2,rd r:w next shal.l erd r:w next shal.l #2,erd r:w next shar.b rd r:w next shar.b #2,rd r:w next shar.w rd r:w next shar.w #2,rd r:w next shar.l erd r:w next shar.l #2,erd r:w next shll.b rd r:w next shll.b #2,rd r:w next shll.w rd r:w next shll.w #2,rd r:w next shll.l erd r:w next shll.l #2,erd r:w next shlr.b rd r:w next shlr.b #2,rd r:w next shlr.w rd r:w next shlr.w #2,rd r:w next shlr.l erd r:w next shlr.l #2,erd r:w next sleep r:w next internal operation:m stc ccr,rd r:w next stc exr,rd r:w next stc ccr,@erd r:w 2nd r:w next w:w ea stc exr,@erd r:w 2nd r:w next w:w ea stc ccr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc exr,@(d:16,erd) r:w 2nd r:w 3rd r:w next w:w ea stc ccr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc exr,@(d:32,erd) r:w 2nd r:w 3rd r:w 4th r:w 5th r:w next w:w ea stc ccr,@?rd r:w 2nd r:w next internal operation, w:w ea 1 state 1 234 56789
711 instruction table a-6 instruction execution cycles (cont) stc exr,@?rd r:w 2nd r:w next internal operation, w:w ea 1 state stc ccr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc exr,@aa:16 r:w 2nd r:w 3rd r:w next w:w ea stc ccr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stc exr,@aa:32 r:w 2nd r:w 3rd r:w 4th r:w next w:w ea stm.l(ern?rn+1),@?p r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stm.l(ern?rn+2),@?p r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stm.l(ern?rn+3),@?p r:w 2nd r:w:m next internal operation, w:w:m stack (h) * 3 w:w stack (l) * 3 1 state stmac mach,erd cannot be used in the h8s/2237 series and h8s/2227 series stmac macl,erd sub.b rs,rd r:w next sub.w #xx:16,rd r:w 2nd r:w next sub.w rs,rd r:w next sub.l #xx:32,erd r:w 2nd r:w 3rd r:w next sub.l ers,erd r:w next subs #1/2/4,erd r:w next subx #xx:8,rd r:w next subx rs,rd r:w next tas @erd r:w 2nd r:w next r:b:m ea w:b ea trapa #x:2 r:w next internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, r:w * 7 1 state 1 state xor.b #xx8,rd r:w next xor.b rs,rd r:w next xor.w #xx:16,rd r:w 2nd r:w next xor.w rs,rd r:w next xor.l #xx:32,erd r:w 2nd r:w 3rd r:w next xor.l ers,erd r:w 2nd r:w next xorc #xx:8,ccr r:w next xorc #xx:8,exr r:w 2nd r:w next reset exception r:w:m vec r:w vec+2 internal operation, r:w * 5 handling 1 state 1 234 56789
712 instruction table a-6 instruction execution cycles (cont) interrupt exception r:w * 6 internal operation, w:w stack (l) w:w stack (h) w:w stack (exr) r:w:m vec r:w vec+2 internal operation, r:w * 7 handling 1 state 1 state notes: 1. eas is the contents of er5. ead is the contents of er6. 2. eas is the contents of er5. ead is the contents of er6. both registers are incremented by 1 after execution of the instructio n. n is the initial value of r4l or r4. if n = 0, these bus cycles are not executed. 3. repeated two times to save or restore two registers, three times for three registers, or four times for four registers. 4. start address after return. 5. start address of the program. 6. prefetch address, equal to two plus the pc value pushed onto the stack. in recovery from sleep mode or software standby mode the read operation is replaced by an internal operation. 7. start address of the interrupt-handling routine. 1 234 56789
713 a.6 condition code modification this section indicates the effect of each cpu instruction on the condition code. the notation used in the table is defined below. m = 31 for longword operands 15 for word operands 7 for byte operands si di ri dn 0 1 * z' c' the i-th bit of the source operand the i-th bit of the destination operand the i-th bit of the result the specified bit in the destination operand not affected modified according to the result of the instruction (see definition) always cleared to 0 always set to 1 undetermined (no guaranteed value) z flag before instruction execution c flag before instruction execution
714 table a-7 condition code modification instruction h n z v c definition add h = sm? ?dm? + dm? ? rme4 + sm? ? rme4 n = rm z = rm ? rme1 ? ...... ? r0 v = sm ?dm ? rm + sm ? dm ?rm c = sm ?dm + dm ? rm + sm ? rm adds addx h = sm? ?dm? + dm? ? rme4 + sm? ? rme4 n = rm z = z' ? rm ? ...... ? r0 v = sm ?dm ? rm + sm ? dm ?rm c = sm ?dm + dm ? rm + sm ? rm and 0 n = rm z = rm ? rme1 ? ...... ? r0 andc stores the corresponding bits of the result. no flags change when the operand is exr. band c = c' ?dn bcc bclr biand c = c' ? dn bild c = dn bior c = c' + dn bist bixor c = c' ?dn + c' ? dn bld c = dn bnot bor c = c' + dn bset bsr bst btst z = dn bxor c = c' ? dn + c' ?dn clrmac cannot be used in the h8s/2237 series and h8s/2227 series
715 table a-7 condition code modification (cont) instruction h n z v c definition cmp h = sm? ? dme4 + dme4 ?rm? + sm? ?rm? n = rm z = rm ? rme1 ? ...... ? r0 v = sm ?dm ? rm + sm ? dm ?rm c = sm ? dm + dm ?rm + sm ?rm daa * * n = rm z = rm ? rme1 ? ...... ? r0 c: decimal arithmetic carry das * * n = rm z = rm ? rme1 ? ...... ? r0 c: decimal arithmetic borrow dec n = rm z = rm ? rme1 ? ...... ? r0 v = dm ? rm divxs n = sm ? dm + sm ?dm z = sm ? sme1 ? ...... ? s0 divxu n = sm z = sm ? sme1 ? ...... ? s0 eepmov exts 0 n = rm z = rm ? rme1 ? ...... ? r0 extu 0 0 z = rm ? rme1 ? ...... ? r0 inc n = rm z = rm ? rme1 ? ...... ? r0 v = dm ?rm jmp jsr ldc stores the corresponding bits of the result. no flags change when the operand is exr. ldm ldmac cannnot be used in the h8s/2237 series and h8s/2227 mac series
716 table a-7 condition code modification (cont) instruction h n z v c definition mov 0 n = rm z = rm ? rme1 ? ...... ? r0 movfpe can not be used in the h8s/2237 series and h8s/2227 movtpe series mulxs n = r2m z = r2m ? r2me1 ? ...... ? r0 mulxu neg h = dm? + rm? n = rm z = rm ? rme1 ? ...... ? r0 v = dm ?rm c = dm + rm nop not 0 n = rm z = rm ? rme1 ? ...... ? r0 or 0 n = rm z = rm ? rme1 ? ...... ? r0 orc stores the corresponding bits of the result. no flags change when the operand is exr. pop 0 n = rm z = rm ? rme1 ? ...... ? r0 push 0 n = rm z = rm ? rme1 ? ...... ? r0 rotl 0 n = rm z = rm ? rme1 ? ...... ? r0 c = dm (1-bit shift) or c = dm? (2-bit shift) rotr 0 n = rm z = rm ? rme1 ? ...... ? r0 c = d0 (1-bit shift) or c = d1 (2-bit shift)
717 table a-7 condition code modification (cont) instruction h n z v c definition rotxl 0 n = rm z = rm ? rme1 ? ...... ? r0 c = dm (1-bit shift) or c = dm? (2-bit shift) rotxr 0 n = rm z = rm ? rme1 ? ...... ? r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) rte stores the corresponding bits of the result. rts shal n = rm z = rm ? rme1 ? ...... ? r0 v = dm ?dm? + dm ? dme1 (1-bit shift) v = dm ?dm? ?dm? ? dm ? dme1 ? dme2 (2-bit shift) c = dm (1-bit shift) or c = dm? (2-bit shift) shar 0 n = rm z = rm ? rme1 ? ...... ? r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) shll 0 n = rm z = rm ? rme1 ? ...... ? r0 c = dm (1-bit shift) or c = dm? (2-bit shift) shlr 0 0 n = rm z = rm ? rme1 ? ...... ? r0 c = d0 (1-bit shift) or c = d1 (2-bit shift) sleep stc stm stmac cannot be used in the h8s/2237 series and h8s/2227 series
718 table a-7 condition code modification (cont) instruction h n z v c definition sub h = sm? ? dme4 + dme4 ?rm? + sm? ?rm? n = rm z = rm ? rme1 ? ...... ? r0 v = sm ?dm ? rm + sm ? dm ?rm c = sm ? dm + dm ?rm + sm ?rm subs subx h = sm? ? dme4 + dme4 ?rm? + sm? ?rm? n = rm z = z' ? rm ? ...... ? r0 v = sm ?dm ? rm + sm ? dm ?rm c = sm ? dm + dm ?rm + sm ?rm tas 0 n = dm z = dm ? dme1 ? ...... ? d0 trapa xor 0 n = rm z = rm ? rme1 ? ...... ? r0 xorc stores the corresponding bits of the result. no flags change when the operand is exr.
719 appendix b internal i/o register b.1 addresses address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ebc0 to h'efbf mra sar sm1 sm0 dm1 dm0 md1 md0 dts sz dtc 16/32 * 1 bit mrb chne disel dar cra crb h'fdac dadr0 d/a converter 8 bit h'fdcd dadr1 h'fdae dacr daoe1 daoe0 dae h'fdd0 h'fdd1 h'fdd2 smr3 brr3 scr3 c/ a /gm * 2 tie chr rie pe te o/ e re stop mpie mp teie cks1 cke1 cks0 cke0 sci3, smart card interface 3 8 bit h'fdd3 tdr3 h'fdd4 ssr3 tdre rdrf orer fer/ ers * 3 per tend mpb mpbt h'fdd5 rdr3 h'fdd6 scmr3 sdir sinv smif h'fde4 sbycr ssby sts2 sts1 sts0 ope power-down state 8 bit h'fde5 syscr intm1 intm0 nmieg mrese rame mcu 8 bit h'fde6 sckcr pstop sck2 sck1 sck0 clock pulse generator 8 bit h'fde7 mdcr mds2 mds1 msd0 mcu 8 bit h'fde8 h'fde9 mstpcra mstpcrb mstpa7 mstpb7 mstpa6 mstpb6 mstpa5 mstpb5 mstpa4 mstpb4 mstpa3 mstpb3 mstpa2 mstpb2 mstpa1 mstpb1 mstpa0 mstpb0 power-down state 8 bit h'fdea mstpcrc mstpc7 mstpc6 mstpc5 mstpc4 mstpc3 mstpc2 mstpc1 mstpc0 notes 1. located in on-chip ram. the bus width is 32 bits when the dtc accesses this area as register information, and 16 bits otherwise. 2. functions as c/ a for sci use, and as gm for smart card interface use. 3. functions as fer for sci use, and as ers for smart card interface use.
720 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fdeb pfcr buzze ae3 ae2 ae1 ae0 bus controller 8 bit h'fdec lpwrcr dton lson nesel substp rfcut stc1 stc0 power-down state 8 bit h'fe00 bara pbc 16 bit h'fe01 baa23 baa22 baa21 baa20 baa19 baa18 baa17 baa16 h'fe02 baa15 baa14 baa13 baa12 baa11 baa10 baa9 baa8 h'fe03 baa7 baa6 baa5 baa4 baa3 baa2 baa1 baa0 h'fe04 barb h'fe05 bab23 bab22 bab21 bab20 bab19 bab18 bab17 bab16 h'fe06 bab15 bab14 bab13 bab12 bab11 bab10 bab9 bab8 h'fe07 bab7 bab6 bab5 bab4 bab3 bab2 bab1 bab0 h'fe08 bcra cmfa cda bamra2 bamra1 bamra0 csela1 csela0 biea 8 bit h'fe09 bcrb cmfb cdb bamrb2 bamrb1 bamrb0 cselb1 cselb0 bieb h'fe12 h'fe13 iscrh iscrl irq7scb irq3scb irq7sca irq3sca irq6scb irq2scb irq6sca irq2sca irq5scb irq1scb irq5sca irq1sca irq4scb irq0scb irq4sca irq0sca interrupt controller 8 bit h'fe14 ier irq7e irq6e irq5e irq4e irq3e irq2e irq1e irq0e h'fe15 isr irq7f irq6f irq5f irq4f irq3f irq2f irq1f irq0f h'fe16 to h'fe1e dtcer dtce7 dtce6 dtce5 dtce4 dtce3 dtce2 dtce1 dtce0 dtc 8 bit h'fe1f dtvecr swdte dtvec6 dtvec5 dtvec4 dtvec3 dtvec2 dtvec1 dtvec0 h'fe30 p1ddr p17ddr p16ddr p15ddr p14ddr p13ddr p12ddr p11ddr p10ddr port 8 bit h'fe32 p3ddr p36ddr p35ddr p34ddr p33ddr p32ddr p31ddr p30ddr h'fe36 p7ddr p77ddr p76ddr p75ddr p74ddr p73ddr p72ddr p71ddr p70ddr h'fe39 paddr pa3ddr pa2ddr pa1ddr pa0ddr h'fe3a pbddr pb7ddr pb6ddr pb5ddr pb4ddr pb3ddr pb2ddr pb1ddr pb0ddr h'fe3b pcddr pc7ddr pc6ddr pc5ddr pc4ddr pc3ddr pc2ddr pc1ddr pc0ddr h'fe3c pdddr pd7ddr pd6ddr pd5ddr pd4ddr pd3ddr pd2ddr pd1ddr pd0ddr h'fe3d peddr pe7ddr pe6ddr pe5ddr pe4ddr pe3ddr pe2ddr pe1ddr pe0ddr h'fe3e pfddr pf7ddr pf6ddr pf5ddr pf4ddr pf3ddr pf2ddr pf1ddr pf0ddr h'fe3f pgddr pg4ddr pg3ddr pg2ddr pg1ddr pg0ddr h'fe40 papcr pa3pcr pa2pcr pa1pcr pa0pcr h'fe41 pbpcr pb7pcr pb6pcr pb5pcr pb4pcr pb3pcr pb2pcr pb1pcr pb0pcr h'fe42 pcpcr pc7pcr pc6pcr pc5pcr pc4pcr pc3pcr pc2pcr pc1pcr pc0pcr h'fe43 pdpcr pd7pcr pd6pcr pd5pcr pd4pcr pd3pcr pd2pcr pd1pcr pd0pcr h'fe44 pepcr pe7pcr pe6pcr pe5pcr pe4pcr pe3pcr pe2pcr pe1pcr pe0pcr h'fe46 p3odr p36odr p35odr p34odr p33odr p32odr p31odr p30odr h'fe47 paodr pa3odr pa2odr pa1odr pa0odr
721 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'fe80 tcr3 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu3 8 bit h'fe81 tmdr3 bfb bfa md3 md2 md1 md0 h'fe82 tior3h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fe83 tior3l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'fe84 tier3 ttge tciev tgied tgiec tgieb tgiea h'fe85 tsr3 tcfv tgfd tgfc tgfb tgfa h'fe86 tcnt3 16 bit h'fe87 h'fe88 tgr3a h'fe89 h'fe8a tgr3b h'fe8b h'fe8c tgr3c h'fe8d h'fe8e tgr3d h'fe8f h'fe90 tcr4 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu4 8 bit h'fe91 tmdr4 md3md2md1md0 h'fe92 tior4 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fe94 tier4 ttge tcieu tciev tgieb tgiea h'fe95 tsr4 tcfd tcfu tcfv tgfb tgfa h'fe96 tcnt4 16 bit h'fe97 h'fe98 tgr4a h'fe99 h'fe9a tgr4b h'fe9b h'fea0 tcr5 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu5 8 bit h'fea1 tmdr5 md3md2md1md0 h'fea2 tior5 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'fea4 tier5 ttge tcieu tciev tgieb tgiea h'fea5 tsr5 tcfd tcfu tcfv tgfb tgfa h'fea6 tcnt5 16 bit h'fea7 h'fea8 tgr5a h'fea9
722 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'feaa tgr5b tpu5 16 bit h'feab h'feb0 tstr cst5 cst4 cst3 cst2 cst1 cst0 tpu 8 bit h'feb1 tsyr sync5 sync4 sync3 sync2 sync1 sync0 h'fec0 h'fec1 ipra iprb ipr6 ipr6 ipr5 ipr5 ipr4 ipr4 ipr2 ipr2 ipr1 ipr1 ipr0 ipr0 interrupt controller 8 bit h'fec2 iprc ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fec3 iprd ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fec4 ipre ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fec5 iprf ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fec6 iprg ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fec7 iprh ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fec8 ipri ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fec9 iprj ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'feca iprk ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fece ipro ipr6 ipr5 ipr4 ipr2 ipr1 ipr0 h'fed0 abwcr abw7 abw6 abw5 abw4 abw3 abw2 abw1 abw0 bus controller 8 bit h'fed1 astcr ast7 ast6 ast5 ast4 ast3 ast2 ast1 ast0 h'fed2 wcrh w71 w70 w61 w60 w51 w50 w41 w40 h'fed3 wcrl w31 w30 w21 w20 w11 w10 w01 w00 h'fed4 bcrh icis1 icis0 brstrm brsts1 brsts0 h'fed5 bcrl brle waite h'ff00 p1dr p17dr p16dr p15dr p14dr p13dr p12dr p11dr p10dr port 8 bit h'ff02 p3dr p36dr p35dr p34dr p33dr p32dr p31dr p30dr h'ff06 p7dr p77dr p76dr p75dr p74dr p73dr p72dr p71dr p70dr h'ff09 padr pa3dr pa2dr pa1dr pa0dr h'ff0a pbdr pb7dr pb6dr pb5dr pb4dr pb3dr pb2dr pb1dr pb0dr h'ff0b pcdr pc7dr pc6dr pc5dr pc4dr pc3dr pc2dr pc1dr pc0dr h'ff0c pddr pd7dr pd6dr pd5dr pd4dr pd3dr pd2dr pd1dr pd0dr h'ff0d pedr pe7dr pe6dr pe5dr pe4dr pe3dr pe2dr pe1dr pe0dr h'ff0e pfdr pf7dr pf6dr pf5dr pf4dr pf3dr pf2dr pf1dr pf0dr h'ff0f pgdr pg4dr pg3dr pg2dr pg1dr pg0dr
723 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ff10 tcr0 cclr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu0 8 bit h'ff11 tmdr0 bfb bfa md3 md2 md1 md0 h'ff12 tior0h iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ff13 tior0l iod3 iod2 iod1 iod0 ioc3 ioc2 ioc1 ioc0 h'ff14 tier0 ttge tciev tgied tgiec tgieb tgiea h'ff15 tsr0 tcfv tgfd tgfc tgfb tgfa h'ff16 tcnt0 16 bit h'ff17 h'ff18 tgr0a h'ff19 h'ff1a tgr0b h'ff1b h'ff1c tgr0c h'ff1d h'ff1e tgr0d h'ff1f h'ff20 tcr1 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu1 8 bit h'ff21 tmdr1 md3md2md1md0 h'ff22 tior1 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ff24 tier1 ttge tcieu tciev tgieb tgiea h'ff25 tsr1 tcfd tcfu tcfv tgfb tgfa h'ff26 tcnt1 16 bit h'ff27 h'ff28 tgr1a h'ff29 h'ff2a tgr1b h'ff2b h'ff30 tcr2 cclr1 cclr0 ckeg1 ckeg0 tpsc2 tpsc1 tpsc0 tpu2 8 bit h'ff31 tmdr2 md3md2md1md0 h'ff32 tior2 iob3 iob2 iob1 iob0 ioa3 ioa2 ioa1 ioa0 h'ff34 tier2 ttge tcieu tciev tgieb tgiea h'ff35 tsr2 tcfd tcfu tcfv tgfb tgfa h'ff36 tcnt2 16 bit h'ff37 h'ff38 tgr2a h'ff39 h'ff3a tgr2b h'ff3b
724 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ff68 h'ff69 tcr0 tcr1 cmieb cmieb cmiea cmiea ovie ovie cclr1 cclr1 cclr0 cclr0 cks2 cks2 cks1 cks1 cks0 cks0 8 bit timer channel 0, 1 8 bit h'ff6a tcsr0 cmfb cmfa ovf adte os3 os2 os1 os0 h'ff6b tcsr1 cmfb cmfa ovf os3 os2 os1 os0 h'ff6c tcora0 8/16 bit h'ff6d tcora1 h'ff6e tcorb0 h'ff6f tcorb1 h'ff70 tcnt0 h'ff71 tcnt1 h'ff74 h'ff75 tcsr0 tcnt0 ovf wt/ it tme cks2 cks1 cks0 watchdog timer 0 16 bit h'ff77 (read) rstcsr wovf rste rsts h'ff78 h'ff79 h'ff7a smr0 brr0 scr0 c/ a /gm * 1 tie chr rie pe te o/ e re stop mpie mp teie cks1 cke1 cks0 cke0 sci0, smart card interface 0 8 bit h'ff7b tdr0 h'ff7c ssr0 tdre rdrf orer fer/ ers * 2 per tend mpb mpbt h'ff7d rdr0 h'ff7e scmr0 sdir sinv smif h'ff80 h'ff81 h'ff82 smr1 brr1 scr1 c/ a /gm * 1 tie chr rie pe te o/ e re stop mpie mp teie cks1 cke1 cks0 cke0 sci1, smart card interface 1 8 bit h'ff83 tdr1 h'ff84 ssr1 tdre rdrf orer fer/ ers * 2 per tend mpb mpbt h'ff85 rdr1 h'ff86 scmr1 sdir sinv smif notes: 1. functions as c/ a for sci use, and as gm for smart card interface use. 2. functions as fer for sci use, and as ers for smart card interface use.
725 address register name bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 module name data bus width h'ff88 h'ff89 h'ff8a smr2 brr2 scr2 c/ a /gm * 1 tie chr rie pe te o/ e re stop mpie mp teie cks1 cke1 cks0 cke0 sci2, smart card interface 2 8 bit h'ff8b tdr2 h'ff8c ssr2 tdre rdrf orer fer/ ers * 2 per tend mpb mpbt h'ff8d rdr2 h'ff8e scmr2 sdir sinv smif h'ff90 addrah ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 a/d converter 8 bit h'ff91 addral ad1 ad0 h'ff92 addrbh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff93 addrbl ad1 ad0 h'ff94 addrch ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff95 addrcl ad1 ad0 h'ff96 addrdh ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 h'ff97 addrdl ad1 ad0 h'ff98 adcsr adf adie adst scan ch2 ch1 ch0 h'ff99 adcr trgs1 trgs0 cks1 cks0 h'ffa2 h'ffa3 (read) tcsr1 tcnt1 ovf wt/ it tme pss rst/ nmi cks2 cks1 cks0 watchdog timer 1 16 bit h'ffb0 port1 p17 p16 p15 p14 p13 p12 p11 p10 port 8 bit h'ffb2 port3 p36 p35 p34 p33 p32 p31 p30 h'ffb3 port4 p47 p46 p45 p44 p43 p42 p41 p40 h'ffb6 port7 p77 p76 p75 p74 p73 p72 p71 p70 h'ffb8 port9 p97 p96 h'ffb9 porta pa3pa2pa1pa0 h'ffba portb pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 h'ffbb portc pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 h'ffbc portd pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 h'ffbd porte pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 h'ffbe portf pf7 pf6 pf5 pf4 pf3 pf2 pf1 pf0 h'ffbf portg pg4 pg3 pg2 pg1 pg0 notes: 1. functions as c/ a for sci use, and as gm for smart card interface use. 2. functions as fer for sci use, and as ers for smart card interface use.
726 b.2 functions mra?tc mode register a h'ebc0 to h'efbf dtc 7 sm1 6 sm0 5 dm1 4 dm0 3 md1 0 sz 2 md0 1 dts bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined dtc data transfer size 0 1 byte-size transfer word-size transfer 0 1 0 1 sar is fixed sar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) sar is decremented after a transfer (by ? when sz = 0; by ? when sz = 1) dtc transfer mode select dtc mode destination address mode source address mode 0 1 destination side is repeat area or block area source side is repeat area or block area 0 1 0 1 dar is fixed dar is incremented after a transfer (by +1 when sz = 0; by +2 when sz = 1) dar is decremented after a transfer (by ? when sz = 0; by ? when sz = 1) 0 1 0 1 0 1 normal mode repeat mode block transfer mode
727 mrb?tc mode register b h'ebc0 to h'efbf dtc 7 chne 6 disel 5 4 3 0 2 1 bit initial value : : r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined dtc interrupt select reserved only 0 should be written to these bits 0 1 after a data transfer ends, the cpu interrupt is disabled unless the transfer counter is 0 after a data transfer ends, the cpu interrupt is enabled dtc chain transfer enable 0 1 end of dtc data transfer dtc chain transfer sar?tc source address register h'ebc0 to h'efbf dtc 23 22 21 20 19 43210 bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined s p ecifies transfer data source address dar?tc destination address register h'ebc0 to h'efbf dtc 23 22 21 20 19 43210 bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined specifies transfer data destination address
728 cra?tc transfer count register a h'ebc0 to h'efbf dtc 15 14 13 12 11109876543210 crah cral bit initial value : : unde- fined r/w : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined specifies the number of dtc data transfers crb?tc transfer count register b h'ebc0 to h'efbf dtc 15 14 13 12 11109876543210 bit initial value : : unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined unde- fined r/w : specifies the number of dtc block data transfers dadr0?/a data register 0 dadr1?/a data register 1 h'fdac h'fdad d/a 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : stores data for d/a conversion
729 dacr?/a control register h'fdae d/a 7 daoe1 0 r/w 6 daoe0 0 r/w 5 dae 0 r/w 4 1 3 1 0 1 2 1 1 1 bit initial value r/w : : : d/a output enable 0 d/a conversion control 0 1 analog output da0 is disabled channel 0 d/a conversion is enabled; analog output da0 is enabled d/a output enable 1 0 1 analog output da1 is disabled channel 1 d/a conversion is enabled; analog output da1 is enabled daoe1 0 1 daoe0 0 1 0 1 dae * 0 1 0 1 * *: don? care description channel 0 and 1 d/a conversions disabled channel 0 d/a conversion enabled channel 1 d/a conversion disabled channel 0 and 1 d/a conversions enabled channel 0 d/a conversion disabled channel 1 d/a conversion enabled channel 0 and 1 d/a conversions enabled channel 0 and 1 d/a conversions enabled
730 smr3?erial mode register 3 h'fdd0 sci3 7 c/a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value r/w : : : multiprocessor mode clock select 0 1 multiprocessor function disabled multiprocessor format selected parity mode 0 1 even parity odd parity parity enable 0 1 parity bit addition and checking disabled parity bit addition and checking enabled character length 0 1 note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. 8-bit data 7-bit data * selects asynchronous mode or clocked synchronous mode 0 1 asynchronous mode clocked synchronous mode stop bit length 0 1 1 stop bit 2 stop bits 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock
731 smr3?erial mode register 3 h'fdd0 smart card interface 3 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 bcp1 0 r/w 0 cks0 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w bit initial value r/w : : : clock select parity mode 0 1 even parity odd parity parity enable 0 1 setting prohibited parity bit addition and checking enabled block transfer mode 0 1 normal smart card interface mode operation block transfer mode operation gsm mode 0 1 note: etu: elementary time unit (time for transfer of 1 bit) normal smart card interface mode operation tend flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit clock output on/off control only gsm mode smart card interface mode operation tend flag generation 11.0 etu after beginning of start bit high/low fixing control possible in addition to clock output on/off control (set by scr) 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock base clock pulse 0 1 0 1 0 1 32 clocks 64 clocks 372 clocks 256 clocks
732 brr3?it rate register 3 h'fdd1 sci3, smart card interface 3 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w note: for details, see section 13.2.8, bit rate re g ister ( brr ) . : : : sets the serial transfer bit rate
733 scr3?erial control register 3 h'fdd2 sci3 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : transmit end interrupt enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit enable 0 1 transmission disabled transmission enabled receive enable 0 1 reception disabled reception enabled receive interrupt enable transmit interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled 0 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled multiprocessor interrupt enable 0 1 multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when mpb= 1 data is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and settingof the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. clock enable 0 1 0 1 0 1 asynchronous mode internal clock/sck pin functions as i/o port clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode internal clock/sck pin functions as clock output * 1 clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input notes: 1. 2. outputs a clock of the same frequency as the bit rate. inputs a clock with a frequency 16 times the bit rate.
734 scr3?erial control register 3 h'fdd2 smart card interface 3 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : transmit end interrupt enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit enable 0 1 transmission disabled transmission enabled receive enable 0 1 reception disabled reception enabled receive interrupt enable transmit interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled 0 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled multiprocessor interrupt enable 0 1 multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when mpb= 1 data is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and settingof the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. clock enable operates as port i/o pin outputs clock as sck output pin operates as sck output pin, with output fixed low outputs clock as sck output pin operates as sck output pin, with output fixed high outputs clock as sck output pin smcr smif smr c/a, gm scr setting sck pin function see the sci cke1 cke0 0 1000 1001 1100 1101 1110 1111
735 tdr3?ransmit data register 3 h'fdd3 sci3, smart card interface 3 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : stores data for serial transmission
736 ssr3?erial status register 3 h'fdd4 sci3 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : multiprocessor bit 0 1 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted overrun error receive data register full 0 1 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 transmit end 0 1 [clearing conditions] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?when the te bit in scr is 0 ?when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character parity error 0 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/e bit in smr framing error 0 1 [clearing condition] ?when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 0 1 [clearing conditions] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 1 note: only 0 can be written, to clear the flag. [clearing conditions] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr
737 ssr3?erial status register 3 h'fdd4 smart card interface 3 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : multiprocessor bit 0 1 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted overrun error receive data register full 0 1 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 transmit end 0 1 note: etu: elementary time unit (time for transfer of 1 bit) [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and write data to tdr [setting conditions] upon reset, and in standby mode or module stop mode when the te bit in scr is 0 and the ers bit is also 0 when tdre = 1 and ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 0 when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 when tdre = 1, 1.5 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 when tdre = 1, 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1 parity error 0 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/e bit in smr error signal status 0 1 note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its previous state. [clearing condition] ?upon reset, and in standby mode or module stop mode ?when 0 is written to ers after reading ers = 1 [setting condition] when the low level of the error signal is sampled 0 1 [clearing conditions] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 1 note: onl y 0 can be written, to clear the fla g . [clearing conditions] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr
738 rdr3?eceive data register 3 h'fdd5 sci3, smart card interface 3 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : stores received serial data scmr3?mart card mode register 3 h'fdd6 sci3, smart card interface 3 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 bit initial value r/w : : : specifies inversion of the data logic level tdr contents are transmitted as they are receive data is stored as it is in rdr tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr 0 1 smart card interface mode select selects the serial/parallel conversion format tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first tdr contents are transmitted msb-first receive data is stored in rdr msb-first 0 1 0 1 smart card interface function is disabled smart card interface function is enabled
739 sbycr?tandby control register h'fde4 power-down state 7 ssby 0 r/w 6 sts2 0 r/w 5 sts1 0 r/w 4 sts0 0 r/w 3 ope 1 r/w 0 0 2 0 1 0 bit initial value read/write standby timer select standby time = 8192 states standby time = 16384 states standby time = 32768 states standby time = 65536 states standby time = 131072 states standby time = 262144 states reserved standby time = 16 states 0 1 0 1 0 1 0 1 0 1 0 1 0 1 output port enable software standby transition to sleep mode after execution of sleep instruction in high-speed mode or medium-speed mode transition to subsleep mode after execution of sleep instruction in subactive mode transition to software standby mode, subactive mode, or watch mode after execution of sleep instruction in high-speed mode or medium-speed mode transition to watch mode or high-speed mode after execution of sleep instruction in subactive mode 0 1 0 1 in software standby mode and watch mode, and in a direct transition, address bus and bus control signals are high-impedance in software standby mode and watch mode, and in a direct transition, address bus and bus control signals retain their output state
740 syscr?ystem control register h'fde5 mcu 7 0 r/w 6 0 5 intm1 0 r/w 4 intm0 0 r/w 3 nmieg 0 r/w 0 rame 1 r/w 2 mrese 0 r/w 1 0 bit initial value r/w : : : ram enable 0 1 on-chip ram is disabled on-chip ram is enabled manual reset select 0 1 manual reset is disabled manual reset is enabled nmi interrupt input edge select 0 1 falling edge rising edge interrupt control mode select 0 1 0 1 0 1 interrupt control mode 0 setting prohibited interrupt control mode 2 setting prohibited reserved onl y 0 should be written to this bit
741 sckcr?ystem clock control register h'fde6 clock pulse generator 7 pstop 0 r/w 6 0 r/w 5 0 4 0 3 0 0 sck0 0 r/w 2 sck2 0 r/w 1 sck1 0 r/w bit initial value r/w : : : ?clock output control pstop 0 1 ?output fixed high ?output fixed high fixed high fixed high high impedance high impedance bus master clock select 0 1 0 1 0 1 0 1 0 1 0 1 bus master is in high-speed mode medium-speed clock is ?2 medium-speed clock is ?4 medium-speed clock is ?8 medium-speed clock is ?16 medium-speed clock is ?32 high-speed mode, medium- speed mode, subactive mode sleep mode, subsleep mode software standby mode, watch mode, direct transition hardware standby mode mdcr?ode control register h'fde7 mcu 7 1 6 0 5 0 4 0 3 0 0 mds0 * r 2 mds2 * r 1 mds1 * r note: * determined by pins md 2 to md 0 . bit initial value r/w : : : current mode pin operating mode
742 mstpcra?odule stop control register a mstpcrb?odule stop control register b mstpcrc?odule stop control register c h'fde8 h'fde9 h'fdea power-down state 7 mstpa7 0 r/w 6 mstpa6 0 r/w 5 mstpa5 1 r/w 4 mstpa4 1 r/w 3 mstpa3 1 r/w 0 mstpa0 1 r/w 2 mstpa2 1 r/w 1 mstpa1 1 r/w bit initial value read/write mstpcra 7 mstpb7 1 r/w 6 mstpb6 1 r/w 5 mstpb5 1 r/w 4 mstpb4 1 r/w 3 mstpb3 1 r/w 0 mstpb0 1 r/w 2 mstpb2 1 r/w 1 mstpb1 1 r/w bit initial value read/write mstpcrb 7 mstpc7 1 r/w 6 mstpc6 1 r/w 5 mstpc5 1 r/w 4 mstpc4 1 r/w 3 mstpc3 1 r/w 0 mstpc0 1 r/w 2 mstpc2 1 r/w 1 mstpc1 1 r/w bit initial value read/write mstpcrc specifies module stop mode 0 1 module stop mode is cleared module stop mode is set
743 pfcr?in function control register h'fdeb bus controller 7 0 0 r/w 6 0 0 r/w 5 buzze 0 0 r/w 4 0 0 r/w 3 ae3 1 0 r/w 0 ae0 1 0 r/w 2 ae2 1 0 r/w 1 ae1 0 0 r/w bit modes 4 and 5 initial value modes 6 and 7 initial value read/write address output enable a8 to a23 address output disabled a8 address output enabled; a9 to a23 address output disabled a8, a9 address output enabled; a10 to a23 address output disabled a8 to a10 address output enabled; a11 to a23 address output disabled a8 to a11 address output enabled; a12 to a23 address output disabled a8 to a12 address output enabled; a13 to a23 address output disabled a8 to a13 address output enabled; a14 to a23 address output disabled a8 to a14 address output enabled; a15 to a23 address output disabled a8 to a15 address output enabled; a16 to a23 address output disabled a8 to a16 address output enabled; a17 to a23 address output disabled a8 to a17 address output enabled; a18 to a23 address output disabled a8 to a18 address output enabled; a19 to a23 address output disabled a8 to a19 address output enabled; a20 to a23 address output disabled a8 to a20 address output enabled; a21 to a23 address output disabled a8 to a21 address output enabled; a22, a23 address output disabled a8 to a23 address output enabled 0 1 note: in expanded mode with on-chip rom enabled, address pins a0 to a7 are made address outputs by setting the corresponding ddr bits to 1; in expanded mode with on-chip rom disabled, address pins a0 to a7 are always address outputs. 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 buzz output enable 0 1 functions as pf1 i/o pin functions as buzz output pin
744 lpwrcr?ow-power control register h'fdec power-down state 7 dton 0 r/w 6 lson 0 r/w 5 nesel 0 r/w 4 substp 0 r/w 3 rfcut 0 r/w 0 stc0 0 r/w 2 0 r/w 1 stc1 0 r/w bit initial value read/write subclock oscillator control 0 1 subclock oscillator operates subclock oscillator is stopped noise elimination sampling frequency select 0 1 sampling at ?divided by 32 sampling at ?divided by 4 built-in feedback resistor control 0 1 system clock oscillator's built-in feedback resistor and duty adjustment circuit are used system clock oscillator's built-in feedback resistor and duty adjustment circuit are not used frequency multiplication factor 0 1 0 1 0 1 x1 (initial value) x2 (setting prohibited) x4 (setting prohibited) pll is bypassed low-speed on flag 0 1 when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode * when a sleep instruction is executed in subactive mode, a transition is made to watch mode, or directly to high-speed mode after watch mode is cleared, a transition is made to high-speed mode when a sleep instruction is executed in high-speed mode a transition is made to watch mode or subactive mode * when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode after watch mode is cleared, a transition is made to subactive mode direct-transfer on flag 0 1 when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made to sleep mode, software standby mode, or watch mode* when a sleep instruction is executed in subactive mode, a transition is made to subsleep mode or watch mode when a sleep instruction is executed in high-speed mode or medium-speed mode, a transition is made directly to subactive mode*, or a transition is made to sleep mode or software standby mode when a sleep instruction is executed in subactive mode, a transition is made directly to high-speed mode, or a transition is made to subsleep mode note: when a transition is made to watch mode or subactive mode, high-speed mode must be set. *
745 bara?reak address register a barb?reak address register b h'fe00 h'fe04 pbc bit initial value read/write 31 unde- fined 24 unde- fined r/w baa 23 23 0 r/w baa 22 22 0 r/w baa 21 21 0 r/w baa 20 20 0 r/w baa 19 19 0 r/w baa 18 18 0 r/w baa 17 17 0 r/w baa 16 16 0 r/w 0 baa 7 7 r/w 0 baa 6 6 r/w 0 baa 5 5 r/w 0 baa 4 4 r/w 0 baa 3 3 r/w 0 baa 2 2 r/w 0 baa 1 1 r/w 0 baa 0 0 ?? ?? ?? ?? ?? ?? ?? ?? bit initial value read/write 31 unde- fined 24 unde- fined r/w bab 23 23 0 r/w bab 22 22 0 r/w bab 21 21 0 r/w bab 20 20 0 r/w bab 19 19 0 r/w bab 18 18 0 r/w bab 17 17 0 r/w bab 16 16 0 r/w 0 bab 7 7 r/w 0 bab 6 6 r/w 0 bab 5 5 r/w 0 bab 4 4 r/w 0 bab 3 3 r/w 0 bab 2 2 r/w 0 bab 1 1 r/w 0 bab 0 0 ?? ?? ?? ?? ?? ?? ?? ?? these bits hold the channel a or b pc break address
746 bcra?reak control register a h'fe08 pbc bit initial value read/write r/(w) * 0 cmfa 7 r/w 0 cda 6 r/w 0 bamra2 5 r/w 0 bamra1 4 r/w 0 bamra0 3 r/w 0 csela1 2 r/w 0 csela0 1 r/w 0 biea 0 break address mask register all bara bits are unmasked and included in break conditions baa0 (lowest bit) is masked, and not included in break conditions baa1 to 0 (lower 2 bits) are masked, and not included in break conditions baa2 to 0 (lower 3 bits) are masked, and not included in break conditions baa3 to 0 (lower 4 bits) are masked, and not included in break conditions baa7 to 0 (lower 8 bits) are masked, and not included in break conditions baa11 to 0 (lower 12 bits) are masked, and not included in break conditions baa15 to 0 (lower 16 bits) are masked, and not included in break conditions 0 1 0 1 0 1 0 1 0 1 0 1 0 1 break condition select 0 1 0 1 0 1 instruction fetch data read cycle data write cycle data read/write cycle break interrupt enable 0 1 pc break interrupts are disabled pc break interrupts are enabled cpu cycle/dtc cycle select 0 1 pc break is performed when cpu is bus master pc break is performed when cpu or dtc is bus master condition match flag a 0 1 note: * only 0 can be written, to clear the flag. [clearing condition] when 0 is written to cmfa after reading cmfa = 1 [setting condition] when a condition set for channel a is satisfied bcrb?reak control register b h'fe09 pbc bit the bit confi g uration is the same as for bcra initial value read/write r/w 0 cmfb 7 r/w 0 cdb 6 r/w 0 bamrb2 5 r/w 0 bamrb1 4 r/w 0 bamrb0 3 r/w 0 cselb1 2 r/w 0 cselb0 1 r/w 0 bieb 0
747 iscrh?rq sense control register h iscrl?rq sense control register l h'fe12 h'fe13 interrupt controller 15 irq7scb 0 r/w 14 irq7sca 0 r/w 13 irq6scb 0 r/w 12 irq6sca 0 r/w 11 irq5scb 0 r/w 8 irq4sca 0 r/w 10 irq5sca 0 r/w 9 irq4scb 0 r/w bit initial value r/w : : : 7 irq3scb 0 r/w 6 irq3sca 0 r/w 5 irq2scb 0 r/w 4 irq2sca 0 r/w 3 irq1scb 0 r/w 0 irq0sca 0 r/w 2 irq1sca 0 r/w 1 irq0scb 0 r/w bit initial value r/w : : : irq7 to irq4 sense control iscrh iscrl irq3 to irq0 sense control irqnscb 0 1 ( n= 7 to 0 ) irqnsca 0 1 0 1 interrupt request generation irqn input low level falling edge of irqn input rising edge of irqn input both falling and rising edges of irqn input
748 ier?rq enable register h'fe14 interrupt controller 7 irq7e 0 r/w 6 irq6e 0 r/w 5 irq5e 0 r/w 4 irq4e 0 r/w 3 irq3e 0 r/w 0 irq0e 0 r/w 2 irq2e 0 r/w 1 irq1e 0 r/w bit initial value r/w : : : irqn enable 0 1 irqn interrupts disabled irqn interrupts enabled (n= 7 to 0) isr?rq status register h'fe15 interrupt controller 7 irq7f 0 r/(w) * 6 irq6f 0 r/(w) * 5 irq5f 0 r/(w) * 4 irq4f 0 r/(w) * 3 irq3f 0 r/(w) * 0 irq0f 0 r/(w) * 2 irq2f 0 r/(w) * 1 irq1f 0 r/(w) * bit initial value r/w note: * onl y 0 can be written, to clear the fla g . : : : indicates the status of irq7 to irq0 interrupt requests
749 dtcer?tc enable registers h'fe16 to h'fe1e dtc 7 dtce7 0 r/w 6 dtce6 0 r/w 5 dtce5 0 r/w 4 dtce4 0 r/w 3 dtce3 0 r/w 0 dtce0 0 r/w 2 dtce2 0 r/w 1 dtce1 0 r/w bit initial value r/w : : : dtc activation enable 0 1 dtc activation by this interrupt is disabled [clearing conditions] ?when the disel bit is 1 and the data transfer has ended ?when the specified number of transfers have ended dtc activation by this interrupt is enabled [holding condition] when the disel bit is 0 and the specified number of transfers have not ended correspondence between interrupt sources and dtcer bit register 76543210 dtcera irq0 irq1 irq2 irq3 irq4 irq5 irq6 irq7 dtcerb adi tgi0a tgi0b tgi0c tgi0d tgi1a tgi1b dtcerc tgi2a tgi2b tgi3a tgi3b tgi3c tgi3d tgi4a tgi4b dtcerd tgi5a tgi5b cmia0 cmib0 cmia1 cmib1 dtcere rxi0 txi0 rxi1 txi1 dtcerf rxi2 txi2 dtceri rxi3 txi3
750 dtvecr?tc vector register h'fe1f dtc 7 swdte 0 r/(w) * 6 dtvec6 0 r/w 5 dtvec5 0 r/w 4 dtvec4 0 r/w 3 dtvec3 0 r/w 0 dtvec0 0 r/w 2 dtvec2 0 r/w 1 dtvec1 0 r/w note: * a value of 1 can always be written to the swdte bit, but 0 can only be written after 1 is read. bit initial value r/w : : : dtc software activation enable sets vector number for dtc software activation 0 1 dtc software activation is disabled [clearing condition] ?when the disel bit is 0 and the specified number of transfers have not ended dtc software activation is enabled [holding conditions] ?when the disel bit is 1 and data transfer has ended ?when the specified number of transfers have ended ?during data transfer due to software activation p1ddr?ort 1 data direction register h'fe30 port 1 7 p17ddr 0 w 6 p16ddr 0 w 5 p15ddr 0 w 4 p14ddr 0 w 3 p13ddr 0 w 0 p10ddr 0 w 2 p12ddr 0 w 1 p11ddr 0 w bit initial value read/write specify input or output for the pins of port 1
751 p3ddr?ort 3 data direction register h'fe32 port 3 7 undefined 6 p36ddr 0 w 5 p35ddr 0 w 4 p34ddr 0 w 3 p33ddr 0 w 0 p30ddr 0 w 2 p32ddr 0 w 1 p31ddr 0 w bit initial value read/write specif y input or output for the pins of port 3 p7ddr?ort 7 data direction register h'fe36 port 7 7 p77ddr 0 w 6 p76ddr 0 w 5 p75ddr 0 w 4 p74ddr 0 w 3 p73ddr 0 w 0 p70ddr 0 w 2 p72ddr 0 w 1 p71ddr 0 w bit initial value read/write specify input or output for the pins of port 7 paddr?ort a data direction register h'fe39 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3ddr 0 w 0 pa0ddr 0 w 2 pa2ddr 0 w 1 pa1ddr 0 w bit initial value read/write specif y input or output for the pins of port a pbddr?ort b data direction register h'fe3a port b 7 pb7ddr 0 w 6 pb6ddr 0 w 5 pb5ddr 0 w 4 pb4ddr 0 w 3 pb3ddr 0 w 0 pb0ddr 0 w 2 pb2ddr 0 w 1 pb1ddr 0 w bit initial value read/write specif y input or output for the pins of port b
752 pcddr?ort c data direction register h'fe3b port c 7 pc7ddr 0 w 6 pc6ddr 0 w 5 pc5ddr 0 w 4 pc4ddr 0 w 3 pc3ddr 0 w 0 pc0ddr 0 w 2 pc2ddr 0 w 1 pc1ddr 0 w bit initial value read/write specif y input or output for the pins of port c pdddr?ort d data direction register h'fe3c port d 7 pd7ddr 0 w 6 pd6ddr 0 w 5 pd5ddr 0 w 4 pd4ddr 0 w 3 pd3ddr 0 w 0 pd0ddr 0 w 2 pd2ddr 0 w 1 pd1ddr 0 w bit initial value read/write specif y input or output for the pins of port d peddr?ort e data direction register h'fe3d port e 7 pe7ddr 0 w 6 pe6ddr 0 w 5 pe5ddr 0 w 4 pe4ddr 0 w 3 pe3ddr 0 w 0 pe0ddr 0 w 2 pe2ddr 0 w 1 pe1ddr 0 w bit initial value read/write s p ecif y in p ut or out p ut for the p ins of p ort e
753 pfddr?ort f data direction register h'fe3e port f 7 pf7ddr 1 w 0 w 6 pf6ddr 0 w 0 w 5 pf5ddr 0 w 0 w 4 pf4ddr 0 w 0 w 3 pf3ddr 0 w 0 w 0 pf0ddr 0 w 0 w 2 pf2ddr 0 w 0 w 1 pf1ddr 0 w 0 w bit modes 4 to 6 initial value read/write mode 7 initial value read/write specif y input or output for the pins of port f pgddr?ort g data direction register h'fe3f port g 7 undefined undefined 6 undefined undefined 5 undefined undefined 4 pg4ddr 1 w 0 w 3 pg3ddr 0 w 0 w 0 pg0ddr 0 w 0 w 2 pg2ddr 0 w 0 w 1 pg1ddr 0 w 0 w bit modes 4 and 5 initial value read/write modes 6 and 7 initial value read/write specify input or output for the pins of port g
754 papcr?ort a mos pull-up control register h'fe40 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3pcr 0 r/w 0 pa0pcr 0 r/w 2 pa2pcr 0 r/w 1 pa1pcr 0 r/w bit initial value read/write controls the mos input pull-up function incorporated into port a on a bit-b y -bit basis pbpcr?ort b mos pull-up control register h'fe41 port b 7 pb7pcr 0 r/w 6 pb6pcr 0 r/w 5 pb5pcr 0 r/w 4 pb4pcr 0 r/w 3 pb3pcr 0 r/w 0 pb0pcr 0 r/w 2 pb2pcr 0 r/w 1 pb1pcr 0 r/w bit initial value read/write controls the mos input pull-up function incorporated into port b on a bit-by-bit basis pcpcr?ort c mos pull-up control register h'fe42 port c 7 pc7pcr 0 r/w 6 pc6pcr 0 r/w 5 pc5pcr 0 r/w 4 pc4pcr 0 r/w 3 pc3pcr 0 r/w 0 pc0pcr 0 r/w 2 pc2pcr 0 r/w 1 pc1pcr 0 r/w bit initial value read/write controls the mos input pull-up function incorporated into port c on a bit-b y -bit basis pdpcr?ort d mos pull-up control register h'fe43 port d 7 pd7pcr 0 r/w 6 pd6pcr 0 r/w 5 pd5pcr 0 r/w 4 pd4pcr 0 r/w 3 pd3pcr 0 r/w 0 pd0pcr 0 r/w 2 pd2pcr 0 r/w 1 pd1pcr 0 r/w bit initial value read/write controls the mos input pull-up function incorporated into port d on a bit-b y -bit basis
755 pepcr?ort e mos pull-up control register h'fe44 port e 7 pe7pcr 0 r/w 6 pe6pcr 0 r/w 5 pe5pcr 0 r/w 4 pe4pcr 0 r/w 3 pe3pcr 0 r/w 0 pe0pcr 0 r/w 2 pe2pcr 0 r/w 1 pe1pcr 0 r/w bit initial value read/write controls the mos input pull-up function incorporated into port e on a bit-by-bit basis p3odr?ort 3 open-drain control register h'fe46 port 3 7 undefined 6 p36odr 0 r/w 5 p35odr 0 r/w 4 p34odr 0 r/w 3 p33odr 0 r/w 0 p30odr 0 r/w 2 p32odr 0 r/w 1 p31odr 0 r/w bit initial value read/write controls the pmos on/off status for each port 3 pin (p36 to p30) paodr?ort a open-drain control register h'fe47 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3odr 0 r/w 0 pa0odr 0 r/w 2 pa2odr 0 r/w 1 pa1odr 0 r/w bit initial value read/write controls the pmos on/off status for each port a pin ( pa3 to pa0 )
756 tcr3?imer control register 3 h'fe80 tpu3 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value r/w : : : counter clear tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 tcnt clearing disabled tcnt cleared by tgrc compare match/input capture * 2 tcnt cleared by tgrd compare match/input capture * 2 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 0 1 notes: 1. synchronous operation setting is performed by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 0 1 0 1 0 1 0 1 0 1 0 1 select the input clock edge 0 1 0 1 count at rising edge count at falling edge count at both edges time prescaler internal clock: counts on ?1 internal clock: counts on ?4 internal clock: counts on ?16 internal clock: counts on ?64 external clock: counts on tclka pin input internal clock: counts on ?1024 internal clock: counts on ?256 internal clock: counts on ?4096 0 1 0 1 0 1 0 1 0 1 0 1 0 1
757 tmdr3?imer mode register 3 h'fe81 tpu3 7 1 6 1 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : buffer operation a 0 1 tgra operates normally tgra and tgrc used together for buffer operation modes normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 0 1 * : don? care notes: 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2. 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * buffer operation b 0 1 tgrb operates normally tgrb and tgrd used together for buffer operation
758 tior3h?imer i/o control register 3h h'fe82 tpu3 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : tgr3a i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt4 count-up/ count-down 0 1 * : don? care note: when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and ?1 is used as the tcnt4 count clock, this settin g is invalid and input capture is not g enerated. 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istioca3 pin capture input source is channel 4/count clock tgr3a is output compare register tgr3a is input capture register tgr3b i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt4 count-up/ count-down * 0 1 * : don? care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocb3 pin capture input source is channel 4/count clock tgr3b is output compare register tgr3b is input capture register
759 tior3l?imer i/o control register 3l h'fe83 tpu3 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w bit initial value r/w : : : tgr3c i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt4 count-up/ count-down 0 1 * : don? care note: note: 1. when the bfa bit in tmdr3 is set to 1 and tgr3c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. notes: 1. when bits tpsc2 to tpsc0 in tcr4 are set to b'000 and ?1 is used as the tcnt4 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr3 is set to 1 and tgr3d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. when tgrc or tgrd is designated for buffer operation, this setting is invalid and the register operates as a buffer re g ister. 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocc3 pin capture input source is channel 4/count clock tgr3c is output compare register tgr3c is input capture register tgr3d i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt4 count-up/ count-down * 1 0 1 * : don? care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocd3 pin capture input source is channel 4/count clock tgr3d is output compare register tgr3d is input capture register
760 tier3?imer interrupt enable register 3 h'fe84 tpu3 7 ttge 0 r/w 6 1 5 0 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w bit initial value r/w : : : tgr interrupt enable b tgr interrupt enable a 0 1 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 0 1 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled tgr interrupt enable c 0 1 interrupt requests (tgic) by tgfc bit disabled interrupt requests (tgic) by tgfc bit enabled tgr interrupt enable d 0 1 interrupt requests (tgid) by tgfd bit disabled interrupt requests (tgid) by tgfd bit enabled overflow interrupt enable 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled a/d conversion start request enable 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled
761 tsr3?imer status register 3 h'fe85 tpu3 7 1 6 1 5 0 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 0 tgfa 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * bit initial value r/w note: can onl y be written with 0 for fla g clearin g . : : : overflow flag 0 1 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) input capture/output compare flag a 0 1 [clearing conditions] ?when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfa after reading tgfa = 1 [setting conditions] ?when tcnt = tgra while tgra is functioning as output compare register ?when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 1 [clearing conditions] ?when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ?when tcnt = tgrb while tgrb is functioning as output compare register ?when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register input capture/output compare flag c 0 1 [clearing conditions] ?when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfc after reading tgfc = 1 [setting conditions] ?when tcnt = tgrc while tgrc is functioning as output compare register ?when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register input capture/output compare flag d 0 1 [clearing conditions] ?when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfd after reading tgfd = 1 [setting conditions] ?when tcnt = tgrd while tgrd is functioning as output compare register ?when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register
762 tcnt3?imer counter 3 h'fe86 tpu3 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value r/w : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w u p -counter tgr3a?imer general register 3a tgr3b?imer general register 3b tgr3c?imer general register 3c tgr3d?imer general register 3d h'fe88 h'fe8a h'fe8c h'fe8e tpu3 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value r/w : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w
763 tcr4?imer control register 4 h'fe90 tpu4 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value r/w : : : time prescaler internal clock: counts on ?1 internal clock: counts on ?4 internal clock: counts on ?16 internal clock: counts on ?64 external clock: counts on tclka pin input external clock: counts on tclkc pin input internal clock: counts on ?1024 counts on tcnt5 overflow/underflow 0 1 note: this setting is ignored when channel 4 is in phase counting mode. 0 1 0 1 0 1 0 1 0 1 0 1 select the input clock edge count at rising edge count at falling edge count at both edges 0 1 note: this setting is ignored when channel 4 is in phase counting mode. 0 1 counter clear tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 0 1 note: synchronous operation setting is performed by setting the sync bit in tsyr to 1. 0 1 0 1
764 tmdr4?imer mode register 4 h'fe91 tpu4 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : mode 0 1 note: md3 is a reserved bit. in a write, it should always be written with 0. * : don? care 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4
765 tior4?imer i/o control register 4 h'fe92 tpu4 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : tgr4a i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at generation of tgr3a compare match/input capture 0 1 * : don? care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istioca4 pin capture input source is tgr3a compare match/ input capture tgr4a is output compare register tgr4a is input capture register 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at generation of tgr3c compare match/input capture 0 1 * : don? care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocb4 pin capture input source is tgr3c compare match/ input capture tgr4b is output compare register tgr4b is input capture register tgr4b i/o control
766 tier4?imer interrupt enable register 4 h'fe94 tpu4 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w bit initial value r/w : : : tgr interrupt enable b tgr interrupt enable a 0 1 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 0 1 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled overflow interrupt enable 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled underflow interrupt enable 0 1 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled a/d conversion start request enable 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled
767 tsr4?imer status register 4 h'fe95 tpu4 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * bit initial value r/w : : : note: can only be written with 0 for fla g clearin g . input capture/output compare flag a 0 1 [clearing conditions] ?when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfa after reading tgfa = 1 [setting conditions] ?when tcnt = tgra while tgra is functioning as output compare register ?when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 1 [clearing conditions] ?when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ?when tcnt = tgrb while tgrb is functioning as output compare register ?when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register overflow flag 0 1 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) underflow flag 0 1 [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) count direction flag 0 1 tcnt counts down tcnt counts up
768 tcnt4?imer counter 4 h'fe96 tpu4 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value r/w : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note : these counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. in other cases they function as up-counters. up/down-counter * tgr4a?imer general register 4a tgr4b?imer general register 4b h'fe98 h'fe9a tpu4 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value r/w : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w
769 tcr5?imer control register 5 h'fea0 tpu5 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value r/w : : : time prescaler internal clock: counts on ?1 internal clock: counts on ?4 internal clock: counts on ?16 internal clock: counts on ?64 external clock: counts on tclka pin input external clock: counts on tclkc pin input internal clock: counts on ?256 external clock: counts on tclkd pin input 0 1 note: this setting is ignored when channel 5 is in phase counting mode. 0 1 0 1 0 1 0 1 0 1 0 1 select the input clock edge count at rising edge count at falling edge count at both edges 0 1 note: this setting is ignored when channel 5 is in phase counting mode. 0 1 counter clear tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 0 1 note: synchronous operation setting is performed by setting the sync bit in tsyr to 1. 0 1 0 1
770 tmdr5?imer mode register 5 h'fea1 tpu5 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : mode 0 1 note: md3 is a reserved bit. in a write, it should always be written with 0. * : don? care 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4
771 tior5?imer i/o control register 5 h'fea2 tpu5 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : tgr5a i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 1 * : don? care 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istioca5 pin tgr5a is output compare register tgr5a is input capture register tgr5b i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 1 * : don? care 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocb5 pin tgr5b is output compare register tgr5b is input capture register
772 tier5?imer interrupt enable register 5 h'fea4 tpu5 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w bit initial value r/w : : : tgr interrupt enable b tgr interrupt enable a 0 1 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 0 1 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled overflow interrupt enable 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled underflow interrupt enable 0 1 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled a/d conversion start request enable 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled
773 tsr5?imer status register 5 h'fea5 tpu5 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * bit initial value r/w : : : note: can only be written with 0 for flag clearing. input capture/output compare flag a 0 1 [clearing conditions] ?when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfa after reading tgfa = 1 [setting conditions] ?when tcnt = tgra while tgra is functioning as output compare register ?when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 1 [clearing conditions] ?when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ?when tcnt = tgrb while tgrb is functioning as output compare register ?when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register overflow flag 0 1 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) underflow flag 0 1 [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) count direction flag 0 1 tcnt counts down tcnt counts up
774 tcnt5?imer counter 5 h'fea6 tpu5 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value r/w : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note : these counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. in other cases they function as up-counters. up/down-counter * tgr5a?imer general register 5a tgr5b?imer general register 5b h'fea8 h'feaa tpu5 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value r/w : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w tstr?imer start register h'feb0 tpu 7 0 6 0 5 cst5 0 r/w 4 cst4 0 r/w 3 cst3 0 r/w 0 cst0 0 r/w 2 cst2 0 r/w 1 cst1 0 r/w bit initial value r/w : : : counter start 0 1 note: if 0 is written to the cst bit during operation with the tioc pin designated for output, the counter stops but the tioc pin output compare output level is retained. if tior is written to when the cst bit is cleared to 0, the pin output level will be changed to the set initial output value. tcntn count operation is stopped tcntn performs count operation (n= 5 to 0)
775 tsyr?imer synchro register h'feb1 tpu 7 0 6 0 5 sync5 0 r/w 4 sync4 0 r/w 3 sync3 0 r/w 0 sync0 0 r/w 2 sync2 0 r/w 1 sync1 0 r/w bit initial value r/w notes: to set synchronous operation, the sync bits for at least two channels must be set to 1. to set synchronous clearing, in addition to the sync bit , the tcnt clearing source must also be set by means of bits cclr2 to cclr0 in tcr. 1. 2. : : : timer synchro 0 1 tcntn operates independently (tcnt presetting/clearing is unrelated to other channels) tcntn performs synchronous operation tcnt synchronous presetting/synchronous clearing is possible (n= 5 to 0)
776 ipra?nterrupt priority register a iprb ?nterrupt priority register b iprc?nterrupt priority register c iprd?nterrupt priority register d ipre ?nterrupt priority register e iprf ?nterrupt priority register f iprg?nterrupt priority register g iprh?nterrupt priority register h ipri ?nterrupt priority register i iprj ?nterrupt priority register j iprk?nterrupt priority register k ipro?nterrupt priority register o h'fec0 h'fec1 h'fec2 h'fec3 h'fec4 h'fec5 h'fec6 h'fec7 h'fec8 h'fec9 h'feca h'fece interrupt controller 7 0 6 ipr6 1 r/w 5 ipr5 1 r/w 4 ipr4 1 r/w 3 0 0 ipr0 1 r/w 2 ipr2 1 r/w 1 ipr1 1 r/w bit initial value r/w correspondence between interrupt sources and ipr settings note: * reserved bits. these bits cannot be modified and are alwa y s read as 1. : : : set priority (levels 7 to 0) for interrupt sources bits register 6 to 4 2 to 0 ipra irq0 irq1 iprb irq2, irq3 irq4, irq5 iprc irq6, irq7 dtc iprd watchdog timer 0 * ipre pc break a/d converter, watchdog timer 1 iprf tpu channel 0 tpu channel 1 iprg tpu channel 2 tpu channel 3 iprh tpu channel 4 tpu channel 5 ipri 8-bit timer channel 0 8-bit timer channel 1 iprj * sci channel 0 iprk sci channel 1 sci channel 2 ipro sci channel 3 *
777 abwcr?us width control register h'fed0 bus controller 7 abw7 1 r/w 0 r/w 6 abw6 1 r/w 0 r/w 5 abw5 1 r/w 0 r/w 4 abw4 1 r/w 0 r/w 3 abw3 1 r/w 0 r/w 0 abw0 1 r/w 0 r/w 2 abw2 1 r/w 0 r/w 1 abw1 1 r/w 0 r/w bit : initial value : modes 5 to 7 mode 4 : r/w initial value : : r/w area 7 to 0 bus width control 0 1 area n is designated for 16-bit access area n is designated for 8-bit access (n= 7 to 0) astcr?ccess state control register h'fed1 bus controller 7 ast7 1 r/w 6 ast6 1 r/w 5 ast5 1 r/w 4 ast4 1 r/w 3 ast3 1 r/w 0 ast0 1 r/w 2 ast2 1 r/w 1 ast1 1 r/w bit initial value r/w : : : area 7 to 0 access state control 0 1 area n is designated for 2-state access wait state insertion in area n external space is disabled area n is designated for 3-state access wait state insertion in area n external space is enabled (n= 7 to 0)
778 wcrh?ait control register h h'fed2 bus controller 7 w71 1 r/w 6 w70 1 r/w 5 w61 1 r/w 4 w60 1 r/w 3 w51 1 r/w 0 w40 1 r/w 2 w50 1 r/w 1 w41 1 r/w bit initial value r/w : : : area 7 wait control area 4 wait control program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 area 5 wait control area 6 wait control
779 wcrl?ait control register l h'fed3 bus controller 7 w31 1 r/w 6 w30 1 r/w 5 w21 1 r/w 4 w20 1 r/w 3 w11 1 r/w 0 w00 1 r/w 2 w10 1 r/w 1 w01 1 r/w bit initial value r/w : : : area 3 wait control area 0 wait control program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 program wait not inserted 1 program wait state inserted 2 program wait states inserted 3 program wait states inserted 0 1 0 1 0 1 area 1 wait control area 2 wait control
780 bcrh?us control register h h'fed4 bus controller 7 icis1 1 r/w 6 icis0 1 r/w 5 brstrm 0 r/w 4 brsts1 1 r/w 3 brsts0 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : reserved only 0 should be written to these bits burst cycle select 0 0 1 max. 4 words in burst access max. 8 words in burst access burst cycle select 1 0 1 burst cycle comprises 1 state burst cycle comprises 2 states area 0 burst rom enable 0 1 area 0 is basic bus interface area 0 is burst rom interface idle cycle insert 0 0 1 idle cycle not inserted in case of successive external read and external write cycles idle cycle inserted in case of successive external read and external write cycles idle cycle insert 1 0 1 idle cycle not inserted in case of successive external read cycles in different areas idle cycle inserted in case of successive external read cycles in different areas
781 bcrl?us control register l h'fed5 bus controller 7 brle 0 r/w 6 0 r/w 5 0 4 0 r/w 3 1 r/w 0 waite 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : wait pin enable reserved only 0 should be written to this bit reserved only 0 should be written to this bit reserved only 1 should be written to this bit reserved only 0 should be written to this bit reserved only 0 should be written to this bit reserved this bit cannot be modified 0 1 wait input by wait pin disabled wait input by wait pin enabled bus release enable 0 1 external bus release is disabled external bus release is enabled
782 p1dr?ort 1 data register h'ff00 port 1 7 p17dr 0 r/w 6 p16dr 0 r/w 5 p15dr 0 r/w 4 p14dr 0 r/w 3 p13dr 0 r/w 0 p10dr 0 r/w 2 p12dr 0 r/w 1 p11dr 0 r/w bit initial value read/write stores output data for the port 1 pins (p17 to p10) p3dr?ort 3 data register h'ff02 port 3 7 undefined 6 p36dr 0 r/w 5 p35dr 0 r/w 4 p34dr 0 r/w 3 p33dr 0 r/w 0 p30dr 0 r/w 2 p32dr 0 r/w 1 p31dr 0 r/w bit initial value read/write stores output data for the port 3 pins ( p36 to p30 ) p7dr?ort 7 data register h'ff06 port 7 7 p77dr 0 r/w 6 p76dr 0 r/w 5 p75dr 0 r/w 4 p74dr 0 r/w 3 p73dr 0 r/w 0 p70dr 0 r/w 2 p72dr 0 r/w 1 p71dr 0 r/w bit initial value read/write stores output data for the port 7 pins (p77 to p70) padr?ort a data register h'ff09 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3dr 0 r/w 0 pa0dr 0 r/w 2 pa2dr 0 r/w 1 pa1dr 0 r/w bit initial value read/write stores output data for the port a pins ( pa3 to pa0 )
783 pbdr?ort b data register h'ff0a port b 7 pb7dr 0 r/w 6 pb6dr 0 r/w 5 pb5dr 0 r/w 4 pb4dr 0 r/w 3 pb3dr 0 r/w 0 pb0dr 0 r/w 2 pb2dr 0 r/w 1 pb1dr 0 r/w bit initial value read/write stores output data for the port b pins ( pb7 to pb0 ) pcdr?ort c data register h'ff0b port c 7 pc7dr 0 r/w 6 pc6dr 0 r/w 5 pc5dr 0 r/w 4 pc4dr 0 r/w 3 pc3dr 0 r/w 0 pc0dr 0 r/w 2 pc2dr 0 r/w 1 pc1dr 0 r/w bit initial value read/write stores output data for the port c pins ( pc7 to pc0 ) pddr?ort d data register h'ff0c port d 7 pd7dr 0 r/w 6 pd6dr 0 r/w 5 pd5dr 0 r/w 4 pd4dr 0 r/w 3 pd3dr 0 r/w 0 pd0dr 0 r/w 2 pd2dr 0 r/w 1 pd1dr 0 r/w bit initial value read/write stores output data for the port d pins ( pd7 to pd0 ) pedr?ort e data register h'ff0d port e 7 pe7dr 0 r/w 6 pe6dr 0 r/w 5 pe5dr 0 r/w 4 pe4dr 0 r/w 3 pe3dr 0 r/w 0 pe0dr 0 r/w 2 pe2dr 0 r/w 1 pe1dr 0 r/w bit initial value read/write stores output data for the port e pins ( pe7 to pe0 )
784 pfdr?ort f data register h'ff0e port f 7 pf7dr 0 r/w 6 pf6dr 0 r/w 5 pf5dr 0 r/w 4 pf4dr 0 r/w 3 pf3dr 0 r/w 0 pf0dr 0 r/w 2 pf2dr 0 r/w 1 pf1dr 0 r/w bit initial value read/write stores output data for the port f pins (pf7 to pf0) pgdr?ort g data register h'ff0f port g 7 undefined 6 undefined 5 undefined 4 pg4dr 0 r/w 3 pg3dr 0 r/w 0 pg0dr 0 r/w 2 pg2dr 0 r/w 1 pg1dr 0 r/w bit initial value read/write stores output data for the port g pins (pg4 to pg0)
785 tcr0?timer control register 0 h'ff10 tpu0 7 cclr2 0 r/w 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value r/w : : : counter clear tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 tcnt clearing disabled tcnt cleared by tgrc compare match/input capture * 2 tcnt cleared by tgrd compare match/input capture * 2 tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 1 0 1 notes: 1. synchronous operation setting is performed by setting the sync bit in tsyr to 1. 2. when tgrc or tgrd is used as a buffer register, tcnt is not cleared because the buffer register setting has priority, and compare match/input capture does not occur. 0 1 0 1 0 1 0 1 0 1 0 1 select the input clock edge 0 1 0 1 count at rising edge count at falling edge count at both edges time prescaler internal clock: counts on ?1 internal clock: counts on ?4 internal clock: counts on ?16 internal clock: counts on ?64 external clock: counts on tclka pin input external clock: counts on tclkb pin input external clock: counts on tclkc pin input external clock: counts on tclkd pin input 0 1 0 1 0 1 0 1 0 1 0 1 0 1
786 tmdr0?timer mode register 0 h'ff11 tpu0 7 1 6 1 5 bfb 0 r/w 4 bfa 0 r/w 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : buffer operation a 0 1 tgra operates normally tgra and tgrc used together for buffer operation modes normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4 0 1 * : don? care notes: 1. md3 is a reserved bit. in a write, it should always be written with 0. 2. phase counting mode cannot be set for channels 0 and 3. in this case, 0 should always be written to md2. 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * buffer operation b 0 1 tgrb operates normally tgrb and tgrd used together for buffer operation
787 tior0h?timer i/o control register 0h h'ff12 tpu0 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : note: when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and ?1 is used as the tcnt1 count clock, this settin g is invalid and input capture is not g enerated. tgr0a i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt1 count- up/count-down 0 1 * : don? care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istioca0 pin capture input source is channel 1/count clock tgr0a is output compare register tgr0a is input capture register tgr0b i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt1 count- up/count-down * 1 0 1 * : don? care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocb0 pin capture input source is channel 1/count clock tgr0b is output compare register tgr0b is input capture register
788 tior0l?timer i/o control register 0l h'ff13 tpu0 7 iod3 0 r/w 6 iod2 0 r/w 5 iod1 0 r/w 4 iod0 0 r/w 3 ioc3 0 r/w 0 ioc0 0 r/w 2 ioc2 0 r/w 1 ioc1 0 r/w notes: 1. when bits tpsc2 to tpsc0 in tcr1 are set to b'000 and ?1 is used as the tcnt1 count clock, this setting is invalid and input capture is not generated. 2. when the bfb bit in tmdr0 is set to 1 and tgr0d is used as a buffer register, this setting is invalid and input capture/output compare is not generated. bit initial value r/w : : : note: when the bfa bit in tmdr0 is set to 1 and tgr0c is used as a buffer register, this setting is invalid and input capture/output compare is not generated. note: when tgrc or tgrd is designated for buffer operation, this setting is invalid and the re g ister operates as a buffer re g ister. tgr0c i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt1 count- up/count-down 0 1 * : don? care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocc0 pin capture input source is channel 1/count clock tgr0c is output compare register * 1 tgr0c is input capture register * 1 tgr0d i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at tcnt1 count- up/count-down * 1 0 1 * : don? care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source is tiocd0 pin capture input source is channel 1/count clock tgr0d is output compare register * 2 tgr0d is input capture register * 2
789 tier0?timer interrupt enable register 0 h'ff14 tpu0 7 ttge 0 r/w 6 1 5 0 4 tciev 0 r/w 3 tgied 0 r/w 0 tgiea 0 r/w 2 tgiec 0 r/w 1 tgieb 0 r/w bit initial value r/w : : : tgr interrupt enable b tgr interrupt enable a 0 1 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 0 1 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled tgr interrupt enable c 0 1 interrupt requests (tgic) by tgfc bit disabled interrupt requests (tgic) by tgfc bit enabled tgr interrupt enable d 0 1 interrupt requests (tgid) by tgfd bit disabled interrupt requests (tgid) by tgfd bit enabled overflow interrupt enable 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled a/d conversion start request enable 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled
790 tsr0?timer status register 0 h'ff15 tpu0 7 1 6 1 5 0 4 tcfv 0 r/(w) * 3 tgfd 0 r/(w) * 0 tgfa 0 r/(w) * 2 tgfc 0 r/(w) * 1 tgfb 0 r/(w) * bit initial value r/w note: can only be written with 0 for flag clearing. : : : overflow flag 0 1 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) input capture/output compare flag a 0 1 [clearing conditions] ?when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfa after reading tgfa = 1 [setting conditions] ?when tcnt = tgra while tgra is functioning as output compare register ?when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 1 [clearing conditions] ?when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ?when tcnt = tgrb while tgrb is functioning as output compare register ?when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register input capture/output compare flag c 0 1 [clearing conditions] ?when dtc is activated by tgic interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfc after reading tgfc = 1 [setting conditions] ?when tcnt = tgrc while tgrc is functioning as output compare register ?when tcnt value is transferred to tgrc by input capture signal while tgrc is functioning as input capture register input capture/output compare flag d 0 1 [clearing conditions] ?when dtc is activated by tgid interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfd after reading tgfd = 1 [setting conditions] ?when tcnt = tgrd while tgrd is functioning as output compare register ?when tcnt value is transferred to tgrd by input capture signal while tgrd is functioning as input capture register
791 tcnt0?timer counter 0 h'ff16 tpu0 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value r/w : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w u p -counter tgr0a?imer general register 0a tgr0b?imer general register 0b tgr0c?imer general register 0c tgr0d?imer general register 0d h'ff18 h'ff1a h'ff1c h'ff1e tpu0 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value r/w : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w
792 tcr1?timer control register 1 h'ff20 tpu1 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value r/w : : : time prescaler internal clock: counts on ?1 internal clock: counts on ?4 internal clock: counts on ?16 internal clock: counts on ?64 external clock: counts on tclka pin input external clock: counts on tclkb pin input internal clock: counts on ?256 counts on tcnt2 overflow/underflow 0 1 note: this setting is ignored when channel 1 is in phase counting mode. 0 1 0 1 0 1 0 1 0 1 0 1 select the input clock edge count at rising edge count at falling edge count at both edges 0 1 note: * this setting is ignored when channel 1 is in phase counting mode. 0 1 * counter clear tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 0 1 note: * synchronous operation setting is performed by setting the sync bit in tsyr to 1. 0 1 0 1
793 tmdr1?timer mode register 1 h'ff21 tpu1 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : mode 0 1 note: md3 is a reserved bit. in a write, it should always be written with 0. * : don? care 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4
794 tior1?timer i/o control register 1 h'ff22 tpu1 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : tgr1a i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at generation of channel 0/tgr0a compare match/ input capture 0 1 * : don? care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istioca1 pin capture input source is tgr0a compare match/ input capture tgr1a is output compare register tgr1a is input capture register 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges input capture at generation of tgr0c compare match/input capture 0 1 * : don? care 0 1 0 1 0 1 0 1 0 1 * 0 1 0 1 0 1 0 1 0 1 * * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocb1 pin capture input source is tgr0c compare match/ input capture tgr1b is output compare register tgr1b is input capture register tgr1b i/o control
795 tier1?timer interrupt enable register 1 h'ff24 tpu1 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w bit initial value r/w : : : tgr interrupt enable b tgr interrupt enable a 0 1 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 0 1 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled overflow interrupt enable 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled underflow interrupt enable 0 1 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled a/d conversion start request enable 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled
796 tsr1?timer status register 1 h'ff25 tpu1 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * bit initial value r/w : : : note: can onl y be written with 0 for fla g clearin g . input capture/output compare flag a 0 1 [clearing conditions] ?when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfa after reading tgfa = 1 [setting conditions] ?when tcnt = tgra while tgra is functioning as output compare register ?when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 1 [clearing conditions] ?when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ?when tcnt = tgrb while tgrb is functioning as output compare register ?when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register overflow flag 0 1 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) underflow flag 0 1 [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) count direction flag 0 1 tcnt counts down tcnt counts up
797 tcnt1?timer counter 1 h'ff26 tpu1 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value r/w : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note : these counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. in other cases they function as up-counters. up/down-counter * tgr1a?imer general register 1a tgr1b?imer general register 1b h'ff28 h'ff2a tpu1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value r/w : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w
798 tcr2?timer control register 2 h'ff30 tpu2 7 0 6 cclr1 0 r/w 5 cclr0 0 r/w 4 ckeg1 0 r/w 3 ckeg0 0 r/w 0 tpsc0 0 r/w 2 tpsc2 0 r/w 1 tpsc1 0 r/w bit initial value r/w : : : time prescaler internal clock: counts on ?1 internal clock: counts on ?4 internal clock: counts on ?16 internal clock: counts on ?64 external clock: counts on tclka pin input external clock: counts on tclkb pin input external clock: counts on tclkc pin input internal clock: counts on ?1024 0 1 note: this setting is ignored when channel 2 is in phase counting mode. 0 1 0 1 0 1 0 1 0 1 0 1 select the input clock edge count at rising edge count at falling edge count at both edges 0 1 note: this setting is ignored when channel 2 is in phase counting mode. 0 1 counter clear tcnt clearing disabled tcnt cleared by tgra compare match/input capture tcnt cleared by tgrb compare match/input capture tcnt cleared by counter clearing for another channel performing synchronous clearing/synchronous operation * 0 1 note: synchronous operation setting is performed by setting the sync bit in tsyr to 1. 0 1 0 1
799 tmdr2?timer mode register 2 h'ff31 tpu2 7 1 6 1 5 0 4 0 3 md3 0 r/w 0 md0 0 r/w 2 md2 0 r/w 1 md1 0 r/w bit initial value r/w : : : mode 0 1 note: md3 is a reserved bit. in a write, it should always be written with 0. * : don? care 0 1 * 0 1 0 1 * 0 1 0 1 0 1 0 1 * normal operation reserved pwm mode 1 pwm mode 2 phase counting mode 1 phase counting mode 2 phase counting mode 3 phase counting mode 4
800 tior2?timer i/o control register 2 h'ff32 tpu2 7 iob3 0 r/w 6 iob2 0 r/w 5 iob1 0 r/w 4 iob0 0 r/w 3 ioa3 0 r/w 0 ioa0 0 r/w 2 ioa2 0 r/w 1 ioa1 0 r/w bit initial value r/w : : : tgr2a i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 1 * : don? care 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istioca2 pin tgr2a is output compare register tgr2a is input capture register tgr2b i/o control 0 output at compare match 1 output at compare match toggle output at compare match 0 output at compare match 1 output at compare match toggle output at compare match input capture at rising edge input capture at falling edge input capture at both edges 0 1 * : don? care 0 1 * 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 * output disabled initial output is 0 output output disabled initial output is 1 output capture input source istiocb2 pin tgr2b is output compare register tgr2b is input capture register
801 tier2?timer interrupt enable register 2 h'ff34 tpu2 7 ttge 0 r/w 6 1 5 tcieu 0 r/w 4 tciev 0 r/w 3 0 0 tgiea 0 r/w 2 0 1 tgieb 0 r/w bit initial value r/w : : : tgr interrupt enable b tgr interrupt enable a 0 1 interrupt requests (tgib) by tgfb bit disabled interrupt requests (tgib) by tgfb bit enabled 0 1 interrupt requests (tgia) by tgfa bit disabled interrupt requests (tgia) by tgfa bit enabled overflow interrupt enable 0 1 interrupt requests (tciv) by tcfv disabled interrupt requests (tciv) by tcfv enabled underflow interrupt enable 0 1 interrupt requests (tciu) by tcfu disabled interrupt requests (tciu) by tcfu enabled a/d conversion start request enable 0 1 a/d conversion start request generation disabled a/d conversion start request generation enabled
802 tsr2?timer status register 2 h'ff35 tpu2 7 tcfd 1 r 6 1 5 tcfu 0 r/(w) * 4 tcfv 0 r/(w) * 3 0 0 tgfa 0 r/(w) * 2 0 1 tgfb 0 r/(w) * bit initial value r/w : : : note: can only be written with 0 for flag clearing. input capture/output compare flag a 0 1 [clearing conditions] ?when dtc is activated by tgia interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfa after reading tgfa = 1 [setting conditions] ?when tcnt = tgra while tgra is functioning as output compare register ?when tcnt value is transferred to tgra by input capture signal while tgra is functioning as input capture register input capture/output compare flag b 0 1 [clearing conditions] ?when dtc is activated by tgib interrupt while disel bit of mrb in dtc is 0 ?when 0 is written to tgfb after reading tgfb = 1 [setting conditions] ?when tcnt = tgrb while tgrb is functioning as output compare register ?when tcnt value is transferred to tgrb by input capture signal while tgrb is functioning as input capture register overflow flag 0 1 [clearing condition] when 0 is written to tcfv after reading tcfv = 1 [setting condition] when the tcnt value overflows (changes from h'ffff to h'0000 ) underflow flag 0 1 [clearing condition] when 0 is written to tcfu after reading tcfu = 1 [setting condition] when the tcnt value underflows (changes from h'0000 to h'ffff) count direction flag 0 1 tcnt counts down tcnt counts up
803 tcnt2?timer counter 2 h'ff36 tpu2 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 8 0 r/w 10 0 r/w 9 0 r/w bit initial value r/w : : : 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w note : these counters can be used as up/down-counters only in phase counting mode or when counting overflow/underflow on another channel. in other cases they function as up-counters. up/down-counter * tgr2a?imer general register 2a tgr2b?imer general register 2b h'ff38 h'ff3a tpu2 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 8 1 r/w 10 1 r/w 9 1 r/w bit initial value r/w : : : 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w
804 tcr0?timer control register 0 tcr1?timer control register 1 h'ff68 h'ff69 8-bit timer channel 0 8-bit timer channel 1 7 cmieb 0 r/w 6 cmiea 0 r/w 5 ovie 0 r/w 4 cclr1 0 r/w 3 cclr0 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value r/w : : : clock select clock input disabled internal clock, counted at falling edge of ?8 internal clock, counted at falling edge of ?64 internal clock, counted at falling edge of ?8192 for channel 0: count at tcnt1 overflow signal * for channel 1: count at tcnt0 compare match a * external clock, counted at rising edge external clock, counted at falling edge external clock, counted at both rising and falling edges 0 1 note: if the count input of channel 0 is the tcnt1 overflow signal and that of channel 1 is the tcnt0 compare match signal, no incrementing clock is generated. do not use this setting. 0 1 0 1 0 1 0 1 0 1 0 1 counter clear clear is disabled clear by compare match a clear by compare match b clear by rising edge of external reset input 0 1 0 1 0 1 timer overflow interrupt enable ovf interrupt requests (ovi) are disabled ovf interrupt requests (ovi) are enabled 0 1 compare match interrupt enable a cmfa interrupt requests (cmia) are disabled cmfa interrupt requests (cmia) are enabled 0 1 compare match interrupt enable b cmfb interrupt requests (cmib) are disabled cmfb interrupt requests (cmib) are enabled 0 1
805 tcsr0?timer control/status register 0 tcsr1?timer control/status register 1 h'ff6a h'ff6b tmr0 tmr1 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 adte 0 r/w 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w only 0 can be written to bits 7 to 5, to clear these flags. bit initial value r/w : : : note: * 7 cmfb 0 r/(w) * 6 cmfa 0 r/(w) * 5 ovf 0 r/(w) * 4 1 3 os3 0 r/w 0 os0 0 r/w 2 os2 0 r/w 1 os1 0 r/w bit initial value r/w : : : tcsr0 tcsr1 output select 0 1 0 1 0 1 no change when compare match a occurs 0 is output when compare match a occurs 1 is output when compare match a occurs output is inverted when compare match a occurs (toggle output) output select 0 1 0 1 0 1 no change when compare match b occurs 0 is output when compare match b occurs 1 is output when compare match b occurs output is inverted when compare match b occurs (toggle output) a/d trigger enable (tcsr0 only) 0 1 a/d converter start requests by compare match a are disabled a/d converter start requests by compare match a are enabled timer overflow flag 0 1 [clearing condition] cleared by reading ovf when ovf = 1, then writing 0 to ovf [setting condition] set when tcnt overflows from h'ff to h'00 compare match flag a 0 1 [clearing conditions] ?cleared by reading cmfa when cmfa = 1, then writing 0 to cmfa ?when dtc is activated by cmia interrupt while disel bit of mrb in dtc is 0 [setting condition] set when tcnt matches tcora compare match flag b 0 1 [clearing conditions] ?cleared by reading cmfb when cmfb = 1, then writing 0 to cmfb ?when dtc is activated by cmib interrupt while disel bit of mrb in dtc is 0 [setting condition] set when tcnt matches tcorb
806 tcora0?time constant register a0 tcora1?time constant register a1 h'ff6c h'ff6d tmr0 tmr1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcora0 tcora1 bit initial value r/w : : : tcorb0?ime constant register b0 tcorb1?ime constant register b1 h'ff6e h'ff6f tmr0 tmr1 15 1 r/w 14 1 r/w 13 1 r/w 12 1 r/w 11 1 r/w 10 1 r/w 9 1 r/w 8 1 r/w 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 2 1 r/w 1 1 r/w 0 1 r/w tcorb0 tcorb1 bit initial value r/w : : : tcnt0?imer counter 0 tcnt1?imer counter 1 h'ff70 h'ff71 tmr0 tmr1 15 0 r/w 14 0 r/w 13 0 r/w 12 0 r/w 11 0 r/w 10 0 r/w 9 0 r/w 8 0 r/w 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 2 0 r/w 1 0 r/w 0 0 r/w tcnt0 tcnt1 bit initial value r/w : : :
807 tcsr0?timer control/status register h'ff74(w) h'ff74(r) wdt0 7 ovf 0 r/(w) * 1 6 wt/it 0 r/w 5 tme 0 r/w 4 1 3 1 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write note: 1. only 0 can be written, to clear the flag. note: 2. the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs. tcsr is write-protected by a password to prevent accidental overwriting. for details see section 12.2.5, notes on register access. timer enable 0 1 tcnt is initialized to h'00 and count operation is halted tcnt counts timer mode select 0 1 interval timer mode: interval timer interrupt (wovi) request is sent to cpu when tcnt overflows watchdog timer mode: internal reset can be selected when tcnt overflows overflow flag 0 1 [clearing conditions] overflow flag read tcsr when ovf = 1, then write 0 in ovf [setting condition] when tcnt overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the internal reset. clock select clock overflow period * 2 (when ?= 10 mhz) ?2 (initial value) 51.2 s ?64 1.6 ms ?128 3.2 ms ?512 13.2 ms ?2048 52.4 ms ?8192 209.8 ms ?32768 838.8 ms ?131072 3.368 s 0 1 0 1 0 1 0 1 0 1 0 1 0 1 cks2 cks1 cks0
808 tcnt0?timer counter h'ff74(w) h'ff75(r) wdt0 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : rstcsr?eset control/status register h'ff76(w) h'ff77(r) wdt0 7 wovf 0 r/(w) * 6 rste 0 r/w 5 rsts 0 r/w 4 1 3 1 0 1 2 1 1 1 bit initial value r/w : : : note: * only 0 can be written, to clear the flag. rstcsr is write-protected by a password to prevent accidental overwriting. for details see section 12.2.5, notes on re g ister access. reset select 0 1 power-on reset manual reset reset enable 0 1 note: * the chip is not reset internally, but tcnt and tcsr in wdt0 are reset. no internal reset when tcnt overflows * internal reset is generated when tcnt overflows watchdog overflow flag 0 1 [clearing condition] cleared by reading tcsr when wovf = 1, then writing 0 to wovf [setting condition] when tcnt overflows (from h?f to h?0) in watchdog timer mode
809 smr0?serial mode register 0 h'ff78 sci0 7 c/a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value r/w : : : multiprocessor mode clock select 0 1 multiprocessor function disabled multiprocessor format selected parity mode 0 1 even parity odd parity parity enable 0 1 parity bit addition and checking disabled parity bit addition and checking enabled character length 0 1 note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. 8-bit data 7-bit data * selects asynchronous mode or clocked synchronous mode 0 1 asynchronous mode clocked synchronous mode stop bit length 0 1 1 stop bit 2 stop bits 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock
810 smr0?serial mode register 0 h'ff78 smart card interface 0 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 bcp1 0 r/w 0 cks0 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w bit initial value r/w : : : clock select parity mode 0 1 even parity odd parity parity enable 0 1 setting prohibited parity bit addition and checking enabled block transfer mode 0 1 normal smart card interface mode operation block transfer mode operation gsm mode 0 1 note: etu: elementary time unit (time for transfer of 1 bit) normal smart card interface mode operation tend flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit clock output on/off control only gsm mode smart card interface mode operation tend flag generation 11.0 etu after beginning of start bit high/low fixing control possible in addition to clock output on/off control (set by scr) 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock base clock pulse 0 1 0 1 0 1 32 clocks 64 clocks 372 clocks 256 clocks
811 brr0?bit rate register 0 h'ff79 sci0, smart card interface 0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w note: for details, see section 13.2.8, bit rate re g ister ( brr ) : : : sets the serial transfer bit rate
812 scr0?serial control register 0 h'ff7a sci0 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : transmit end interrupt enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit enable 0 1 transmission disabled transmission enabled receive enable 0 1 reception disabled reception enabled receive interrupt enable transmit interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled 0 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled multiprocessor interrupt enable 0 1 multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when mpb= 1 data is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and settingof the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. clock enable 0 1 0 1 0 1 asynchronous mode internal clock/sck pin functions as i/o port clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode internal clock/sck pin functions as clock output * 1 clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input notes: 1. 2. outputs a clock of the same frequency as the bit rate. inputs a clock with a frequency 16 times the bit rate.
813 scr0?serial control register 0 h'ff7a smart card interface 0 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : transmit end interrupt enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit enable 0 1 transmission disabled transmission enabled receive enable 0 1 reception disabled reception enabled receive interrupt enable transmit interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled 0 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled multiprocessor interrupt enable 0 1 multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when mpb= 1 data is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and settingof the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. clock enable operates as port i/o pin outputs clock as sck output pin operates as sck output pin, with output fixed low outputs clock as sck output pin operates as sck output pin, with output fixed high outputs clock as sck output pin smcr smif smr c/a, gm scr setting sck pin function see the sci cke1 cke0 0 1000 1001 1100 1101 1110 1111
814 tdr0?transmit data register 0 h'ff7b sci0, smart card interface 0 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : stores data for serial transmission
815 ssr0?serial status register 0 h'ff7c sci0 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : multiprocessor bit 0 1 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted overrun error receive data register full 0 1 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 transmit end 0 1 [clearing conditions] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?when the te bit in scr is 0 ?when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character parity error 0 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/e bit in smr framing error 0 1 [clearing condition] ?when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 0 1 [clearing conditions] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 1 note: onl y 0 can be written, to clear the fla g . [clearing conditions] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr
816 ssr0?serial status register 0 h'ff7c smart card interface 0 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : multiprocessor bit 0 1 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted overrun error receive data register full 0 1 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 transmit end 0 1 note: etu: elementary time unit (time for transfer of 1 bit) [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and write data to tdr [setting conditions] upon reset, and in standby mode or module stop mode when the te bit in scr is 0 and the ers bit is also 0 when tdre = 1 and ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 0 when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 when tdre = 1, 1.5 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 when tdre = 1, 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1 parity error 0 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/e bit in smr error signal status 0 1 note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its previous state. [clearing condition] ?upon reset, and in standby mode or module stop mode ?when 0 is written to ers after reading ers = 1 [setting condition] when the low level of the error signal is sampled 0 1 [clearing conditions] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 1 note: only 0 can be written, to clear the flag. [clearing conditions] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr
817 rdr0?receive data register 0 h'ff7d sci0, smart card interface 0 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : stores received serial data scmr0?mart card mode register 0 h'ff7e sci0, smart card interface 0 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 bit initial value r/w : : : specifies inversion of the data logic level tdr contents are transmitted as they are receive data is stored as it is in rdr tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr 0 1 smart card interface mode select selects the serial/parallel conversion format tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first tdr contents are transmitted msb-first receive data is stored in rdr msb-first 0 1 0 1 smart card interface function is disabled smart card interface function is enabled
818 smr1?serial mode register 1 h'ff80 sci1 7 c/a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value r/w : : : multiprocessor mode clock select 0 1 multiprocessor function disabled multiprocessor format selected parity mode 0 1 even parity odd parity parity enable 0 1 parity bit addition and checking disabled parity bit addition and checking enabled character length 0 1 note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. 8-bit data 7-bit data * selects asynchronous mode or clocked synchronous mode 0 1 asynchronous mode clocked synchronous mode stop bit length 0 1 1 stop bit 2 stop bits 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock
819 smr1?serial mode register 1 h'ff80 smart card interface 1 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 bcp1 0 r/w 0 cks0 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w bit initial value r/w : : : clock select parity mode 0 1 even parity odd parity parity enable 0 1 setting prohibited parity bit addition and checking enabled block transfer mode 0 1 normal smart card interface mode operation block transfer mode operation gsm mode 0 1 note: etu: elementary time unit (time for transfer of 1 bit) normal smart card interface mode operation tend flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit clock output on/off control only gsm mode smart card interface mode operation tend flag generation 11.0 etu after beginning of start bit high/low fixing control possible in addition to clock output on/off control (set by scr) 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock base clock pulse 0 1 0 1 0 1 32 clocks 64 clocks 372 clocks 256 clocks
820 brr1?bit rate register 1 h'ff81 sci1, smart card interface 1 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w note: for details, see section 13.2.8, bit rate re g ister ( brr ) : : : sets the serial transfer bit rate
821 scr1?serial control register 1 h'ff82 sci1 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : transmit end interrupt enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit enable 0 1 transmission disabled transmission enabled receive enable 0 1 reception disabled reception enabled receive interrupt enable transmit interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled 0 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled multiprocessor interrupt enable 0 1 multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when mpb= 1 data is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and settingof the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. clock enable 0 1 0 1 0 1 asynchronous mode internal clock/sck pin functions as i/o port clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode internal clock/sck pin functions as clock output * 1 clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input notes: 1. 2. outputs a clock of the same frequency as the bit rate. inputs a clock with a frequency 16 times the bit rate.
822 scr1?serial control register 1 h'ff82 smart card interface 1 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : transmit end interrupt enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit enable 0 1 transmission disabled transmission enabled receive enable 0 1 reception disabled reception enabled receive interrupt enable transmit interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled 0 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled multiprocessor interrupt enable 0 1 multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when mpb= 1 data is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and settingof the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. clock enable operates as port i/o pin outputs clock as sck output pin operates as sck output pin, with output fixed low outputs clock as sck output pin operates as sck output pin, with output fixed high outputs clock as sck output pin smcr smif smr c/a, gm scr setting sck pin function see the sci cke1 cke0 0 1000 1001 1100 1101 1110 1111
823 tdr1?transmit data register 1 h'ff83 sci1, smart card interface 1 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : stores data for serial transmission
824 ssr1?serial status register 1 h'ff84 sci1 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : multiprocessor bit 0 1 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted overrun error receive data register full 0 1 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 transmit end 0 1 [clearing conditions] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?when the te bit in scr is 0 ?when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character parity error 0 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/e bit in smr framing error 0 1 [clearing condition] ?when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 0 1 [clearing conditions] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 1 note: only 0 can be written, to clear the flag. [clearing conditions] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr
825 ssr1?serial status register 1 h'ff84 smart card interface 1 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : multiprocessor bit 0 1 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted overrun error receive data register full 0 1 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 transmit end 0 1 note: etu: elementary time unit (time for transfer of 1 bit) [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and write data to tdr [setting conditions] upon reset, and in standby mode or module stop mode when the te bit in scr is 0 and the ers bit is also 0 when tdre = 1 and ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 0 when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 when tdre = 1, 1.5 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 when tdre = 1, 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1 parity error 0 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/e bit in smr error signal status 0 1 note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its previous state. [clearing condition] ?upon reset, and in standby mode or module stop mode ?when 0 is written to ers after reading ers = 1 [setting condition] when the low level of the error signal is sampled 0 1 [clearing conditions] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 1 note: onl y 0 can be written, to clear the fla g . [clearing conditions] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr
826 rdr1?receive data register 1 h'ff85 sci1, smart card interface 1 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : stores received serial data scmr1?mart card mode register 1 h'ff86 sci1, smart card interface 1 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 bit initial value r/w : : : specifies inversion of the data logic level tdr contents are transmitted as they are receive data is stored as it is in rdr tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr 0 1 smart card interface mode select selects the serial/parallel conversion format tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first tdr contents are transmitted msb-first receive data is stored in rdr msb-first 0 1 0 1 smart card interface function is disabled smart card interface function is enabled
827 smr2?serial mode register 2 h'ff88 sci2 7 c/a 0 r/w 6 chr 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 stop 0 r/w 0 cks0 0 r/w 2 mp 0 r/w 1 cks1 0 r/w bit initial value r/w : : : multiprocessor mode clock select 0 1 multiprocessor function disabled multiprocessor format selected parity mode 0 1 even parity odd parity parity enable 0 1 parity bit addition and checking disabled parity bit addition and checking enabled character length 0 1 note: * when 7-bit data is selected, the msb (bit 7) of tdr is not transmitted. 8-bit data 7-bit data * selects asynchronous mode or clocked synchronous mode 0 1 asynchronous mode clocked synchronous mode stop bit length 0 1 1 stop bit 2 stop bits 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock
828 smr2?serial mode register 2 h'ff88 smart card interface 2 7 gm 0 r/w 6 blk 0 r/w 5 pe 0 r/w 4 o/e 0 r/w 3 bcp1 0 r/w 0 cks0 0 r/w 2 bcp0 0 r/w 1 cks1 0 r/w bit initial value r/w : : : clock select parity mode 0 1 even parity odd parity parity enable 0 1 setting prohibited parity bit addition and checking enabled block transfer mode 0 1 normal smart card interface mode operation block transfer mode operation gsm mode 0 1 note: etu: elementary time unit (time for transfer of 1 bit) normal smart card interface mode operation tend flag generation 12.5 etu (11.5 etu in block transfer mode) after beginning of start bit clock output on/off control only gsm mode smart card interface mode operation tend flag generation 11.0 etu after beginning of start bit high/low fixing control possible in addition to clock output on/off control (set by scr) 0 1 0 1 0 1 ?clock ?4 clock ?16 clock ?64 clock base clock pulse 0 1 0 1 0 1 32 clocks 64 clocks 372 clocks 256 clocks
829 brr2?bit rate register 2 h'ff89 sci2, smart card interface 2 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w note: for details, see section 13.2.8, bit rate re g ister ( brr ) : : : sets the serial transfer bit rate
830 scr2?serial control register 2 h'ff8a sci2 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : transmit end interrupt enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit enable 0 1 transmission disabled transmission enabled receive enable 0 1 reception disabled reception enabled receive interrupt enable transmit interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled 0 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled multiprocessor interrupt enable 0 1 multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when mpb= 1 data is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and settingof the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. clock enable 0 1 0 1 0 1 asynchronous mode internal clock/sck pin functions as i/o port clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode internal clock/sck pin functions as clock output * 1 clocked synchronous mode internal clock/sck pin functions as serial clock output asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input asynchronous mode external clock/sck pin functions as clock input * 2 clocked synchronous mode external clock/sck pin functions as serial clock input notes: 1. 2. outputs a clock of the same frequency as the bit rate. inputs a clock with a frequency 16 times the bit rate.
831 scr2?serial control register 2 h'ff8a smart card interface 2 7 tie 0 r/w 6 rie 0 r/w 5 te 0 r/w 4 re 0 r/w 3 mpie 0 r/w 0 cke0 0 r/w 2 teie 0 r/w 1 cke1 0 r/w bit initial value r/w : : : transmit end interrupt enable 0 1 transmit end interrupt (tei) request disabled transmit end interrupt (tei) request enabled transmit enable 0 1 transmission disabled transmission enabled receive enable 0 1 reception disabled reception enabled receive interrupt enable transmit interrupt enable 0 1 transmit data empty interrupt (txi) requests disabled transmit data empty interrupt (txi) requests enabled 0 1 receive data full interrupt (rxi) request and receive error interrupt (eri) request disabled receive data full interrupt (rxi) request and receive error interrupt (eri) request enabled multiprocessor interrupt enable 0 1 multiprocessor interrupts disabled [clearing conditions] ?when the mpie bit is cleared to 0 ?when mpb= 1 data is received multiprocessor interrupts enabled receive interrupt (rxi) requests, receive error interrupt (eri) requests, and settingof the rdrf, fer, and orer flags in ssr are disabled until data with the multiprocessor bit set to 1 is received. clock enable operates as port i/o pin outputs clock as sck output pin operates as sck output pin, with output fixed low outputs clock as sck output pin operates as sck output pin, with output fixed high outputs clock as sck output pin smcr smif smr c/a, gm scr setting sck pin function see the sci cke1 cke0 0 1000 1001 1100 1101 1110 1111
832 tdr2?transmit data register 2 h'ff8b sci2, smart card interface 2 7 1 r/w 6 1 r/w 5 1 r/w 4 1 r/w 3 1 r/w 0 1 r/w 2 1 r/w 1 1 r/w bit initial value r/w : : : stores data for serial transmission
833 ssr2?serial status register 2 h'ff8c sci2 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 fer 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : multiprocessor bit 0 1 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted overrun error receive data register full 0 1 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 transmit end 0 1 [clearing conditions] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?when the te bit in scr is 0 ?when tdre = 1 at transmission of the last bit of a 1-byte serial transmit character parity error 0 1 [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/e bit in smr framing error 0 1 [clearing condition] ?when 0 is written to fer after reading fer = 1 [setting condition] when the sci checks whether the stop bit at the end of the receive data when reception ends, and the stop bit is 0 0 1 [clearing conditions] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 1 note: onl y 0 can be written, to clear the fla g . [clearing conditions] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr
834 ssr2?serial status register 2 h'ff8c smart card interface 2 7 tdre 1 r/(w) * 6 rdrf 0 r/(w) * 5 orer 0 r/(w) * 4 ers 0 r/(w) * 3 per 0 r/(w) * 0 mpbt 0 r/w 2 tend 1 r 1 mpb 0 r bit initial value r/w : : : multiprocessor bit 0 1 [clearing condition] when data with a 0 multiprocessor bit is received [setting condition] when data with a 1 multiprocessor bit is received multiprocessor bit transfer 0 1 data with a 0 multiprocessor bit is transmitted data with a 1 multiprocessor bit is transmitted overrun error receive data register full 0 1 [clearing condition] when 0 is written to orer after reading orer = 1 [setting condition] when the next serial reception is completed while rdrf = 1 transmit end 0 1 [clearing conditions] when 0 is written to tdre after reading tdre = 1 when the dtc is activated by a txi interrupt and write data to tdr [setting conditions] upon reset, and in standby mode or module stop mode when the te bit in scr is 0 and the ers bit is also 0 when tdre = 1 and ers = 0 (normal transmission) 2.5 etu after transmission of a 1-byte serial character when gm = 0 and blk = 0 when tdre = 1 and ers = 0 (normal transmission) 1.0 etu after transmission of a 1-byte serial character when gm = 0 and blk = 1 when tdre = 1, 1.5 etu after transmission of a 1-byte serial character when gm = 1 and blk = 0 when tdre = 1, 1.0 etu after transmission of a 1-byte serial character when gm = 1 and blk = 1 parity error 0 1 note: etu: elementary time unit (time for transfer of 1 bit) [clearing condition] when 0 is written to per after reading per = 1 [setting condition] when, in reception, the number of 1 bits in the receive data plus the parity bit does not match the parity setting (even or odd) specified by the o/e bit in smr error signal status 0 1 note: clearing the te bit in scr to 0 does not affect the ers flag, which retains its previous state. [clearing condition] ?upon reset, and in standby mode or module stop mode ?when 0 is written to ers after reading ers = 1 [setting condition] when the low level of the error signal is sampled 0 1 [clearing conditions] ?when 0 is written to rdrf after reading rdrf = 1 ?when the dtc is activated by an rxi interrupt and reads data from rdr [setting condition] when serial reception ends normally and receive data is transferred from rsr to rdr transmit data register empty 0 1 note: onl y 0 can be written, to clear the fla g . [clearing conditions] ?when 0 is written to tdre after reading tdre = 1 ?when the dtc is activated by a txi interrupt and writes data to tdr [setting conditions] ?when the te bit in scr is 0 ?when data is transferred from tdr to tsr and data can be written to tdr
835 rdr2?receive data register 2 h'ff8d sci2, smart card interface 2 7 0 r 6 0 r 5 0 r 4 0 r 3 0 r 0 0 r 2 0 r 1 0 r bit initial value r/w : : : stores received serial data scmr2?mart card mode register 2 h'ff8e sci2, smart card interface 2 7 1 6 1 5 1 4 1 3 sdir 0 r/w 0 smif 0 r/w 2 sinv 0 r/w 1 1 bit initial value r/w : : : specifies inversion of the data logic level tdr contents are transmitted as they are receive data is stored as it is in rdr tdr contents are inverted before being transmitted receive data is stored in inverted form in rdr 0 1 smart card interface mode select selects the serial/parallel conversion format tdr contents are transmitted lsb-first receive data is stored in rdr lsb-first tdr contents are transmitted msb-first receive data is stored in rdr msb-first 0 1 0 1 smart card interface function is disabled smart card interface function is enabled
836 addrah ?a/d data register ah addral ?a/d data register al addrbh ?a/d data register bh addrbl ?a/d data register bl addrch ?a/d data register ch addrcl ?a/d data register cl addrdh ?a/d data register dh addrdl ?a/d data register dl h'ff90 h'ff91 h'ff92 h'ff93 h'ff94 h'ff95 h'ff96 h'ff97 a/d converter 15 ad9 0 r bit initial value r/w : : : 14 ad8 0 r 13 ad7 0 r 12 ad6 0 r 11 ad5 0 r 10 ad4 0 r 9 ad3 0 r 8 ad2 0 r 7 ad1 0 r 6 ad0 0 r 5 0 r 4 0 r 3 0 r 2 0 r 1 0 r 0 0 r store the results of a/d conversion analog input channel group 0 an0 an1 an2 an3 a/d data register addra addrb addrc addrd group 1 an4 an5 an6 an7
837 adcsr?a/d control/status register h'ff98 a/d 7 adf 0 r/(w) * 6 adie 0 r/w 5 adst 0 r/w 4 scan 0 r/w 3 0 r/w 0 ch0 0 r/w 2 ch2 0 r/w 1 ch1 0 r/w bit initial value r/w : : : note: * onl y 0 can be written, to clear this fla g . scan mode 0 1 single mode scan mode a/d interrupt enable 0 1 a/d conversion end interrupt (adi) request disabled a/d conversion end interrupt (adi) request enabled a/d end flag 0 1 [clearing conditions] ?when 0 is written to the adf flag after reading adf = 1 ?when the dtc is activated by an adi interrupt and addr is read [setting conditions] ?single mode: when a/d conversion ends ?scan mode: when a/d conversion ends on all specified channels a/d start 0 1 ?a/d conversion stopped ?single mode: a/d conversion is started. cleared to 0 automatically when conversion on the specified channel ends ?scan mode: a/d conversion is started. conversion continues sequentially on the selected channels until adst is cleared to 0 by software, a reset, or a transition to standby mode or module stop mode. channel select reserved only 0 should be written to this bit group selection ch2 0 1 ch1 0 1 0 1 ch0 0 1 0 1 0 1 0 1 single mode an0 (initial value) an0 an1 an0, an1 an2 an0 to an2 an3 an0 to an3 an4 an4 an5 an4, an5 an6 an4 to an6 an7 an4 to an7 scan mode description channel selection
838 adcr?a/d control register h'ff99 a/d 7 trgs1 0 r/w 6 trgs0 0 r/w 5 1 4 1 3 cks1 0 r/w 0 1 r/w 2 cks0 0 r/w 1 1 bit initial value r/w : : : clock select cks1 0 1 cks0 0 1 0 1 description conversion time = 530 states (max.) conversion time = 260 states (max.) conversion time = 134 states (max.) conversion time = 68 states (max.) timer trigger select 0 1 0 1 0 1 a/d conversion start by software is enabled a/d conversion start by tpu conversion start trigger is enabled a/d conversion start by 8-bit timer conversion start trigger is enabled a/d conversion start by external trigger pin (adtrg) is enabled
839 tcsr1?timer control/status register 1 h'ffa2 wdt1 7 ovf 0 r/(w) * 1 6 wt/it 0 r/w 5 tme 0 r/w 4 pss 0 r/w 3 rst/nmi 0 r/w 0 cks0 0 r/w 2 cks2 0 r/w 1 cks1 0 r/w bit initial value read/write note: 1. only 0 can be written to clear the flag. tcsr is write-protected by a password to prevent accidental overwriting. for details see section 12.2.5, notes on re g ister access. power-on reset or nmi 0 1 an nmi interrupt is requested a power-on reset is requested timer enable 0 1 tcnt is initialized to h'00 and count operation is halted tcnt counts timer mode select 0 1 interval timer mode: interval timer interrupt (wovi) request is sent to cpu when tcnt overflows watchdog timer mode: power-on reset or nmi interrupt request is sent to cpu when tcnt overflows overflow flag 0 1 [clearing conditions] ?write 0 in the tme bit ?read tcsr when ovf = 1, then write 0 in ovf [setting condition] when tcnt overflows (changes from h'ff to h'00) when internal reset request generation is selected in watchdog timer mode, ovf is cleared automatically by the interval reset. prescaler select 0 1 tcnt counts ?based prescaler (psm) divided clock pulses tcnt counts ?ub-based prescaler (pss) divided clock pulses clock select 0 0 0 0 ?2 (initial value) 51.2 s 1 ?64 1.6 ms 1 0 ?128 3.2 ms 1 ?512 13.2 ms 1 0 0 ?2048 52.4 ms 1 ?8192 209.8 ms 1 0 ?32768 838.8 ms 1 ?131072 3.36 s 1 0 0 0 ?ub/2 15.6 ms 1 ?ub/4 31.3 ms 1 0 ?ub/8 62.5 ms 1 ?ub/16 125 ms 1 0 0 ?ub/32 250 ms 1 ?ub/64 500 ms 1 0 ?ub/128 1 s 1 ?ub/256 2 s pss note: 2. the overflow period is the time from when tcnt starts counting up from h'00 until overflow occurs. cks2 cks1 cks0 clock overflow period * 2 (when ?= 10 mhz and ?ub = 32.768 khz)
840 tcnt1?timer counter 1 h'ffa2 (write) h'ffa3 (read) wdt1 7 0 r/w 6 0 r/w 5 0 r/w 4 0 r/w 3 0 r/w 0 0 r/w 2 0 r/w 1 0 r/w bit initial value r/w : : : port1?ort 1 register h'ffb0 port 1 7 p17 * r 6 p16 * r 5 p15 * r 4 p14 * r 3 p13 * r 0 p10 * r 2 p12 * r 1 p11 * r bit initial value read/write note: * determined by the state of pins p17 to p10. state of port 1 pins port3?ort 3 register h'ffb2 port 3 7 undefined 6 p36 * r 5 p35 * r 4 p34 * r 3 p33 * r 0 p30 * r 2 p32 * r 1 p31 * r bit initial value read/write note: * determined by the state of pins p35 to p30. state of port 3 pins port4?ort 4 register h'ffb3 port 4 7 p47 * r 6 p46 * r 5 p45 * r 4 p44 * r 3 p43 * r 0 p40 * r 2 p42 * r 1 p41 * r bit initial value read/write note: * determined by the state of pins p47 to p40. state of port 4 pins
841 port7?port 7 register h'ffb6 port 7 7 p77 * r 6 p76 * r 5 p75 * r 4 p74 * r 3 p73 * r 0 p70 * r 2 p72 * r 1 p71 * r bit initial value read/write note: * determined by the state of pins p77 to p70. state of port 7 pins port9?ort 9 register h'ffb8 port 9 7 p97 * r 6 p96 * r 5 r 4 r 3 r 0 r 2 r 1 r bit initial value read/write note: * determined by the state of pins p97 and p96. state of port 9 pins porta?ort a register h'ffb9 port a 7 undefined 6 undefined 5 undefined 4 undefined 3 pa3 * r 0 pa0 * r 2 pa2 * r 1 pa1 * r bit initial value read/write note: * determined by the state of pins pa3 to pa0. state of port a pins
842 portb?port b register h'ffba port b 7 pb7 * r 6 pb6 * r 5 pb5 * r 4 pb4 * r 3 pb3 * r 0 pb0 * r 2 pb2 * r 1 pb1 * r bit initial value read/write note: * determined by the state of pins pb7 to pb0. state of port b pins portc?ort c register h'ffbb port c 7 pc7 * r 6 pc6 * r 5 pc5 * r 4 pc4 * r 3 pc3 * r 0 pc0 * r 2 pc2 * r 1 pc1 * r bit initial value read/write note: * determined by the state of pins pc7 to pc0. state of port c pins portd?ort d register h'ffbc port d 7 pd7 * r 6 pd6 * r 5 pd5 * r 4 pd4 * r 3 pd3 * r 0 pd0 * r 2 pd2 * r 1 pd1 * r bit initial value read/write note: * determined by the state of pins pd7 to pd0. state of port d pins
843 porte?port e register h'ffbd port e 7 pe7 * r 6 pe6 * r 5 pe5 * r 4 pe4 * r 3 pe3 * r 0 pe0 * r 2 pe2 * r 1 pe1 * r bit initial value read/write note: * determined by the state of pins pe7 to pe0. state of port e pins portf?ort f register h'ffbe port f 7 pf7 * r 6 pf6 * r 5 pf5 * r 4 pf4 * r 3 pf3 * r 0 pf0 * r 2 pf2 * r 1 pf1 * r bit initial value read/write note: * determined by the state of pins pf7 to pf0. state of port f pins portg?ort g register h'ffbf port g 7 undefined 6 undefined 5 undefined 4 pg4 * r 3 pg3 * r 0 pg0 * r 2 pg2 * r 1 pg1 * r bit initial value read/write note: * determined by the state of pins pg4 to pg0. state of port g pins
844 appendix c i/o port block diagrams c.1 port 1 block diagrams r p1nddr c qd reset internal data bus internal address bus wddr1 reset wdr1 r p1ndr modes 4 to 6 c qd p1n * rdr1 rpor1 bus controller tpu module address output enable output compare output/ pwm output enable output compare output/ pwm output input capture input wddr1 wdr1 rdr1 rpor1 n = 0 or 1 note: * priority order: output compare/pwm output > dr output : write to p1ddr : write to p1dr : read p1dr : read port 1 legend figure c-1 (a) port 1 block diagram (pins p10 and p11)
845 r p1nddr c qd reset internal data bus internal address bus wddr1 reset wdr1 r p1ndr modes 4 to 6 c qd p1n * rdr1 rpor1 bus controller address output enable tpu module output compare output/ pwm output enable output compare output/ pwm output external clock input input capture input wddr1 wdr1 rdr1 rpor1 n = 2 or 3 note: * priority order: output compare/pwm output > dr output : write to p1ddr : write to p1dr : read p1dr : read port 1 legend figure c-1 (b) port 1 block diagram (pins p12 and p13)
846 r p1nddr c qd reset internal data bus wddr1 reset wdr1 r p1ndr c qd p1n rdr1 rpor1 tpu module interrupt controller output compare output/ pwm output enable output compare output/ pwm output irq interrupt input input capture input * wddr1 wdr1 rdr1 rpor1 n = 4 or 6 note: * priority order: output compare/pwm output > dr output : write to p1ddr : write to p1dr : read p1dr : read port 1 legend figure c-1 (c) port 1 block diagram (pins p14 and p16)
847 r p1nddr c qd reset internal data bus wddr1 reset wdr1 r p1ndr c qd p1n rdr1 rpor1 tpu module output compare output/ pwm output enable output compare output/ pwm output external clock input input capture input * wddr1 wdr1 rdr1 rpor1 n = 5 or 7 note: * priority order: output compare/pwm output > dr output : write to p1ddr : write to p1dr : read p1dr : read port 1 legend figure c-1 (d) port 1 block diagram (pins p15 and p17)
848 c.2 port 3 block diagrams r p3nddr c qd reset internal data bus wddr3 reset wdr3 r c qd p3n rdr3 rodr3 rpor3 sci module serial transmit enable serial transmit data p3ndr reset wodr3 r c qd p3nodr output enable signal open-drain control signal * wddr3 wdr3 wodr3 rdr3 rpor3 rodr3 n = 0 or 3 note: * priority order: serial transmit data output > dr output : write to p3ddr : write to p3dr : write to p3odr : read p3dr : read port 3 : read p3odr legend figure c-2 (a) port 3 block diagram (pins p30 and p33)
849 r p3nddr c qd reset internal data bus wddr3 reset wdr3 r c qd p3n rdr3 rodr3 rpor3 sci module serial receive data enable serial receive data p3ndr reset wodr3 r c qd p3nodr output enable signal open-drain control signal * wddr3 wdr3 wodr3 rdr3 rpor3 rodr3 n = 1 or 4 note: * priority order: serial receive data input > dr output : write to p3ddr : write to p3dr : write to p3odr : read p3dr : read port 3 : read p3odr legend figure c-2 (b) port 3 block diagram (pins p31 and p34)
850 r p3nddr c qd reset internal data bus wddr3 reset wdr3 r c qd p3n rdr3 rodr3 rpor3 sci module serial clock output enable serial clock output serial clock input enable p3ndr reset wodr3 r c qd p3nodr * serial clock input interrupt controller irq interrupt input output enable signal open-drain control signal wddr3 wdr3 wodr3 rdr3 rpor3 rodr3 n = 2 or 5 note: * priority order: serial clock input > serial clock output > dr output : write to p3ddr : write to p3dr : write to p3odr : read p3dr : read port 3 : read p3odr legend figure c-2 (c) port 3 block diagram (pins p32 and p35)
851 r p36ddr c qd reset internal data bus wddr3 reset wdr3 r c qd p36 rdr3 rodr3 rpor3 p36dr reset wodr3 r c qd p36odr legend output enable signal open-drain control signal wddr3 wdr3 wodr3 rdr3 rpor3 rodr3 : write to p3ddr : write to p3dr : write to p3odr : read p3dr : read port 3 : read p3odr figure c-2 (d) port 3 block diagram (pin p36)
852 c.3 port 4 block diagram p4n rpor4 a/d converter module internal data bus analog input rpor4 n= 0 to 7 : read port legend figure c-3 port 4 block diagram (pins p40 to p47)
853 c.4 port 7 block diagrams r p70ddr c qd reset wddr7 internal data bus mode 7 modes 4 to 6 reset wdr7 r p70dr c qd p70 rdr7 rpor7 bus controller chip select 8-bit timer module counter external clock input counter external reset input wddr7 wdr7 rdr7 rpor7 : write to p7ddr : write to p7dr : read p7dr : read port 7 legend figure c-4 (a) port 7 block diagram (pin p70)
854 r p71ddr c qd reset internal data bus wddr7 mode 7 modes 4 to 6 reset wdr7 r p71dr c qd p71 rdr7 rpor7 bus controller chip select wddr7 wdr7 rdr7 rpor7 : write to p7ddr : write to p7dr : read p7dr : read port 7 legend figure c-4 (b) port 7 block diagram (pin p71)
855 r p7nddr c qd reset internal data bus wddr7 mode 7 reset wdr7 r p7ndr c qd p7n rdr7 rpor7 8-bit timer module bus controller chip select compare match output enable compare match output * modes 4 to 6 wddr7 wdr7 rdr7 rpor7 n = 2 or 3 note: * priority order: compare match output > dr output : write to p7ddr : write to p7dr : read p7dr : read port 7 legend figure c-4 (c) port 7 block diagram (pins p72 and p73)
856 r p74ddr c qd reset internal data bus wddr7 reset wdr7 r p74dr c qd p74 rdr7 rpor7 manual reset input wddr7 wdr7 rdr7 rpor7 : write to p7ddr : write to p7dr : read p7dr : read port 7 legend figure c-4 (d) port 7 block diagram (pin p74)
857 r p75ddr c qd reset output enable signal internal data bus wddr7 reset wdr7 r p75dr c qd p75 rdr7 rpor7 sci module serial clock output enable serial clock input enable serial clock output serial clock input * wddr7 wdr7 rdr7 rpor7 note: * priority order: serial clock input > serial clock output > dr output : write to p7ddr : write to p7dr : read p7dr : read port 7 legend figure c-4 (e) port 7 block diagram (pin p75)
858 r p76ddr c qd reset internal data bus wddr7 reset wdr7 r p76dr c qd p76 rdr7 rpor7 sci module serial receive data enable serial receive data output enable signal * wddr7 wdr7 rdr7 rpor7 note: * priority order: serial receive data input > dr output : write to p7ddr : write to p7dr : read p7dr : read port 7 legend figure c-4 (f) port 7 block diagram (pin p76)
859 r p77ddr c qd reset internal data bus wddr7 reset wdr7 r p77dr c qd p77 rdr7 rpor7 sci module serial transmit enable serial transmit data * wddr7 wdr7 rdr7 rpor7 note: * priority order: serial transmit data output > dr output : write to p7ddr : write to p7dr : read p7dr : read port 7 legend figure c-4 (g) port 7 block diagram (pin p77)
860 c.5 port 9 block diagram p9n rpor9 d/a converter module internal data bus h8s/2237 series only output enable analog output rpor9 n= 6 or 7 : read port 9 legend figure c-5 port 9 block diagram (pins p96 and p97)
861 c.6 port a block diagrams r pa0pcr c qd reset internal data bus internal address bus wpcra reset wdra r c qd pa0 rdra rodra rpora pa0dr reset wddra r c qd pa0ddr reset wodra rpcra r c qd pa0odr output enable signal modes 4 to 6 open-drain control signal * wddra wdra wodra wpcra : write to paddr : write to padr : write to paodr : write to papcr rdra rpora rodra rpcra : read padr : read port a : read paodr : read papcr legend note: * priority order: address output > dr output bus controller address output enable figure c-6 (a) port a block diagram (pin pa0)
862 r pa1pcr c qd reset internal data bus internal address bus wpcra reset wdra r c qd pa1 rdra rodra rpora pa1dr reset wddra r c qd pa1ddr reset wodra rpcra r c qd pa1odr * output enable signal open-drain control signal modes 4 to 6 wddra wdra wodra wpcra rdra rpora rodra rpcra note: * priority order: address output > serial transmit data > dr output : write to paddr : write to padr : write to paodr : write to papcr : read padr : read port a : read paodr : read papcr legend bus controller address output enable sci module serial transmit enable serial transmit data figure c-6 (b) port a block diagram (pin pa1)
863 r pa2pcr c qd reset internal data bus internal address bus wpcra reset wdra r c qd pa2 rdra rodra rpora pa2dr reset wddra r c qd pa2ddr reset wodra rpcra r c qd pa2odr * output enable signal open-drain control signal modes 4 to 6 wddra wdra wodra wpcra rdra rpora rodra rpcra : write to paddr : write to padr : write to paodr : write to papcr : read padr : read port a : read paodr : read papcr legend bus controller address output enable sci module serial receive data enable serial receive data note: * priority order: address output > serial receive data input > dr output figure c-6 (c) port a block diagram (pin pa2)
864 r pa3pcr c qd reset internal data bus internal address bus wpcra reset wdra r c qd pa3 rdra rodra rpora pa3dr reset wddra r c qd pa3ddr reset wodra rpcra r c qd pa3odr * output enable signal open-drain control signal modes 4 to 6 wddra wdra wodra wpcra rdra rpora rodra rpcra note: * priority order: address output > serial clock input > serial clock output > dr output : write to paddr : write to padr : write to paodr : write to papcr : read padr : read port a : read paodr : read papcr legend bus controller address output enable sci module serial clock output enable serial clock input enable serial clock input serial clock output figure c-6 (d) port a block diagram (pin pa3)
865 c.7 port b block diagram r pbnpcr c qd reset internal data bus internal address bus wpcrb reset wdrb r c qd pbn rdrb rporb pbndr reset wddrb r c qd pbnddr rpcrb * output enable signal modes 4 to 6 wddrb wdrb wpcrb rdrb rporb rpcrb n = 0 to 7 note: * priority order: address output > output compare/pwm output > dr output : write to pbddr : write to pbdr : write to pbpcr : read pbdr : read port b : read pbpcr legend bus controller address output enable tpu module output compare output/ pwm output enable output compare output/ pwm output input capture input figure c-7 port b block diagram (pins pb0 to pb7)
866 c.8 port c block diagram r pcnpcr c qd reset internal data bus internal address bus wpcrc reset wdrc r c qd pcn rdrc rporc pcndr reset wddrc r modes 4 and 5 * s c qd pcnddr rpcrc output enable signal mode 7 modes 4 to 6 wddrc wdrc wpcrc rdrc rporc rpcrc n = 0 to 7 : write to pcddr : write to pcdr : write to pcpcr : read pcdr : read port c : read pcpcr legend note: * set priority figure c-8 port c block diagram (pins pc0 to pc7)
867 c.9 port d block diagram reset r pdnpcr c qd reset internal upper data bus internal lower data bus wpcrd reset wdrd r c qd pdn rdrd external address upper write external address lower write rpord pdndr wddrd c qd pdnddr rpcrd mode 7 modes 4 to 6 external address write r external address upper read external address lower read legend wddrd wdrd wpcrd rdrd rpord rpcrd n = 0 to 7 : write to pdddr : write to pddr : write to pdpcr : read pddr : read port d : read pdpcr figure c-9 port d block diagram (pins pd0 to pd7)
868 c.10 port e block diagram reset r penpcr c qd reset internal upper data bus internal lower data bus wpcre reset wdre r c qd pen rdre rpore pendr wddre c qd penddr rpcre mode 7 modes 4 to 6 external address write r external address lower read legend wddre wdre wpcre rdre rpore rpcre n = 0 to 7 : write to peddr : write to pedr : write to pepcr : read pedr : read port e : read pepcr 8-bit bus mode figure c-10 port e block diagram (pins pe0 to pe7)
869 c.11 port f block diagrams r pf0ddr c qd reset internal data bus wddrf reset wdrf r c qd pf0 rdrf rporf bus request input interrupt controller irq interrupt input pf0dr bus controller brle output modes 4 to 6 legend wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f figure c-11 (a) port f block diagram (pin pf0)
870 r pf1ddr c qd reset internal data bus wddrf reset wdrf r c qd pf1 rdrf rporf wdt1 module buzz output enable buzz output pf1dr bus controller brle output bus request acknowledge output modes 4 to 6 legend wddrf wdrf rdrf rporf note: * priority order: bus request acknowledge output > buzz output > dr output : write to pfddr : write to pfdr : read pfdr : read port f * figure c-11 (b) port f block diagram (pin pf1)
871 r pf2ddr c qd reset internal data bus wddrf reset wdrf r c qd pf2 rdrf rporf wait input pf2dr bus controller wait enable modes 4 to 6 legend wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f figure c-11 (c) port f block diagram (pin pf2)
872 r pf3ddr c qd reset internal data bus wddrf reset wdrf r c qd pf3 rdrf rporf irq interrupt input a/d converter adtrg input pf3dr interrupt controller lwr output 16 bit bus mode bus controller modes 4 to 6 legend wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f figure c-11 (d) port f block diagram (pin pf3)
873 r pfnddr c qd reset internal data bus wddrf reset wdrf r c qd pfn rdrf rporf pfndr modes 4 to 6 mode 7 pf4: hwr output pf5: rd output pf6: as output bus controller modes 4 to 6 legend wddrf wdrf rdrf rporf n = 4 to 6 : write to pfddr : write to pfdr : read pfdr : read port f figure c-11 (e) port f block diagram (pins pf4 to pf6)
874 r s pf7ddr c qd reset internal data bus modes 4 to 6 * wddrf reset wdrf r c qd pf7 rdrf rporf pf7dr legend wddrf wdrf rdrf rporf : write to pfddr : write to pfdr : read pfdr : read port f note: * set priority figure c-11 (f) port f block diagram (pin pf7)
875 c.12 port g block diagrams r pg0ddr c qd reset internal data bus wddrg reset wdrg r c qd pg0 rdrg rporg irq interrupt input pg0dr interrupt controller legend wddrg wdrg rdrg rporg : write to pgddr : write to pgdr : read pgdr : read port g figure c-12 (a) port g block diagram (pin pg0)
876 r pg1ddr c qd reset internal data bus wddrg reset wdrg r c qd pg1 rdrg rporg irq interrupt input pg1dr interrupt controller legend wddrg wdrg rdrg rporg : write to pgddr : write to pgdr : read pgdr : read port g mode 7 chip select bus controller modes 4 to 6 figure c-12 (b) port g block diagram (pin pg1)
877 r pgnddr c qd wddrg reset reset internal data bus wdrg r c qd pgn rdrg rporg pgndr legend wddrg wdrg rdrg rporg n = 2 or 3 : write to pgddr : write to pgdr : read pgdr : read port g mode 7 chip select bus controller modes 4 to 6 figure c-12 (c) port g block diagram (pins pg2 and pg3)
878 r s pg4ddr c qd wddrg reset reset internal data bus modes 4 and 5 modes 6 and 7 wdrg r c qd pg4 rdrg rporg pg4dr legend wddrg wdrg rdrg rporg : write to pgddr : write to pgdr : read pgdr : read port g mode 7 chip select bus controller modes 4 to 6 figure c-12 (d) port g block diagram (pin pg4)
879 appendix d pin states d.1 port states in each processing state table d-1 i/o port states in each processing state port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode, watch mode bus- released state program execution state, sleep mode, subsleep mode p17 to p14 4 to 7 t keep t keep keep i/o port p13/tiocd0/tclkb/a23 p12/tiocc0/tclka/a22 p11/tiocb0/a21 7 t keep t keep keep i/o port address output selected by aen bit 4 to 6 t keep t [ope= 0] t [ope= 1] keep t address output port selected 4 to 6 t keep t keep keep i/o port p10/tioca0/a20 7 t keep t keep keep i/o port address output selected by aen bit 4, 5 6 l t keep t [ope= 0] t [ope= 1] keep t address output port selected 4 to 6 t * keep t keep keep i/o port port 3 4 to 7 t keep t keep keep i/o port port 4 4 to 7 t t t t t input port p77 to p74 4 to 7 t keep t keep keep i/o port p73/tmo1/ cs7 p72/tmo0/ cs6 p71/ cs5 p70/tmri01/tmci01/ cs4 7 4 to 6 t t keep keep t t keep [ddr?pe= 0] t [ddr?pe= 1] h keep t i/o port [ddr = 0] input port [ddr = 1] cs7 to cs4 p97/da1 p96/da0 4 to 7 t t t [daoen= 1] keep [daoen= 0] t keep input port port a 7 t keep t keep keep i/o port address output selected by aen bit 4, 5 6 l t keep t [ope= 0] t [ope= 1] keep t address output port selected 4 to 6 t * keep t keep keep i/o port
880 table d-1 i/o port states in each processing state (cont) port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode, watch mode bus- released state program execution state, sleep mode, subsleep mode port b 7 t keep t keep keep i/o port address output selected by aen bit 4, 5 6 l t keep t [ope= 0] t [ope= 1] keep t address output port selected 4 to 6 t * keep t keep keep i/o port port c 4, 5 l keep t [ope= 0] t [ope= 1] keep t address output 6 t keep t [ddr?pe= 0] t [ddr?pe= 1] keep t [ddr = 0] input port [ddr = 1] address output 7 t keep t keep keep i/o port port d 4 to 6 t t t t t data bus 7 t keep t keep keep i/o port port e 8-bit bus 4 to 6 t keep t keep keep i/o port 16-bit bus 4 to 6 t t t t t data bus 7 t keep t keep keep i/o port pf7/ 4 to 6 clock output [[ddr = 0] input port [ddr = 1] clock output t [ddr= 0] input port [ddr= 1] h [ddr= 0] input port [ddr= 1] clock output [ddr= 0] input port [ddr= 1] clock output 7 t keep t [ddr= 0] input port [ddr= 1] h [ddr= 0] input port [ddr= 1] clock output [ddr= 0] input port [ddr= 1] clock output pf6/ as , pf5/ rd , pf4/ hwr 4 to 6 h h t [ope= 0] t [ope= 1] h t as , rd , hwr 7 t keep t keep keep i/o port pf3/ lwr / adtrg / irq3 7 t keep t keep keep i/o port 8-bit bus 16-bit bus 4 to 6 4 to 6 (mode 4) h (modes 5 and 6) t keep h t t keep [ope= 0] t [ope= 1] h keep t i/o port lwr
881 table d-1 i/o port states in each processing state (cont) port name pin name mcu operating mode power- on reset manual reset hardware standby mode software standby mode, watch mode bus- released state program execution state, sleep mode, subsleep mode pf2/ wait 4 to 6 t keep t [waite= 0] keep [waite= 1] t [waite= 0] keep [waite= 1] t [waite= 0] i/o port [waite= 1] wait 7 t keep t keep keep i/o port pf1/ back /buzz 4 to 6 t keep t [brle= 0] keep [brle= 1] h l [brle= 0] i/o port [brle= 1] back 7 t keep t keep keep i/o port pf0/ breq / ireq2 4 to 6 t keep t [brle= 0] keep [brle= 1] t t [brle= 0] i/o port [brle= 1] breq 7 t keep t keep keep i/o port pg4/ cs0 4, 5 6 h t keep t [ddr?pe= 0] t [ddr?pe= 1] h t [ddr = 0] input port [ddr = 1] cs0 (in sleep mode and subsleep mode: h) 7 t keep t keep keep i/o port pg3/ cs1 pg2/ cs2 pg1/ cs3 / irq7 4 to 6 t keep t [ddr?pe= 0] t [ddr?pe= 1] h t [ddr= 0] input port [ddr= 1] cs1 to cs3 7 t keep t keep keep i/o port pg0/ irq6 4 to 7 t keep t keep keep i/o port legend: h: high level l: low level t: high impedance keep: input port becomes high-impedance, output port retains state ddr data direction register ope: output port enable waite: wait input enable brle: bus release enable note: * l in modes 4 and 5 (address output)
882 appendix e timing of transition to and recovery from hardware standby mode timing of transition to hardware standby mode (1) to retain ram contents with the rame bit set to 1 in syscr, drive the res signal low at least 10 states before the stby signal goes low, as shown below. res must remain low until stby signal goes low (delay from stby low to res high: 0 ns or more). stby res t 2 0ns t 1 10t cyc figure e-1 timing of transition to hardware standby mode (2) to retain ram contents with the rame bit cleared to 0 in syscr, or when ram contents do not need to be retained, res does not have to be driven low as in (1). timing of recovery from hardware standby mode drive the res signal low and the nmi signal high approximately 100 ns or more before stby goes high to execute a power-on reset. stby res t osc t 100ns figure e-2 timing of recovery from hardware standby mode
883 appendix f product code lineup table f-1 h8s/2237 series and h8s/2227 series product code lineup product type product code mark code package h8s/2237 mask rom version hd6432237 hd6432237( *** )te 100-pin tqfp (tfp-100b) hd6432237( *** )tf 100-pin tqfp (tfp-100g) hd6432237( *** )f 100-pin qfp (fp-100a) hd6432237( *** )fa 100-pin qfp (fp-100b) ztat version hd6472237 hd6472237te10 100-pin tqfp (tfp-100b) hd6472237tf10 100-pin tqfp (tfp-100g) hd6472237f10 100-pin qfp (fp-100a) hd6472237fa10 100-pin qfp (fp-100b) h8s/2235 mask rom version hd6432235 hd6432235( *** )te 100-pin tqfp (tfp-100b) hd6432235( *** )tf 100-pin tqfp (tfp-100g) hd6432235( *** )f 100-pin qfp (fp-100a) hd6432235( *** )fa 100-pin qfp (fp-100b) h8s/2233 mask rom version hd6432233 hd6432233( *** )te 100-pin tqfp (tfp-100b) hd6432233( *** )tf 100-pin tqfp (tfp-100g) hd6432233( *** )f 100-pin qfp (fp-100a) hd6432233( *** )fa 100-pin qfp (fp-100b) h8s/2227 mask rom version hd6432227 hd6432227( *** )te 100-pin tqfp (tfp-100b) hd6432227( *** )tf 100-pin tqfp (tfp-100g) hd6432227( *** )f 100-pin qfp (fp-100a) hd6432227( *** )fa 100-pin qfp (fp-100b) h8s/2225 mask rom version hd6432225 hd6432225( *** )te 100-pin tqfp (tfp-100b) hd6432225( *** )tf 100-pin tqfp (tfp-100g) hd6432225( *** )f 100-pin qfp (fp-100a) hd6432225( *** )fa 100-pin qfp (fp-100b) h8s/2223 mask rom version hd6432223 hd6432223( *** )te 100-pin tqfp (tfp-100b) hd6432223( *** )tf 100-pin tqfp (tfp-100g) hd6432223( *** )f 100-pin qfp (fp-100a) hd6432223( *** )fa 100-pin qfp (fp-100b) note: ( *** ) is the rom code.
884 appendix g package dimensions figures g-1 to g-4 show the h8s/2237 series and h8s/2227 series package dimensions. 16.0 0.2 14 0.08 0.10 0.5 0.1 16.0 0.2 0.5 0.10 0.10 1.20 max *0.17 0.05 0 ?8 75 51 125 76 100 26 50 m *0.22 0.05 1.0 1.00 1.0 0.20 0.04 0.15 0.04 unit: mm *dimension including the plating thickness base material dimension figure g-1 tfp-100b package dimensions
885 14.0 0.2 12 0.07 0.10 0.5 0.1 14.0 0.2 0.4 1.20 max *0.17 0.05 0 ?8 75 51 125 76 100 26 50 m *0.18 0.05 1.0 1.2 0.16 0.04 0.15 0.04 1.00 0.10 0.10 unit: mm *dimension including the plating thickness base material dimension figure g-2 tfp-100g package dimensions
886 0.13 m 0 ?10 *0.32 0.08 *0.17 0.05 3.10 max 1.2 0.2 24.8 0.4 20 80 51 50 31 30 1 100 81 18.8 0.4 14 0.15 0.65 2.70 2.4 0.20 +0.10 ?.20 0.58 0.83 0.30 0.06 0.15 0.04 unit: mm *dimension including the plating thickness base material dimension figure g-3 fp-100a package dimensions
887 0.10 16.0 0.3 1.0 0.5 0.2 16.0 0.3 3.05 max 75 51 50 26 1 25 76 100 14 0 ?8 0.5 0.08 m *0.22 0.05 2.70 *0.17 0.05 0.12 +0.13 ?.12 1.0 0.20 0.04 0.15 0.04 unit: mm *dimension including the plating thickness base material dimension figure g-4 fp-100b package dimensions
h8s/2237 series, h8s/2227 series hardware manual publication date: 1st edition, august 1998 2nd edition, december 1998 published by: electronic devices sales & marketing group semiconductor & integrated circuits group hitachi, ltd. edited by: technical documentation group ul media co., ltd. copyright ?hitachi, ltd., 1998. all rights reserved. printed in japan.

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